International Rectifier 233 Kansas Street
,
El Se
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undo
,
CA 90245 USA
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IRDCiP2005C-2
IRDCiP2005C-2: 500kHz, 30A, Dual Output,
180o Out of Phase Synchronous Buck Converter
Featuring iP2005C and IR3623M
Overview
This reference design is capable of delivering a continuous current of 30A per
channel without heatsink at an ambient temperature of 45ºC and airflow of
200LFM. Fig. 4 - Fig. 25 provide performance graphs, thermal images, and
waveforms. Fig. 1 - Fig. 3 are provided to engineers as design references for
implementing an IR3623+iP2005C solution.
The components installed on this demoboard were selected based on operation
at an input voltage of 12V (+/-10%), a switching frequency of 500kHz (+/-
15%), and an output voltage of 1.5V at channel-1 and 2.5V at channel-2. Major
changes from these set points may require optimizing the control loop and/or
adjusting the values of input/output filters in order to meet the user’s specific application requirements. Refer to iP2005C and
IR3623 datasheets for more information.
IRDCiP2005C-2 Recommended Operating Conditions
(refer to the iP2005C datasheet for maximum operating conditions)
Input voltage: 8.5V – 14.5V
Output voltage: 0.8 – 5V
Switching Freq: 500kHz
Output current: This reference design is capable of delivering a continuous current of 30A per channel without heatsink
at an ambient temperature of 45ºC and airflow of 200LFM.
Demoboard Quic k Star t Guide
Initial Settings:
VOUT1 is set to 1.5V, but can be adjusted from 0.8V to 5V by changing the values of R11 and R15 according to the following
formula: R11 = R15 = (10k * 0.8) / (VOUT1 - 0.8)
VOUT2 is set to 2.5V, but can be adjusted from 0.8V to 5V by changing the values of R12 and R16 according to the following
formula: R12 = R16 = (10k * 0.8) / (VOUT2 - 0.8)
The switching frequency is set to 500kHz, but can be adjusted by changing the value of R26. See Fig. 4 for the relationship
between R26 and the switching frequency.
7/23/2009
IRDCiP2005C-2
Power Up Procedure:
1. Apply input voltage across VIN and PGND.
2. If R45 is not installed, apply bias voltage across VDD and PGND.
3. Apply load across VOUT pads and PGND pads.
4. Toggle the SEQ (SW1) and EN (SW2) switches to the ON position.
5. Adjust load to desired level. See recommendations above.
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Demoboard Schematic
Fig. 1 Schematic
IRDCiP2005C-2
Bill of Material
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Demoboard Component Placement
Fig. 2
Top Layer (Face View)
Fig. 3
Bottom Layer (Through View)
IRDCiP2005C-2
Description of Test Points and Connectors
1.
Jumpers
Jumper Pin Name Description
SW1 EN Board Enable ( switch Up=Off, Down=On ) - Vin pin on top
SW2 SEQ Sequence ( switch Up=Off, Down=On ) - Vin pin on top
2.
Test Points/Connectors
Test Point Pin Name Description
T1 / T2 VIN / PGND Vin supply voltage
TP2 / TP28 VIN / PGND Vin supply voltage sense
T3 / T5 / T7 VOUT1 / PGND / PGND Channel 1 Output, connect to DC load
TP35 / TP33 VOUT1 / PGND Channel 1 Output sense
TP21 / TP37 VSW1 / PGND Channel 1 switch node / PGND test points
TP9 EN1 Channel 1 Enable test point
TP11 PWM1 Channel 1 PWM test point
TP19 CC1 Channel 1 error amplifier output
TP25 FB1 Channel 1 error amplifier non-inverting input
T4 / T6 / T9 VOUT2 / PGND / PGND Channel 2 Output, connect to DC load
TP36 / TP34 VOUT2 / PGND Channel 2 Output sense
TP22 / TP38 VSW2 / PGND Channel 2 switch node / PGND test points
TP10 EN2 Channel 2 Enable test point
TP12 PWM2 Channel 2 PWM test point
TP20 CC2 Channel 2 error amplifier output
TP26 FB2 Channel 2 error amplifier non-inverting input
TP7 / TP8 VDD / PGND iP2005C internal bias voltage test points
TP23 SYNC External frequency synchronization input
TP17 TRACK1 Channel 1 tracking input, pull-up to Vout3 if not used
TP18 TRACK2 Track2 test point
TP15 PGOOD1 Channel 1 Power good test point
TP16 PGOOD2 Channel 2 Power good test point
TP13 SS1 Channel 1 Soft start test point
TP14 SS2 Channel 2 Soft start test point
TP24 FAULT Fault monitor test point
3. Test points for Efficiency Measurement
Test Point Pin Name Description
TP1 / TP4 +VINS1 / -VOUTS1 Channel 1 Vin sense for efficiency measurement
TP3 / TP4 +VOUTS1 / -VOUTS1 Channel 1 Output sense for efficiency measurement
TP27 / TP6 +VINS2 / -VOUTS2 Channel 2 Vin sense for efficiency measurement
TP5 / TP6 +VOUTS2 / -VOUTS2 Channel 2 Output sense for efficiency measurement
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Test Results
Fig. 4 Relationship Between Switching Frequency and R26
VIN = 12V, VOUT1 = 1.5V, Iout1 = 10A, fsw = 500 kHz
Fig. 5 Channel-1 Power Up Sequence (C3: EN, C1: SS1, C4: VOUT1)
VIN = 12V, VOUT1 = 1.5V, Iout1 = 30A, fsw = 500 kHz
Fig. 6 Channel-1 Power Down Sequence (C3: EN, C1: SS1, C4: VOUT1)
IRDCiP2005C-2
g. 7 Channel-2 Power Up Sequence (C3: EN, C1: SS2, C4: VOUFi 2)
Fig. T2)
Fig. 9 UT1)
T
8 Channel-2 Power Down Sequence (C3: EN, C1: SS2, C4: VOU
Hiccup Mode Over Current Protection (C1: SS1, C4: Iout1, C3: VO
VIN = 12V, VOUT1 = 1.5V, fsw = 500 kHz
out2 sw
VIN = 12V, VOUT2 = 2.5V, Iout2 = 30A, fsw = 500 kHz
VIN = 12V, VOUT2 = 2.5V, I = 10A, f = 500 kHz
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Fig. 10 OUT1)
Hiccup Mode Over Current Protectio n (C1: SS1, C4: Iout1, C3: V
Fig. 11 Deadtime and Ringing at Switch Node
Fig. 12 Channel-1 Output Voltage DC Ripple
Vp-p = 18.6 mV
VIN = 12V, VOUT1 = 1.5V, Iout1 = 10A, fsw = 500 kHz
VIN = 12V, VOUT1 = 1.5V, fsw = 500 kHz
VIN = 12V, VOUT1 = 1.5V, Iout1 = 20A, fsw = 500 kHz
IRDCiP2005C-2
Fig. 13 Channel-1 Output Voltage DC Ripple
VIN = 12V, VOUT1 = 1.5V, Iout1 = 10A, fsw = 500 kHz
Vp-p = 18.8 mV
Fig. 14 Channel-2 Output Voltage DC Ripple
Fig. 15 Channel-2 Output Voltage DC Ripple
Vp-p = 23 mV
VIN = 12V, VOUT2 = 2.5V, Iout2 = 10A, fsw = 500 kHz
VIN = 12V, VOUT2 = 2.5V, Iout2 = 10A, fsw = 500 kHz
Vp-p = 25.4 mV
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Fig. 1 d by 2)
Fig. 1 d by 2)
6 Load Transient Resp o nse (C 1: V OU T1 – AC , C 2: Iout1 divide
VIN = 12V, VOUT1 = 1.5V, Iout1 = 0-30A, 0.5A/us,
fsw = 500 kHz
7 Load Transient Resp o nse (C 1: V OU T2 – AC , C 2: Iout2 divide
VIN = 12V, VOUT2 = 2.5V, Iout2 = 0-30A, 0.5A/us,
fsw = 500 kHz
IRDCiP2005C-2
fc = 72 kHz
PM = 62
Fig. 18 Bode Plot (VIN = 12V, VOUT1 = 1.5V, Iout1 = 20A)
fc = 66 kHz
PM = 62
Fig. 19 Bode Plot (VIN = 12V, VOUT2 = 2.5V, Iout2 = 20A)
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VIN = 12V, V OUT1 = 1.5V, 200LFM, fsw = 500kHz, No Heatsink
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 5 10 15 20 25 30
Chann el-1 Load C u r rent (A)
Power Loss (W)
Internal VDD, TA = 45C
Internal VDD, TA = Room
VDD = 6V, TA = 45C
VDD = 6V, TA = Room
Fig. 20 Channel-1 Po wer Loss
VIN = 12V, V OUT1 = 1.5V, 200LFM, fsw = 500kHz, No Heatsink
74%
76%
78%
80%
82%
84%
86%
88%
90%
92%
0 5 10 15 20 25 30
Channel-1 Load Current (A)
Efficiency
Internal VDD, TA = 45C
Internal VDD, TA = Room
VDD = 6V, TA = 45C
VDD = 6V, TA = Room
Fig. 21 Channel-1 Efficiency
IRDCiP2005C-2
VIN = 12V, V OUT2 = 2.5V, 200LFM, fsw = 500kHz, No Heatsink
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0 5 10 15 20 25 30
Chann el-2 Load C u r rent (A)
Power Loss (W)
Internal VDD, TA = 45C
Internal VDD, TA = Room
VDD = 6V, TA = 45C
VDD = 6V, TA = Room
Fig. 22 Channel-2 Po wer Loss
VIN = 12V, V OUT2 = 2.5V, 200LFM, fsw = 500kHz, No Heatsink
75%
77%
79%
81%
83%
85%
87%
89%
91%
93%
95%
0 5 10 15 20 25 30
Channel-2 Load Current (A)
Efficiency
Internal VDD, TA = 45C
Internal VDD, TA = Room
VDD = 6V, TA = 45C
VDD = 6V, TA = Room
Fig. 23 Channel-2 Efficiency
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Fig. 24 Thermal Image: Iout = 30A per channel, VIN = 12V, with Internal VDD, VOUT1 = 1.5V, VOUT2 = 2.5V,
TA = 45oC, fsw = 500kHz, 200LFM, No Heatsink
Fig. 25 Thermal Image: Iout = 30A per channel, VIN = 12V, VDD = 6V, VOUT1 = 1.5V, VOUT2 = 2.5V, TA =
45oC, fsw = 500kHz, 200LFM, No Heatsink
Table 1 Maximum Temperature for iP2005C Dual Output Configuration
Bias Voltage U1 U2
Internal VDD = 5.2V 103oC 108oC
External VDD = 6V 101oC 106oC
IRDCiP2005C-2
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Refer to the following application notes for detailed guidelines and suggestions when
implementing iPOWIR Technology products:
AN-1043: Stabilize the Buck Converter with Transconductance Amplifier
This paper explains how to design the voltage compensation network for Buck Converters with
Transconductance Amplifier. The design methods and equations for Type II and Type III compensation
are given.
AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s
iPowIR Technology BGA and LGA and Packages
This paper discusses optimization of the layout design for mounting iPowIR BGA and LGA packages on
printed circuit boards, accounting for thermal and electrical performance and assembly considerations.
Topics discussed include PCB layout placement, and via interconnect suggestions, as well as soldering,
pick and place, reflow, inspection, cleaning and re working recommendations.
AN-1030: Applyi ng iPOWIR Products in Your Thermal Environment
This paper explains how to use the Power Loss and SOA curves in the data shee t to validate if the
operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.
AN-1047: Graphical solution for two branch heatsinking Safe Operating Area
Detailed explanation of the dual axis SOA graph and how it is derived.
Use of this design for any application should be fully verified by the customer. International Rectifier
cannot guarantee suitability for your applications, and is not liable for any result of usage for such
applications including, without limitation, personal or property damage or violation of third party
intellectual property rights.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, Calif ornia 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7 903
