SY89871U
2.5GHz Any Diff. In-To-LVPECL
Programmable Clock Divider/Fanout Buffer
w/ Internal Termination
Precision Edge is a registered trademark of Micrel, Inc
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Oct. 1, 2013
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General Description
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8, and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output banks.
Bank A (QA) is a frequency-matched copy of the input.
Bank B (QB0, QB1) is a divided down output of the input
frequency. Bank A and Bank B maintain a matched delay
independent of the divider setting.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Typical Performance
Precision Edge®
Features
Two matched-delay outputs:
- Bank A: undivided pass-through (QA)
- Bank B: programmable divide by 2, 4, 8, 16 (QB0,
QB1)
Matched delay: all outputs have matched delay,
independent of divider setting
Guaranteed AC performance:
- >2.5GHz fMAX
- <250ps tr/tf
- <670ps tpd (matched delay)
- <15ps within-device skew
Low jitter design
- 231fs RMS phase jitter (Typ)
Power supply 3.3V or 2.5V
Unique patent-pending input termination and VT pin for
DC- and AC- coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
TTL/CMOS inputs for select and reset
100K EP compatible LVPECL outputs
Parallel programming capability
Wide operating temperature range: -40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package
Applications
OC-3 to OC-192 SONET/SDH applications
Transponders
Oscillators
SONET/SDH line cards
2
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Functional Block Diagram
Ordering Information
Part Number
Package Type
Operating Range
Package Marking
Lead Finish
SY89871UMG(2)
QFN-16
Industrial
871U with Pb-Free bar line indicator
NiPdAu Pb-Free
SY89871UMGTR(1,2)
QFN-16
Industrial
871U with Pb-Free bar line indicator
NiPdAu Pb-Free
Note:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
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Pin Configuration
Pin Description
Pin Number
Pin Name
Pin Function
1, 2, 3, 4
QB0, /QB0
QB1, /QB1
Differential Buffered Output Clocks: The differential output is a divided-down version of the
input frequency and has a matched output delay with Bank A. Divided by 2, 4, 8, or 16. See
“Truth Table.” Unused output pairs may be left floating.
5, 6
QA, /QA
Differential Buffered Undivided Output Clock.
7, 14
VCC
Positive Power Supply: Bypass with 0.1µF and 0.01µF low ESR capacitors.
8
/RESET
Output Reset: Internal 25KΩ pull-up. Logic LOW will reset the divider select. See “Truth Table.”
Input threshold is VCC/2.
12, 9
IN, /IN
Differential Input: Internal 50Ω termination resistors to VT input. See “Input Interface
Applications” section.
10
VREF-AC
Reference Voltage: Equal to VCC–1.4V (approx.), and used for AC-coupled applications. For
DC-coupled applications, VREF-AC is normally left floating. Maximum sink/source current is
0.5mA. See “Input Interface Applications” section.
11
VT
Input Termination Center-Tap: Each side of differential input pair terminates to this pin. The VT
pin provides a center tap to a termination network for maximum interface flexibility. For CML
and LVDS inputs, leave this pin floating. See “Input Interface Application” section.
13
GND
Ground.
15, 16
S1, S0
Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25KΩ pull-up resistor. Logic
HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2.
Truth Table
/RESET
S1
S0
Bank A Output
Bank B Outputs
1
0
0
Input Clock
Input Clock 2
1
0
1
Input Clock
Input Clock 4
1
1
0
Input Clock
Input Clock 8
1
1
1
Input Clock
Input Clock 16
0
X
X
Input Clock
QB = LOW, /QB = HIGH
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) .................................... –0.5V to +4.0V
Input Voltage (VIN) .................................. –0.5V to VCC+0.3V
PECL Output Current (IOUT)
Continuous. ........................................................... 50mA
Surge .................................................................. 100mA
VT Current (IVT) ........................................................ 100mA
Input Current IN, /IN (IIN) ........................................... 50mA
RREF-AC Sink/Source Current (IVREF-AC) ......................... 2mA
Lead Temperature (soldering, 20 sec.) ...................... 260°C
Storage Temperature (TS) ........................... –65°C to 150°C
Operating Ratings(2)
Supply Voltage (VCC) .............................. +2.375V to +3.63V
Ambient Temperature (TA) .......................... –40°C to +85°C
Package Thermal Resistance(3)
QFN (JA)
Still-Air ............................................................ 60°C/W
500lfpm ........................................................... 54°C/W
QFN (JB)
Junction-to-board ........................................... 38°C/W
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC
Power Supply Voltage
2.37
3.60
V
ICC
Power Supply Current
No load, max VCC.
50
75
mA
RIN
Differential Input Resistance, (IN-to-/IN)
90
100
110
Ω
VIH
Input HIGH Voltage, (IN-to-/IN)
0.1
VCC+0.3
V
VIL
Input LOW Voltage, (IN-to-/IN)
–0.3
VIH–0.1
V
VIN
Input Voltage Swing
Note 5
0.1
VCC
V
VDIFF_IN
Differential Input Voltage Swing
Notes 5, 6
0.2
V
|IIN|
Input Current, (IN-to-/IN)
Note 7
45
mA
VREF_AC
Reference Voltage
VCC–1.525
VCC–1.425
VCC–1.325
V
Notes:
1. Permanent device damage may occur if ratings in the “Absolute Maximum Ratings” sections are exceeded. This is a stress rating only and functional
operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most Negative potential on the PCB.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. See “Timing Diagram” for VIN definition. VIN (max.) is specified when VT is floating.
6. See “Typical Operating Characteristics” section for VDIFF definition.
7. Due to the internal termination (see “Input Buffer Structure” section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not
apply a combination of voltages that causes the input current to exceed the maximum limit.
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(100KEP) LVPECL DC Electrical Characteristics(8)
VCC = 3.3V 10% or 2.5V 5%; TA = –40°C to +85°C, RL = 50Ω to VCC –2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
VCC–1.145
VCC–1.020
VCC–0.895
V
VOL
Output LOW Voltage
VCC–1.945
VCC–1.820
VCC–1.695
V
VOUT
Output Voltage Swing
550
800
1050
mV
VDIFF_OUT
Differential Output Voltage Swing
1.10
1.6
2.1
V
LVTTL/ LVCMOS DC Electrical Characteristics(8)
VCC = 3.3V 10% or 2.5V 5%; TA = –40°C to +85°C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VIH
Input HIGH Voltage
2.0
V
VIL
Input LOW Voltage
0.8
V
IIH
Input HIGH Current
–125
20
µA
IIL
Input LOW Current
–300
µA
Note:
8. The circuit is designed to meet the DC specification s shown in the above table after thermal equilibrium has been established. Parameters are for
VCC = 2.5V. They vary 1:1 with VCC.
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AC Electrical Characteristics(9)
VCC = 3.3V 10% or 2.5V 5%; TA = –40C to +85C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Output Toggle Frequency
Output Swing ≥ 400mV
2.5
GHz
Maximum Input Frequency
Note10
3.2
GHz
tPD
Differential Propagation Delay
IN-to_QA or QB
Input Swing < 400mV
460
580
710
ps
Input Swing ≥ 400mV
420
550
670
ps
tSKEW
Within-Device Skew (Differential)
QB0-to-QB1
Note 11
7
15
ps
Within-Device Skew (Differential)
QA-to-QB
Note 11
12
30
ps
Part-to-Part Skew (Differential)
Note 11
250
ps
tJITTER
RMS Phase Jitter
Output = 622MHz
Integration Range 1.875MHz – 20MHz
231
fs
tRR
Reset Recovery Time
600
Ps
tr, tf
Output Rise/Fall Times
(20% to 80%)
70
150
250
ps
Notes:
9. Measured with 400mV input signal, 50% duty cycle, all loading with 50Ω to VCC−2V, unless otherwise stated.
10. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-0to-iinput 2, 4, 8, 16) can accept an input frequency
>3GHz, while Bank A will be slew rate limited.
11. Skew is measured between outputs under identical transitions.
Timing Diagram
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Typical Operating Characteristics
VCC = 3.3V, VIN = 400mV, TA = 25°C, RL = 50Ω to VCC−2V, unless otherwise stated.
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Definition of Single-Ended and Differential Swing
Figure 1a. Single-Ended Swing
Figure 1b. Differential Swing
Input Buffer Structure
Figure 2a. Simplified Differential Input Buffer
Figure 2b. Simplified TTL/CMOS Input Buffer
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Input Interface Applications
Figure 3a. DC-Coupled CML Input
Interface
Figure 3b. AC-Coupled CML Input
Interface
Figure 3c. DC-Coupled PECL Input
Interface
Figure 3d. AC-Coupled PECL Input
Interface
Figure 3e. LVDS Input Interface
Figure 3f. HSTL Input Interface
Related Product and Support Documentation
Part Number
Function
Data Sheet Link
SY89874U
2.5GHz Any Diff. In-to-LVPECL
Programmable Clock Divider and 1:2
Fanout Buffer w/Internal Termination
http://www.micrel.com/product-info/products/sy8987u.shtml
HBW
Solutions
New Products and Applications
http://www.micrel.com/product-info/products/solutions.shtml
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LVPECL Output Termination Recommendations
Figure 4a. Parallel Termination–Thevenin Equivalent
Figure 4b. Three-Resistor “Y–Termination”
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. Rb resistor sets the DC bias voltage, equal to VT. For +3.3V systems Rb = 46Ωto 50Ω. For +2.5V systems Rb = 19Ω.
4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches.
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Figure 4c. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ.
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Package Information
16-Pin Package Type (QFN)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
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© 2012 Micrel, Incorporated.
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Revision Template History
Date
Change Description/Edits by:
Rev.
8/4/10
Added new paragraph to disclaimer in boiler plate. Per Colin Sturt. M.Galvan
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