CYPRESS SEMICONDUCTOR Tn a, Cee a ee ac ET tae a i Ome es Ee = ey as a <a = se a we + Features 0.8-micron CMOS for optimum speed/power Automatic power-down e TIrLcompatible Capable of withstanding greater than 2001V electrostatic discharge Fully asynchronous operation @ MASTER CY7C132/CY7C136 easily expands data bus width to 16 or more bits using SLAVE CY7CL42/CY7C 146 BUSY output flag on CY7C132/ CY7C136; BUSY input on CY7C142/CY7C146 INT flag for port-to-port communica- tion (52-pin LCC/PLCC versions) WBE D Ea TUb23-( 2 25A9bbe2 OOOb353 7 EACYP CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS Sas SEMICONDUCTOR Functional Description The CY7C132/CY7C136/CY7C142) CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMS. Two ports are pro- vided permitting independent access to any location in memory. The CY7C132/ CY7Ci36can be utilized as either a stand- alone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual- port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit- slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and 2048 x 8 Dual-Port Static RAM output enable (OE). BUSY flags are pro- vided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin LCC and PLCC versions, BUSY sig- nals that the port is trying to access the same location currently being accessed by the oth- er port. On the LCC/PLCC versions, INT is an interrupt flag indicating that data has been placed ina unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is con- trolled independently on each port by the chip enable (CE) pins. The CY7C132/CY7C142 are available in both 48-pin DIP and 48-pin LCC. The CY7C136/CY7C146 are available in both 2-pin LCC and 52-pin PLCC. Logic Block Diagram RAL CEL CEL Aton An. VOo. Von BUSY, [1] <_ Ag ~h ry ROW is SELECT oy Ao Mewony AN Row Aca ARRAY \] SELECT Aon Awor* AL SY Aol} (7e192/70126 ONLY) Agr AND i CE. | intennuprioaic f*- CEa Be, w| Potaa7cr4s ON) |,_ oe, ba Aton ARBITRATION LoGic t- RAVA . aay, OL, inl <<$__ Notes: 4. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 2. Open drain outputs; pull-up resistor required. ,-> HUSYalt] BUSY,q en INTAl?) C192-1 Pin Configuration 2-91 wl SRAMs onCYPRESS SEMICONDUCTOR ==> CY7C132/CY7C136 =F -23- 142/CY7C146 SSF HES oucr 1-46-23-12 ene Pin Configurations (continued) , 52-Pin LCC/PLCC 48-Pin LCC Top View Top View at aN pt a ft seze8 ew8 FSB ES WEE D 2549662 0006354 9 EacyP > = SSSrrrrrrrr R a a Ae ey a lg fia S86 SB Ble 6 5 4 3 2:1: 48 47 46 45 F lo = 9Aor gagassegare pergigize3 3 z 132-3 132-4 Selection Guide 7C1322511 | 7C13230 7C132-35 7C13245 7C13255 7C136-25 7C136-30 7C136-35 7013645 713655 70142-25 7C14230 7C14235 7014245 71142~55 70146~25 7C146-30 7C146-35 70146-45 7C14655 Maximum Access Time (ns) 25 30 35 45 55 MaximumOperating Coml/Ind 170 170 120 90 90 Current(mA) Military 170 120 120 Maximum Standby Com'I/Ind 65 65 45 35 35 Current(mA) Military 65 45 45 Maximum Ratings (Abovewhich the useful life may be impaired. Foruserguidelines, Static Discharge Voltage ........ccceeevcesanes .. >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ........ seeueveee = 65Cto +150C Latch-UpCurrent .......ccsececcecseesecceeee >200mA Ambient Temperaturewith . PowerApplied .......sseseeeseessseee 55Cto +125C ~~ Operating Range Supply Voltage to Ground Potential Ambient (Pin 48 to Pin 24) ....se.sceseeeeees cesses, ~0.5V to +7,0V Range Temperature Yeo DC Voltage Applied to Outputs Commercial 0C to +70C 5V + 10% in High Z State faseone pean eeecencceeoees @=O5V tO +7,0V Industrial ~ 40C to +85C 5V + 10% DC Input Voltage ........c.ccceserseess 35V to +7.0V Miltan@ > = 3V 210% Output Current into Outputs (Low) ........0000000. 20MA ary ~ 55C to +125C -_* Notes: 3. 25-ns version available in LCC and PLCC packages only, 4. Ta is the instant on case temperatureCYPRESS SEMICONDUCTOR ube D> 25a%bbe 0006355 0 EaACcyYP. = . CY7C132/CY7C136 SS 7 Cypress T-46-23-12 CY7C142/CY7C146 Electrical Characteristics Over the Operating Rangel 7013225,300) | 7132-35 | 7C132-45,55 7C136-25,30 7C136-35 7C136-45,55 7e422830 | 7C142-35 | 7C142-45,55 | 70146-25,30 7C146-35 7C146-45,55 7 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. Max. | Units 2 : Vou Output HIGH Voltage Vcc = Min. lon = 4.0 mA 2.4 2.4 24 Vv < Vou Output LOW Voltage ToL = 4.0mA 0.4 0.4 0.4 Vv o ToL = 16.0 mAl 0.5 0.5 0.5 Vin Input HIGH Voltage 2.2 2.2 2.2, Vv Vi. Input LOW Voltage 0.8 0.8 08 Vv Ix Input Load Current GND <Vi< Vcc -5 +5 -5 +5 -5 +5 pA loz Output Leakage GND < Vo< Yea -5 +5 -5 +5 -5 +5 pA Current OutputDisabled Tos Output Short Vcc = Max., | 350 350 350 | mA CircuitCurrentll Vour = GND Ice VccOperating CE = Vit, Coml 170 120 90 | mA Supply Current Pups % en, Mil 170 120 Tspi Standby Current CE, and CBr > Vith Com'l 65 45 35 mA Both Ports, = IMAX ' TTLInputs . Mil 65 45 Tsp2 Standby Current CE or CEn > Vite, Com'l 115 90 75 | mA One Port, tive Port Outputs Open, Gy: TTLInputs " f = fax Mil 115 90 Isp Standby Current Both Ports CEy and Com'l 15 15 15 | mA Both Ports, CER > Vcc 0.2V, CMOS Inputs Vin 2. Voc 0.2V or Mil 15 15 Vin <0.2V,=0 Isp4 Standby Current One Port CE, or Com! 105 85 710 mA One Port, CER > Vcc 0.29, CMOS Inputs Vin = Vcc 0.2V or Vin <.0.2V, Mil 105 85 Active Port Outputs Open, f= fax Capacitancel?l Parameters Description Test Conditions Max. Units Cin InputCapacitance Ta = 25C, f= 1 MHz, 15 pF Cour QutputCapacitance Vcc = 5.0V 10 pF Notes: , Seethelast page of this specification for Group Asubgroup testing in- 11. AC test conditions use Von = 1.6V and VoL = 14V. formation. 12. tLzcE, tLZWwE: tHZOE: {.ZOB, tHZCE, and tyzweare tested with Cr = 6. Atf=fyrax, address and data inputs are cycling at the maximum fre- quency of read cycle of 1/t,,and using AC Test Waveforms inputlevels of GND to 3V. 7, BUSY and INT pins only. 8, Duration of the short ciccuit should not exceed 30 seconds, 9, Testedinitially and after any design or process changes that may affect these parameters. 10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse Tevels of 0 to 3.0V and output loading of the specified Tor/Iou, and 30-pF load capacitance. 5pF as in part (b) of AC Test Loads Transition is measured +:500mV form steady state voltage. 13. At any given temperature and voltage condition, trzce is less than tizce for any given device. 44, The internal write time of the memory isdefined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write andeithersignal can terminate a write by going HIGH. The datainput setup and hold timing shouldbe referencd to the risingedge of thesig- nal that terminates the write. 2-93CYPRESS SEMICONDUCTOR 4BE D e56%bb2 OO0b35b 2 EACYP a CY7C132/CY7C136 SSS 2 Crees T-46-23-12 CY7C142/CY7C146 SS] SEMICONDUCTOR AC Test Loads and Waveforms Ri 8939 Al 693 Sv Vr SV Vy ve me TI _ asia oe 30 pF | ava 5pF 70 int o192 = 132-8 . @) ) mes nUEy BUSY Output Load (C7C132/CY7C136 ONLY) Equivalent to: THEVENIN EQUIVALENT ALL INPUT PULSES 3.0V 90% 2502 oe OUTPUT 0-0 14 enp is s5n8 <5ns Switching Characteristics Overthe Operating Rangel>-10] 7C132-251] | 7C132-30 | 7C132-35 | 7132-45 | 7C13255 7C13625 | 7C136-30 | 7C136-35 | 7C13645 | 7C136-55 70142-25 | 7C142-30 | 7C142~35 | 7C14245 | 7C142-55 7146~25 7C146-30 7C146-35 7C14645 7C146--55 Parameters Description Min. | Max. Min, | Max. | Min. | Max. | Min. | Max. Min. | Max. Units READ CYCLE tre Read Cycle Time 25 30 35 45 55 ns taa Address to Data Validl!!] 25 30 35 45 55 | ns toHa Data Hold from 0 0 0 0 0 ns AddressChange tack CE LOW to Data Validl!!] 25 30 35 45 55 ns tooz OE LOW to Data Valid! #4] 15 20 20 25 25 ns tLZOE OE LOW to Low 7, 3 3 3 3 3 ns tHZOR OE HIGH to High Zl2] 15 15 20 20 25 | os tLzcK CE LOW to Low ZI] 5 5 5 5 5 ns tHZcE CE HIGH to High ZE2.13} 15 15 20 20 25 | ns teu CE LOW to Power-Up 0 0 0 0 0 ns tpp CE HIGH to Power-Down 25 25 35 35 35 ns WRITE CYCLEL!4] twc Write Cycle Time 25 30 35 45 55 ns tscr CE LOW to Write End 20 25 30 35 40 ns taw Address Set-Up to Write End 20 25 30 35 40 ns tHa Address Hold from Write End 2 2 2 2 2 ns tsa Address Set-Up to Write Start 0 0 0 0 0 ns tpwE R/W Pulse Width 15 25 25 30 30 ns tsp Data Set-Up to Write End 15 15 15 . 20 20 ns typ Data Hold from Write End 0 0 0 0 0 ns tuzwE. R/W LOW to High Z 15 15 20 20 25 ns tLZWwE R/W HIGH to Low Z 0 0 0 0 0 ns 2-94cy p > CY7C132/CY7C136 8) io pers T-46-23-12 CY7C142/CY7C146 SSS SEMICONDUCTOR Switching Characteristics Over the Operating Rangel5.19] (continued) 7C1322515] | 7013230 | 7C132-38 | 713245 | 70132~55 7C13625 | 7C136-30 | 7C136-35 | 7C136-45 | 7C136~55 7C142~25 | 7C142-30 | 7C142-35 | 7C14245 | 7C142-55 7C146-25 | 7C146-30 | 7C146-35 | 7C146-45 | 7C146-55 Parameters Description Min, | Max, | Min, | Max. | Min. | Max, | Min. | Max, | Min, | Max. | Units BUSY/INTERRUPT TIMING tBLa BUSY LOW from Address Match 20 20 20 25 30 ns tara BUSY HIGH from 20 20 20 25 30 os Address Mismatchl!5) tBLc BUSY LOW from CE LOW 20 20 20 25 30 ns tac BUSY HIGH from CE HIGHIS] 20 20 20 25 30 | ns tps Port Set Up for Priority 3 5 35 5 5 ns twapltl R/W LOW after BUSY LOW 0 0 0 0 0 ns twa R/W HIGH after BUSY HIGH |] 20 30 30 35 35 ns tppp BUSY HIGII to Valid Data 25 30 35 45 45 ns tppp Write Data Valid to Note Note Note Note Note ] ns Read Data Valid 17 17 17 17 17 twpp Write Pulse to Data Delay Note Note Note Note Note | ns 17 17 17 17 17 INTERRUPT TIMING!) twins R/W to INTERRUPT Set Time 25 25 25 35 45 ns tEINS CE to INTERRUPT Set Time 25 25 25 35 45 ns tins Address to INTERRUPT 25 25 25 35 45 ns Set Time toINR OE to INTERRUPT 25 25 25 35 45 ns Reset Timelt5) tEINR CE to INTERRUPT 25 25 25 35 45 ns Reset Timel!5] ting Address to INTERRUPF 25 25 25 35 45 ns Reset Timel!5] Notes: 15. These parameters are measured from the inputsignal changing, until 18. 52-pin LCC/PLCC versions only, the output pin goes to a high-impedance state. 19, R/W is HIGH for read cycle. 16. CY7C142/CY7C146 only. 20. Device is continuously selected, CE = Vj, and OE = Viz. 17. Awrite operation on Port A, where Port A has priority, leavesthe data 21, Address valid prior to or coincident with CE transition LOW. on Port Bs outputs undisturbed until one accesstimeafteroneofthe 29 If OB is LOW during a R/W controlled write cycle, the write pulse following: . width must be the larger of tpwe or trzwe + tsp to allow the data /O A. BUSY on Port B goes HIGH. pins to enter high impedance and for data to be placed on the bus for B. Port Bs address toggled. the required tsp. C. TE for Port B is toggled. we . . D. RAW for Port B is toggled during valid read. 23. Ifthe CE LOW transition occurs simultaneously with orafterthe RAV LOW transition, the outputs remain in a high-impedance state. Switching Waveforms Read Cycle No, 1119.20] Either PortAddress Access eS tac >| ADDRESS * toHA > tha DATAOUT _ PREVIOUS DATA VALID KXKKK XK DATA VALID Cix2-7 2-95 RESS SEMICONDUCTOR WEE D EM 2S8%bbe 00063557 4 EaCYP SRAMs |- CYPRESS SEMICONDUCTOR WbE D MM 254%bbe 0006354 & EXCYP =~ CY7C132/CY7C136 SSF cies 7 CY7C142/CY7C146 Switching Waveforms (continued) Read Cycle No, 2119. 21] oe Either PortCE/OE Access co; A o tace x pom tzce > |S vee tizce > lr ~ DATA OUT ELE LLL DATA VALID y a To 7F* G132-8 Read Cycle No.3 Read with BUSY Master: CY7C132 and 7C1361201 ADDRESS, AW, Dina ADDRESS, tac ADDRESS MATGH tpwe VALID ADDRESS MATCH Write Cycle No.1 (OE Tri-States Data I/Os Either Port) [14.22] Either Port two ADDRESS CE tewe AW tsp DATAWN DATA VALID OE NO NNN NUN OK HIGH IMPEDANCE Dorr PPT 7H. 132-10 2-96CYPRESS SEMICONDUCTOR 4oE > e546%bbe 0006359 4 EaCYP: CY7C132/CY7C136 : CY7C142/CY7C146 SEES ouctos f Switching Waveforms (continued) . 1-46-23-12 Write Cycle No. 2 (R/W Tri-States Data I/Os Either Port)[!4.23] Either Port two ADDRESS CE AAD tsp typ DATA VALID DATAw tuzwe * tiawe SIS TSS NSS OS SSS, HIGH IMPEDANCE AZLLL Le Dot PTTL LL LLL LL LL LL RO SAAAASS Gigs2-11 Busy Timing Diagram No. 1 (CE Arbitration) CE, Valid First: ADDRESS, g x ___ ADDRESS MATCH x G132-12 CEg Valid First: ADDRESS,A x ADDRESS MATCH x CE, N jt# farc i tance BUSY, 6132-13. SRAMs *258%bbe OOOb360 4 EMCYP 4bE D CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms (continued) . . Busy Timing Diagram No. 2 (Address Arbitration) T-4 6 - 2 3. si 2 Left Address Valid First: : : tac OR two ADDRESS, ADDRESS MATCH ADDRESS MISMATCH XX tps ADDRESSa kK tela e tora BUSY, 0132-14 Right Address Valid First: tac OR two "| ADDRESS MATCH > ADDRESS MISMATCH t tps ADDRESS, >< tela t tsya ADDRESS BUSY. Cis2-15 Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146) 0132-16 2--98CYPRESS SEMICONDUCTOR 4bE D e58%bbe O00b3b1 b EaCYP CY7C132/CY7C136 if sonsg CY7C142/CY7C146 2 SEMICONDUCTOR Switching Waveforms (continued) T-46~-23. 12 Interrupt Timing Diagramst!8] Left Side Sets INTR ' We ADDRESS, WRITE 7FF =< tins CE; RAW INTa ADDRESS, CER RWa OER INTR Right Side Sets INT;, C132-18 two ADDRESS, WRITE 7FE tins CER RWa INTL, Ci32-19 Left Side Clears INT, tac ADDRESS, READ 7FE CEL tine Right Side Clears INT, 192-17 INTL 132-20 |CYPRESS SEMICONDUCTOR == Ss Cypress WbE D MM 258%bb2 O00b3b2 & EaCyYP CY7C132/CY7C136 CY7C142/CY7C146 SSS SEMICONDUCTOR Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT 14 SUPPLY VOLTAGE 212 1.0 0.8 0.6 0.4 0.2 9 NORMALIZED Iec , Isa 45 5.0 5.5 SUPPLY VOLTAGE (Vv) 6.0 NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 14 NORMALIZED thy, = oR ob _ Qo 09 08 4.0 45 5.0 5.5 SUPPLY VOLTAGE (V) 60 TYPICAL POWER~ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED tag mm ON ON no & _ o 2 o a 0 10 2.0 SUPPLY VOLTAGE (V) 3.0 4.0 5.0 NORMALIZED SUPPLY CURRENT ys. AMBIENT TEMPERATURE 12 B 1.0 ec 8 os a Ww S 06 2 o4 g 02 \ SBS 0.6 55 25 125 AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 3 1.4 8 12 4 Z ea = 10 . 9 Veg = 5.0V 08 ra 0.6 85 25 125 AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 o =20.0 = =< 15.0 5 5 a 10.0 5.0 Voc = 4.5V Ta = 25C 0 0 200 400 600 800 1000 CAPACITANCE (PF) 2~-100 T-46-23-12 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 8 8 OUTPUT SOURCE CURRENT (mA) o 8 8 8 8 0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) 4.0 OUTPUT SINK CURRENT ys. OUTPUT VOLTAGE ~ = 8 3 eo 8 8 228 o Veo = 5,0V Ta = 25C OUTPUT SINK CURRENT (mA) 1.0 2.0 3.0 OUTPUT VOLTAGE (V) 4.0 NORMALIZED Icc vs. CYCLE TIME 1.25 I Veo = .0V Ta = 25C Vin = 0.5V Ioc = o AT - NORMALIZED 2 q or | 0.50 10 20 30 CYCLE FREQUENCY (MHZ) 40Bee a en BOS te ene ee 2 oo i ot ee CYPRESS SEMICONDUCTOR KE D MM 2589662 0006363 T EmCypP CY7C132/CY7C136 CYPRESS CY7C142/CY7C146 SSS = = SEMICONDUCTOR =: Ordering Information T-46-23-12 : Speed Ordering Code eee Operating Seo Ordering Code ee Operating " y 25 | CY7C13225LC 168 | Commercial 25 | CY7C136251C 169 | Commercial E aor 30. | CY7C13230DC D26 | Commercial CY7C136-25LC 169 o Fe CY7C13230LC L8 30 | CY7C13630IC 369 | Commercial = CY7C13230PC P25 CY7C13630LC L69 & ] CY7C13230DI D26 | Industrial CY7C1363031 369 | Industrial 4 C7C13230PI P25 35. | CY7C136353C 369 | Commercial ? 35 | CY7C13235DC D26__| Commercial CY7C13635LC L69 CY7C13235LC L68 CY7C1363591 369 | Industrial = CY7C13235PC P25 CY7C13635LMB 169 | Military 3 CY7C132-35DI D26 Industrial 45 CY7C136-453C 369 Commercial 3 CY7C13235P1 P25 CY7C13645LC L69 4 CY7C13235DMB D26_| Military CY7C1364531 369 | Industrial ; CY7C13235EMB E78 CY7C13645LMB L69 | Military z CY7C13235LMB L68 55 CY7C136553IC J69 Commercial 3 = 45 | CY7CI3245DC D26_| Commercial CY7C13655LC L069 iB i CY7C13245LC L68 CY7C13655I1 J69 | Industrial F CY7C13245PC P25 CY7C13655LMB L69 | Military : CY7C13245D1 D26 Industria! i CY7C13245P1 P25 Ff CY7C13245DMB D26_| Military . F CY7C13245FMB F78 ; CY7C13245LMB L68 Fs 55 | CY7C13255DC D26 | Commercial 3 CY7Ci3255LC L68 CY7C13255PC P25 CY7C132-55DI D26 Industrial 4 f CY7C13255PI P25 CY7Ci3255DMB D26 | Military CY7C13255FMB F78 i CY7C13255LMB L68 z 2-101CYPRESS SEMICONDUCTOR WEE D MM 2545bbe OOObSEY 1 EACYP = CY7C132/CY7C136 Sa =, T-46-23-12 CY7C142/CY7C146 CYPRESS Ses SEMICONDUCTOR Ordering Information (continued) Speed | Package | Operating Speed Package | Operating (ns) Ordering Code Type Range (us) Ordering Code Type Range 25 CY7C14225LC L68 Commercial 25 CY7C1i4625IC J69 Commercial 30 CY7Ci4230DC D26 Commercial CY7Ci4625LC L69 I CY7C142-30LC L68 30 CY7C146303C J69 Commercial CY7C14230PC P25 CY7C146-30LC L69 CY7C142-30DI D26 Industrial CY7C14630]1 369 Industriai | CY7C142-30PI P25 35 CY7C14635IC 569 Commercial 35 CY7C142~35DC D26 Commercial CY7C14635LC L69 CY7C14235LC L68 CY7C14635]1 J69 Industrial CY7C14235PC P25 CY7C14635LMB L69 Military CY7C14235DI D26 Industrial 45 CY7C14645IC J69 Commercial * CY7C142--35PI P25 CY7C1i4645LC L69 CY7C14235DMB D26 Military CY7C146-45]1 169 Industrial CY7Ci4235FMB F78 CY7C14645LMB L69 Military CY7C142-35LMB L68 55 CY7C146553IC J69 Commercial 45 CY7C14245DC D26 Commercial CY7C146--55LC L69 CY7C14245LC L68 CY7C146S5J1 J69 Industrial CY7C142~45PC P25 CY7C146-55LMB L69 Military CY7C142-45DI D26 Industrial CY7C14245PI P25 CY7C14245DMB D26_| Military CY7C14245FMB F78 CY7C14245LMB L68 55 CY7C142-S55DC D26 Commercial CY7C14255LC L68 CY7C142-55PC P25 CY7C142-S5DI D26 Industrial CY7C142S5PI P25 CY7C14255DMB D26 Military CY7C142-55FMB F78 CY7C14255LMB L68 2-102CYPRESS SEMICONDUCTOR WBE > Bal 256%bbe O006365 3 EMCYP CY7C132/CY7C136 T-46-23.12 CY7C142/CY7C146 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters Subgroups Vou 1,2,3 VoL 1, 2,3 Vin 1, 2,3 Vin, Max. 1,2,3 Ix 1,2,3 loz 1,2,3 Icc 1,2,3 Isnt 1,2,3 Ispa 1,2,3 Isp3 1, 2,3 Ispa 1,2,3 Switching Characteristics Parameters | Subgroups Parameters Subgroups READ CYCLE BUSY/INTERRUPT TIMING trc 7, 8, 9, 10, 14 tBLa 7,8, 9, 10, 11 CAA 7, 8,9, 10, 11 tBHA 7, 8, 9, 10, 11 tack 7, 8, 9, 10, 11 tata 7,8, 9, 10, 11 (poz 7, 8, 9, 10, 11 tpuc 7, 8, 9, 10, 11 WRITE CYCLE tps 7, 8, 9, 10, 11 twe 7, 8, 9, 10, 11 twins 7, 8, 9, 10, 11 tscE 7, 8,9, 10, 11 tEIns 7, 8, 9, 10, 11 taw 7, 8, 9, 10, 11 tins 7, 8, 9, 10, 11 tHa 7, 8, 9, 10, 11 toINR 7, 8, 9, 10, 11 tsa 7, 8, 9, 10, 11 tEINR 7, 8, 9, 10, 11 tpwe 7, 8, 9, 10, 11 tr 7,8, 9, 10, 11 tsp 7, 8, 9, 10, 11 BUSY TIMING tHD 7,8, 9, 10, 11 twa] 7,8, 9, 10, 11 twu 7, 8, 9, 10, 11 tppp 7,8, 9, 10, 11 Note: 24, CY7C142/CY7C146 only. Document #: 38-00061-F 2-103 ae SRAMs ah