1. General description
The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 24 segments and can easily be cascaded
for larger LCD applications. The PCF8566 is compatible with most microprocessors or
microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
2. Features
nSingle-chip LCD controller/driver
n24 segment drives:
uUp to twelve 7-segment numeric characters including decimal pointer
uUp to six 14-segment alphanumeric characters
uAny graphics of up to 96 elements
nVersatile blinking modes
nNo external components required (even in multiple device applications)
nSelectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
nSelectable display bias configuration: static, 12 or 13
nInternal LCD bias generation with voltage-follower buffers
n24 ×4-bit RAM for display data storage
nAuto-incremented display data loading across device subaddress boundaries
nDisplay memory bank switching in static and duplex drive modes
nLCD and logic supplies may be separated
n2.5 V to 6 V power supply range
nLow power consumption
nPower-saving mode for extremely low power consumption in battery-operated and
telephone applications
nI2C-bus interface
nTTL and CMOS compatible
nCompatible with any 4, 8 or 16-bit microprocessor or microcontroller
nMay be cascaded for large LCD applications (up to 1536 segments possible)
nCascadable with 40-segment LCD driver PCF8576C
nOptimized pinning for plane wiring in both and multiple PCF8566 applications
nSpace-saving 40-lead plastic very small outline package (VSO40; SOT158-1)
nManufactured in silicon gate CMOS process
PCF8566
Universal LCD driver for low multiplex rates
Rev. 07 — 25 February 2009 Product data sheet
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 2 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
3. Ordering information
[1] Dark-green version.
[2] Chip in tray for chip on board.
4. Marking
Table 1. Ordering information
Type number Package
Name Description Version
PCF8566P DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
PCF8566T VSO40 plastic very small outline package; 40 leads SOT158-1
PCF8566TS[1] VSO40 plastic very small outline package; 40 leads SOT158-1
PCF8566U[2] PCF8566U wire bond die; 40 bonding pads;
2.5 × 2.91 × 0.381 mm PCF8566U
Table 2. Marking codes
Type number Marking code
PCF8566P PCF8566P
PCF8566T PCF8566T
PCF8566TS PCF8566TS
PCF8566U PC8566-1
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 3 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
5. Block diagram
Fig 1. Block diagram of PCF8566
mgg383
LCD
VOLTAGE
SELECTOR
12
5
TIMING BLINKER
OSCILLATOR
INPUT
FILTERS I2C-BUS
CONTROLLER
POWER-
ON
RESET
CLK 4
SYNC 3
OSC 6
11
SCL 2
SDA 1
SA0
10
DISPLAY
CONTROLLER
COMMAND
DECODER
BACKPLANE
OUTPUTS
13
BP0
14
BP2
15
BP1
16
BP3
INPUT
BANK
SELECTOR
DISPLAY
RAM
24 × 4 BITS
OUTPUT
BANK
SELECTOR
DATA
POINTER
SUB-
ADDRESS
COUNTER
DISPLAY SEGMENT OUTPUTS
DISPLAY LATCH
SHIFT REGISTER
17 to 40
S0 to S23
A0
7
A1
8
A2
9
PCF8566
LCD BIAS
GENERATOR
VSS
VLCD
VDD
R
R
R
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 4 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
Fig 2. Pin configuration for PCF8566
PCF8566
SDA S23
SCL S22
SYNC S21
CLK S20
VDD S19
OSC S18
A0 S17
A1 S16
A2 S15
SA0 S14
VSS S13
VLCD S12
BP0 S11
BP2 S10
BP1 S9
BP3 S8
S0 S7
S1 S6
S2 S5
S3 S4
001aai338
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
21
24
23
26
25
40
39
38
37
36
35
34
33
32
31
30
29
28
27
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 5 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
6.2 Pin description
Fig 3. Pin configuration for PCF8566U
mbh783
PCF8566U
36 37 38 39 40 54321
25 24 23 22 21 16
15
14
13
12
11
10
17181920
9
8
7
6
30
31
32
33
34
35
26
27
28
29
S23
S22
S21
S20
S19
VDD
CLK
SYNC
SCL
SDA
S5
S7
S8
S6
SA0
A2
A1
A0
OSC
S16
S17
S18
VSS
VLCD
BP0
BP2
BP1
S11
S10
S9
S12
S14
S13
S15
BP3
S0
S1
S2
S3
S4
Table 3. Pin description
Symbol Pin Description
SDA 1 I2C-bus data input and output
SCL 2 I2C-bus clock input and output
SYNC 3 cascade synchronization input and output
CLK 4 external clock input and output
VDD 5 positive supply voltage[1]
OSC 6 oscillator select
A0 7 I2C-bus subaddress inputs
A1 8
A2 9
SA0 10 I2C-bus slave address bit 0 input
VSS 11 logic ground
VLCD 12 LCD supply voltage
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 6 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
[1] The substrate (rear side of the die) is wired to VDD but should not be electrically connected.
7. Functional description
The PCF8566 is a versatile peripheral device designed to interface any
microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static
or multiplexed LCD containing up to 4 backplanes and up to 24 segments.
The display configurations possible with the PCF8566 depend on the number of active
backplane outputs required. Display configuration selection is shown in Table 4. All of the
display configurations given in Table 4 can be implemented in the typical system shown in
Figure 4.
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCF8566.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application.
BP0 13 LCD backplane outputs
BP2 14
BP1 15
BP3 16
S0 to S23 17 to 40 LCD segment outputs
Table 3. Pin description
…continued
Symbol Pin Description
Table 4. Display configurations
Backplanes Elements 7-segment numeric 14-segment numeric Dot matrix
Digits Indicator
symbols Characters Indicator
symbols
4 96 12 12 6 12 96 (4 × 24)
3729941672 (3× 24)
248663648 (2× 24)
1243311024
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 7 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.1 Power-on reset
At power-on the PCF8566 resets to the following starting conditions:
All backplane outputs are set to VDD
All segment outputs are set to VDD
Drive mode 1:4 multiplex with 13bias is selected
Blinking is switched off
Input and output bank selectors are reset (as defined in Table 8)
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared
Do not transfer data on the I2C-bus after a power-on for at least 1 ms to allow the reset
action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (Voper) is obtained from VDD VLCD. The LCD voltage may be
temperature compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between VDD and VLCD. The center resistor can be
switched out of the circuit to provide a 12 bias voltage level for the 1:2 multiplex
configuration.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by
mode-set commands from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D), are given in Table 5.
Fig 4. Typical system configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
OSC
1 17 to 40
13 to 16
2
678
512
91011
24 segment drives
4 backplanes
LCD PANEL
(up to 96
elements)
PCF8566
A0 A1 A2 SA0
VDD
VDD VLCD
VSS
VSS
mgg385
R trise
2 Cbus
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 8 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD >3V
th.
Multiplex drive modes of 1:3 and 1:4 with 12bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by , where the values for a are
a = 1 for 12 bias
a = 2 for 13 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
(1)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 3 for 1:3 multiplex
n = 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with the equation:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from the equation:
(3)
Using Equation 3, the discrimination for an LCD drive mode of
1:3 multiplex with 12bias is
Table 5. Preferred LCD drive modes: summary of characteristics
LCD drive mode Number of: LCD bias
configuration
Backplanes Bias levels
static 1 2 static 0 1
1:2 multiplex 2 3 120.354 0.791 2.236
1:2 multiplex 2 4 130.333 0.745 2.236
1:3 multiplex 3 4 130.333 0.638 1.915
1:4 multiplex 4 4 130.333 0.577 1.732
V
off
RMS
()
V
LCD
--------------------------
V
on
RMS
()
V
LCD
-------------------------
DV
on
RMS
()
V
off
RMS
()
--------------------------=
1
1a
+
-------------
Von RMS()
1
n
---n
1
()
1
1a
+
-------------


×
2
+
n
------------------------------------------------------------
V
LCD
=
Voff RMS()
a
2
2a
n+()
n
1a
+()
2
×
---------------------------------
V
LCD
=
Von RMS()
V
off RMS()
------------------------
a1
+()
2
n
1
()+
a1
()
2
n
1
()+
--------------------------------------------=
3 1.732
=
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 9 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
1:4 multiplex with 12bias is
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
1:3 multiplex (12 bias):
1:4 multiplex (12 bias):
These compare with when 13 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
21
3
----------
1.528
=
V
LCD
6V
off
RMS
()
×
2.449V
off
RMS
()
==
V
LCD
43
×()
3
----------------------
2.309V
off
RMS
()
==
V
LCD
3V
off
RMS
()
=
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 10 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 5.
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = VSn+1(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 5. Static drive mode waveforms
mgl745
VSS
VLCD
VSS
VLCD
VSS
VLCD
VLCD
VLCD
VLCD
VLCD
state 1 0 V
BP0
Sn
Sn+1
state 2 0 V
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 1
(on) state 2
(off)
Tfr
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 11 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8566 allows the use of 12bias or 13bias (see Figure 6 and Figure 7).
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.354VLCD
Fig 6. Waveforms for the 1:2 multiplex drive mode with 12 bias
mgl746
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 2
state 1
VSS
VLCD
VLCD / 2
VSS
VSS
VLCD
VLCD
VSS
VLCD
VLCD
VLCD
0 V
0 V
VLCD / 2
VLCD / 2
VLCD / 2
VLCD
VLCD
VLCD / 2
VLCD / 2
Sn
Sn+1
Tfr
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 12 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.745VLCD
Vstate2(t) = VSn(t) VBP1(t)
Voff(RMS) = 0.333VLCD.
Fig 7. Waveforms for the 1:2 multiplex drive mode with 13 bias
mgl747
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
VLCD
VLCD
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
Sn
Sn+1
Tfr
VSS
VLCD
2VLCD / 3
VLCD / 3
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 13 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure 8.
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 8. Waveforms for the 1:3 multiplex drive mode with 13 bias
mgl748
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
(a) Waveforms at driver.
BP2
Sn
Sn+1
Sn+2
Tfr
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
VLCD
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
VLCD
VSS
VLCD
2VLCD / 3
VLCD / 3
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 14 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.4.4 1:4 multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 9.
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 9. Waveforms for the 1:4 multiplex mode with 13 bias
mgl749
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
BP2
(a) Waveforms at driver.
BP3
Sn
Sn+1
Sn+2
Sn+3
Tfr
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
VLCD
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
VLCD
VSS
VLCD
2VLCD / 3
VLCD / 3
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 15 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8566 are timed by the frequency
fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency
fclk(ext).
The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate
for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data
rate of 100 kHz, fclk should be chosen to be above 125 kHz.
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the
output from pin CLK is the clock signal for any cascaded PCF8566s or PCF8576s in the
system.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device. Removing the clock,
freezes the LCD in a DC state.
7.6 Timing
The timing of the PCF8566 sequences the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8566s in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency (see
Table 6). The frame frequency is set by the mode set commands when an internal clock is
used or by the frequency applied to the pin CLK when an external clock is used.
[1] The possible values for fclk see Table 20.
[2] For fclk = 200 kHz.
[3] For fclk = 31 kHz.
The ratio between the clock frequency and the LCD frame frequency depends on the
mode in which the device is operating. In the power-saving mode the reduction ratio is six
times smaller; this allows the clock frequency to be reduced by a factor of six. The
reduced clock frequency results in a significant reduction in power dissipation.
Table 6. LCD frame frequencies [1]
PCF8566 mode Frame frequency Nominal frame frequency (Hz)
normal mode 69 [2]
power saving mode 65 [3]
ffr
f
clk
2880
-------------
=
ffr
f
clk
480
----------
=
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 16 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
The lower clock frequency has the disadvantage of increasing the response time when
large amounts of display data are transmitted on the I2C-bus. When a device is unable to
process a display data byte before the next one arrives, it holds the SCL line LOW until the
first display data byte is stored. This slows down the transmission rate of the I2C-bus but
no data loss occurs.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and one column of the display RAM.
7.8 Shift register
The shift register transfers display information from the display RAM to the display register
while previous data is displayed.
7.9 Segment outputs
The LCD drive section includes 24 segment outputs S0 to S23 which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data resident in the display register. When less than
24 segment outputs are required, the unused segment outputs should be left open-circuit.
7.10 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left as an
open-circuit.
In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.11 Display RAM
The display RAM is a static 24 ×4-bit RAM which stores LCD data. Logic 1 in the RAM bit
map indicates the on-state of the corresponding LCD segment; similarly, logic 0 indicates
the off-state. There is a direct relationship between the RAM addresses and the segment
outputs, and between the individual bits of a RAM word and the backplane outputs. The
first RAM row corresponds to the 24 segments operated with respect to backplane BP0
(see Figure 10). In multiplexed LCD applications, the segment data of rows 1 to 4 of the
display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively.
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 17 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
When display data is transmitted to the PCF8566 the display bytes received are stored in
the display RAM based on the selected LCD drive mode. An example of a 7-segment
numeric display illustrating the storage order for all drive modes is shown in Figure 11.
The RAM storage organization applies equally to other LCD types.
The following applies to Figure 11:
Static drive mode: the eight transmitted data bits are placed in row 0 to eight
successive display RAM addresses.
1:2 multiplex drive mode: the eight transmitted data bits are placed in row 0 and 1 to
four successive display RAM addresses.
1:3 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1 and 2 of
three successive addresses, with bit 2 of the third address left unchanged. This last bit
can, if necessary, be controlled by an additional transfer to this address but avoid
overriding adjacent data because always full bytes are transmitted.
1:4 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1, 2 and
3 to two successive display RAM addresses.
7.12 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load data pointer command (see Table 13). After this, the data byte is
stored starting at the display RAM address indicated by the data pointer (see Figure 11).
Once each byte is stored, the data pointer is automatically incremented based on the
selected LCD configuration.
The contents of the data pointer are incremented as follows:
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
Fig 10. Display RAM bit map showing the direct relationship between display RAM
addresses and segment outputs and between bits in a RAM word and backplane
outputs
0
0
1
2
3
1234 1920212223
display RAM addresses (columns)/segment outputs (S)
display RAM bits
(rows)/
backplane outputs
(BP)
mgg389
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 18 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
x = data bit unchanged
Fig 11. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
mgl751
Sn+2
Sn+1
Sn+7
Sn
Sn
Sn+3
Sn+5
Sn+2
Sn+3
Sn+1
Sn+1
Sn+1
Sn+2
Sn
Sn+6
Sn
Sn+4
DP
DP
DP
DP
a
fb
g
ec
d
a
fb
g
ec
d
a
fb
g
ec
d
a
fb
g
ec
d
BP0
BP0
BP0
BP1
BP1
BP2
BP1
BP2
BP3
BP0
n
c
x
x
x
0
1
2
3
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
n1 n2 n3 n4 n5 n6 n7
bit/
BP
n
a
b
x
x
0
1
2
3
f
g
x
x
e
c
x
x
d
DP
x
x
n1 n2 n3
bit/
BP
n
b
DP
c
x
0
1
2
3
a
d
g
x
f
e
x
x
n1 n2
bit/
BP
n
a
c
b
DP
0
1
2
3
f
e
g
d
n1
bit/
BP
cbaf gedDP
abf gecdDP
bDPcadgf e
acbDPf egd
MSB LSB
MSB LSB
MSB LSB
MSB LSB
drive mode
static
1:2
multiplex
1:3
multiplex
1:4
multiplex
LCD segments LCD backplanes display RAM filling order transmitted display byte
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 19 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.13 Sub-address counter
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter match
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is
defined by the device select command (see Table 14 and Table 21). If the contents of the
subaddress counter and the hardware subaddress do not match then data storage is
blocked but the data pointer will be incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8566 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 14th
display data byte transmitted in 1:3 multiplex mode).
7.14 Output bank selector
The output bank selector (see Table 15), selects one of the four bits per display RAM
address for transfer to the display register. The actual bit selected depends on the LCD
drive mode in operation and on the instant in the multiplex sequence.
In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially
by the contents of bit 1, bit 2 and then bit 3.
In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially.
In 1:2 multiplex mode: bits 0 and 1 are selected.
In the static mode: bit 0 is selected.
The PCF8566 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank select command may request the contents of
bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive mode,
the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables
preparation of display information in an alternative bank and the ability to switch to it once
it has been assembled.
7.15 Input bank selector
The input bank selector loads display data into the display RAM based on the selected
LCD drive configuration. Using the bank select command, display data can be loaded in
bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode. The input bank
selector functions independently of the output bank selector.
7.16 Blinker
The display blinking capabilities of the PCF8566 are very versatile. The whole display can
be blinked at frequencies selected by the blink command. The blinking frequencies are
integer fractions of the clock frequency; the ratios between the clock and blinking
frequencies depend on the mode in which the device is operating (see Table 7).
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 20 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
An additional feature is for an arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. Using the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blinking frequency. This mode can also be
specified by the blink select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display needs to be blinked at a frequency other than the nominal blinking
frequency, this can be done using the mode set command to set and reset the display
enable bit E at the required rate (see Table 9).
8. Basic architecture
8.1 Characteristics of the I2C-bus
The I2C-bus provides bidirectional, two-line communication between different IC or
modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When
connected to the output stages of a device, both lines must be connected to a positive
supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in Figure 12.
Table 7. Blink frequencies
Blinking mode Normal operating
mode ratio Power saving mode
ratio Blink frequency
off - - blinking off
1 2 Hz
2 1 Hz
3 0.5 Hz
fblink
f
clk
92160
----------------
=fblink
f
elk
15360
----------------
=
fblink
f
clk
184320
--------------------
=fblink
f
clk
30720
----------------
=
fblink
f
clk
368640
--------------------
=fblink
f
clk
61440
----------------
=
Fig 12. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 21 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
8.1.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 13.
8.1.2 System configuration
A device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is illustrated in
Figure 14.
8.1.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse. (See
Figure 15).
Acknowledgement on the I2C-bus is illustrated in
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
Fig 13. Definition of START and STOP conditions
mbc622
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
Fig 14. System configuration
mga807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 22 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
A master receiver must signal an end-of-data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
master receiver must leave the data line HIGH during the 9th pulse to not
acknowledge. The master will now generate a STOP condition.
8.1.4 PCF8566 I2C-bus controller
The PCF8566 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8566 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, the transferred command data and the hardware subaddress.
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device applications
A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two
devices with a common I2C-bus slave address have the same hardware subaddress.
In the power-saving mode it is possible that the PCF8566 is not able to keep up with the
highest transmission rates when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW until its internal operations are
completed. This is known as the clock synchronization feature of the I2C-bus and serves
to slow down fast transmitters. Data loss does not occur.
8.1.5 Input filter
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.2 I2C-bus protocol
Two I2C-bus 7 bit slave addresses (0111 110 and 0111 111) are reserved for the
PCF8566. The least significant bit after the slave address is bit R/W. The PCF8566 is a
write-only device. It will not respond to a read access, so this bit should always be logic 0.
The second bit of the slave address is defined by the level tied at input SA0.
Fig 15. Acknowledgement on the I2C-bus
mbc602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 23 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
Two displays controlled by PCF8566 can be recognized on the same I2C-bus which
allows:
Up to 16 PCF8566s on the same I2C-bus for very large LCD applications (see
Section 13)
The use of two types of LCD multiplex on the same I2C-bus
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the PCF8566 slave
addresses. All PCF8566s with the same SA0 level acknowledge in parallel to the slave
address. All PCF8566s with the alternative SA0 level ignore the whole I2C-bus transfer.
After acknowledgement, one or more command bytes (m) follow which define the status of
the addressed PCF8566s. The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes (n) may follow. These display
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data is directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF8566. After the last display byte, the I2C-bus master issues a STOP condition (P).
Fig 16. Slave address structure
Fig 17. I2C-bus protocol
001aai455
S
A
0
011111 0
slave address
1 byte
R/W
mgg390
S
A
0
S011111 0AC COMMAND APADISPLAY DATA
slave address
acknowledge by
all addressed
PCF8566s
acknowledge
by A0, A1 and A2
selected
PCF8566 only
m 1 byte(s) n > 0 byte(s)1 byte update data pointers
and if necessary,
subaddress counter
R/W
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Product data sheet Rev. 07 — 25 February 2009 24 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
8.3 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. All available
commands carry a continuation bit C in their most significant bit position as shown in
Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will
also represent a command. If this bit is reset, it indicates that the command byte is the last
in the transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8566 are defined in Table 8.
8.3.1 Mode set command
(1) C = 0; last command.
(2) C = 1; commands continue.
Fig 18. General format of byte command
msa833
REST OF OPCODE
C
MSB LSB
Table 8. Definition of PCF8566 commands
Command Opcode Reference Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mode set C 1 0 LP E B M1 M0 Section 8.3.1 defines LCD drive mode, LCD bias
configuration, display status and
power dissipation mode
Load data
pointer C 0 0 P4P3P2P1P0Section 8.3.2 data pointer to define one of 24
display RAM addresses
Device select C 1100A2A1A0
Section 8.3.3 define one of eight hardware
subaddresses
Bank select C 11110I O
Section 8.3.4 bit I: defines input bank selection
(storage of arriving display data);
bit O: defines output bank selection
(retrieval of LCD display data)
Blink C 1110ABF1BF0
Section 8.3.5 defines the blink frequency and blink
mode
Table 9. LCD drive mode command bit description
LCD drive mode Bit
Drive mode Backplane M1 M0
static BP0 0 1
1:2 BP0, BP1 1 0
1:3 BP0, BP1. BP2 1 1
1:4 BP0, BP1. BP2, BP3 0 0
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Product data sheet Rev. 07 — 25 February 2009 25 of 48
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
[1] The possibility to disable the display allows implementation of blinking under external control.
8.3.2 Load data pointer command
8.3.3 Device select command
8.3.4 Bank select command
[1] The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.
Table 10. LCD bias configuration command bit description
LCD bias Bit B
13 bias 0
12 bias 1
Table 11. Display status command bit description[1]
Display status Bit E
disabled (blank) 0
enabled 1
Table 12. Power dissipation mode command bit description
Display status Bit LP
normal mode 0
power saving mode 1
Table 13. Load data pointer command bit description
Description Bit
5 bit binary value, 0 to 23 P4 P3 P2 P1 P0
Table 14. Device select command bit description
Description Bit
3 bit binary value, 0 to 7 A2 A1 A0
Table 15. Bank select command[1]
Bank Mode Bit Value
Static 1:2 MUX
Input bank
RAM bit 0 RAM bits 0 and 1 I 0
RAM bit 2 RAM bits 2 and 3 1
Output bank
RAM bit 0 RAM bits 0 and 1 O 0
RAM bit 2 RAM bits 2 and 3 1