IM1644-12 - Innovative Microdevices, Inc.

Features:

Form, fit and function compatible with the MK48T32

and DS1644 Timekeeping RAM.

Integrated NV SRAM, real time clock, crystal, power

fail control circuit and lithium energy source.

Standard JEDEC bytewide 32K X 8 static RAM

pinout.

Clock registers are accessed identical to the static

RAM. These registers are resident in the eight top

RAM locations.

Totally nonvolatile with over the 10 years of opera-

tion in the absence of power.

Access time of 120 ns .

Clock software provided

BCD coded year , month, date, day, hours, minutes

and seconds

Power fail write protection allows for +10% Vcc

power supply tolerance

Year 2000 compliant

Battery low warning available

DESCRIPTION

The IM1644 is an 32K X 8 nonvolatile static RAM

with a full function real time clock which are both

accessible in a bytewide format. The nonvolatile time

keeping RAM is pin and function equivalent to any

JEDEC standard 32K X 8 SRAM. The device can

also be easily substituted in ROM, EPROM,

EEPROM sockets providing read/write nonvolatility

and the addition of the real time clock function. The

real time clock information resides in the eight up-

permost RAM location. The RTC registers contain

year, month, date, day , hours, minutes and seconds

data in 24 BCD format.

Correction for the day of the month and

leap year are made automatically. The RTC clock

registers are double buffered to avoid access of

incorrect data that can occur during clock updates

cycles. The double buffered system also prevents

time loss as the timekeeping countdown unabated

by access to time register data. The IM1644 also

contains its own power fail circuitry which dese-

lects the device when the Vcc supply is in an out of

tolerance condition. This feature prevents loss of

data from unpredictable system operation brought

on by low Vcc as errant access and update cycles

are avoided.

1 28

2 27

3 26

4 25

5 24

6 23

7 22

8 21

9 20

10 19

11 18

12 17

13 16

14 15

PIN NAMES

A0 - A14 Address Inputs

CE Chip Enable

OE Output Enable

WE Write Enabel

Vcc +5 Volts

Gnd Ground

I/O0 - I/O7 Data Input/Output

PIN CONFIGRATION

A14 VCC

A12 WE

A7 A13

A6 A8

A5 A9

A4 A11

A3 OE

A2 A10

A1 CE

A0 I/O7

I/O0 I/O6

I/O1 I/O5

I/O2 I/O4

GND I/O3

INNOVATIVE MICROTECHNOLOGY INC.Phone/Fax-440-322-8083.Website:www.innovativemicrotechnology.com

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

Vcc

VBAT

POWER MONITOR,

SWITCHING AND

WRITE PROTECTION

OSCILLATOR AND

CLOCK COUNTDOWN

CHAIN

POWER GOOD

CLOCK

REGISTER

32K X 8 NV SRAM

CE

WE

OE

32.768 KHz

A0 - A14

I/O0 - I/O7

BLOCK DIAGRAM

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

Actual life expectancy of the IM1644 will be much

longer than 10 years since no internal lithium battery

energy is consumed when Vcc is present. In fact, in

most applications, the life expectancy of the IM1644

will be approximately equal to the shelf life (expected

useful life of the lithium battery with no load attached)

of the lithium battery which may prove to be as long

as 20 years.

BATTERY LOW WARNING

The IM1644 automatically performs battery volt-

age monitoring upon power-up and at factory pro-

grammed time intervals of approximately 24 hours.

The Battery Low (BL) bit, Bit D4 of Flags Register

1FF0h will be asserted if the battery voltage is found

to be less than approximately 2.5V. The BL bit will

remain asserted until completion of battery replace-

ments and subsequent battery low monitoring test

either during the next power-up sequence or the

next scheduled 24 hours interval.

If a battery low is generated during a

power-up sequence, this indicated that the battery

is below approximately 2.5V and may not be able

to maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct.

Afresh battery should be installed.

If a battery low indication is generated dur-

ing 24 hour interval check, this indicates that the

battery is near end of life. However, data is not com-

promised due to the fact that a nominal Vcc is

supplied.

The clock only monitors the battery when

a nominal Vcc is applied to the device. Thus appli-

cations which require extensive durations in the bat-

tery backup mode should be powered-up periodi-

cally (at least once every few months) in order for

this technique to be beneficial. Additionally, if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

INTERNAL BATTERY LONGEVITY

The IM1644 has a self contained lithium power

source that is designed to provide energy for clock

activity, and clock and RAM data retention when the

Vcc supply is not present. The capability of this in-

ternal power supply is sufficient to power the IM1644

continuously for the life of the equipment in which it

is installed. For specification purposes, the life ex-

pectancy is 10 years at 27oC with the internal clock

oscillator running in the absence of Vcc power. The

IM1644 is shipped from INNOVATIVE with the clock

oscillator turned off, so the expected life should be

considered to start from the time the clock oscillator

is first turned on.

WRITING DATA TO RAM OF CLOCK

The IM1644 is in the write mode whenever WE, CE

are in their acitve state. The start of a write is refer-

enced to the latter occurring transtion of WE, CE .

The address must be held valid throughout the cycle.

CE or WE must return inactive for a minimum of tWR

prior to the initiation of another read or write cycle.

Data in must be valid tDS prior to the end of write and

remain valid for tDH afterward. In a typical applica-

tion, the OE signal will be high during a write cycle.

However, OE can be active provided that care is

taken with the data bus to avoid bus contention. If

OE is low prior to WE transition low the data bus can

become active with read data defined by the address

inputs. A low transition on WE will then disable the

outputs tWEZ after WE goes active.

RETRIEVING DATA FROM RAM OR CLOCK

The IM1644 is in the read mode whenever

WE is high, CE is low . The device architecture al-

lows ripple through access to any of the address lo-

cations in the NV SRAM. Valid data will be available

at the DQ pins within t AA after the last address input

is stable, providing that the CEand OE access times

are satisfied. If the CE orOE access times are not

met, valid data will be available at the latter of chip

enable access (tCEA) or at output enable access time

(tOEA). The state of the input/output pins (DQ) is con-

trolled by CE and OE. If the outputs are activated

before tAA, the data address inputs are changed while

CE and OE remain valid, output data wil remain valid

for output data hold time (t OH) but will then go inde-

terminate until the next address access.

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

CLOCK OPERATIONS

Reading the clock

Updates to the TIMEKEEPER regis-

ters should be halted before clock data is read to

prevent reading data in transition. because the

BIPORT TIMEKEEPER cells in the RAM arrays

are only data registers and not the actual clock

counters, updating the registers can be halted with-

out disturbing the clock itself.

Updating is halted when a '1' is

written to the READ bit D6 in the control

Register(7FF8h). As long as '1' remains in that

position, updating is halted. After a halt is issued,

the registers reflect the count; that is the day, date

and time that were current at moment the halt com-

mand was issued.

All of the TIMEKEEPER registers are

updated simultaneously. A halt will not interrupt an

update in progress. Updating occurs approximately

1 sec after the READ bit is reset to' 0 '.

Setting the Clock

Bit D7 of the control Register(7FF8h)

is the WRITE bit. Setting the WRITE bit to a ' 1' like

the READ bit, halts updates to the TIMEKEEPER

registers. The users can then load them with the

correct day, date, and time data in 24 hours BCD

format. The century value can be written at loca-

tion 7FF1h.Memory location from 7FF2h to 7FF7h

is not available to user and should not be accessed.

Resetting the WRITE bit a' 0 ' then transfers the

values of all time register (7FFFh - 7FF9h,7FF1h)

to actual TIMEKEEPER counters and allows nor-

mal operation to resume. After the WRITE bit is

reset, the next clock update will occur approxi-

mately one second later.

NOTE: Upon power up following a power failure

both the WRITE bit and the READ bit will be reset

to ' 0'

Stopping and starting the oscillator

The oscillator may be stopped at any

time. If the device is going to spend a significant

amount of time on the self, the oscillator can be

turned off to minimize current drain on the battery.

The STOP bit is located aat BIT D7 within the sec-

onds register .Setting it to a' 1' stkops the oscillator.

When reset to a' 0' the IM1644 oscillaator starts

within one second.

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

Calibrating the Clock

The IM1644 is driven by a quartz con-

trolled scillator with a nominal frequency of

32,768Hz. The devices are factory calibrated at

25°C and tested for accuracy. Clock accuracy will

not exceed ±35 ppm (parts per million) oscillator

fre-quency error at 25°C, which equates to about

±1.53 minutes per month. When the Calibration

circuit is properly employed, accuracy improves to

better than ±2 ppm at 25°C. The oscillation rate of

crystals changes with temperature. The IM1644

design employs periodic counter correction. The

calibration circuit adds or subtracts counts from the

oscillator divider circuit at the divide by 256 stage.

The number of times pulses which

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon the

value loaded into the five Calibration bits found in

the Control Register. Adding counts speeds the

clock up, sub-tracting counts slows the clock down.

The Calibration bits occupy the five lower order bits

(D4-D0) in the Control Register 7FF8h. These bits

can be set to represent any value between 0 and

31 in binary form. Bit D5 is a Sign bit; ’1’ indicates

positive calibration, ’0’ indicates negative calibra-

tion. Calibration occurs within a 64 minute cycle.

The first 62 minutes in the cycle may, once per

minute, have one second either shortened by 128

or lengthened by 256 oscillator cycles.

If a binary ’1’ is loaded into the reg-

ister , only the first 2 minutes in the 64 minute cycle

will be modified; if a binary 6 is loaded, the first 12

will be affected, and so on. Therefore, each cali-

bration step has the effect of adding 512 or sub-

tracting 256 oscillator cycles for every 125,829,120

actual oscillator cycles, that is +4.068 or –2.034

ppm of adjustment per calibration step in the cali-

bration register . Assuming that the oscillator is run-

ning at exactly 32,768Hz, each of the 31 increments

in the Calibration byte would represent +10.7 or –

5.35 seconds per month which corresponds to a

total range of +5.5 or –2.75 minutes per month.

This allows the designer to give the end user

the ability to calibrate the clock as the environment

requires,even if the final product is packaged in a

non-user serviceable enclosure. The designer

could providea simple utility that accesses the Cali-

bration byte.

Two methods are available for ascertain-

ing how much calibration a given IM1644 may re-

quire. The first involves setting the clock, letting it

run for a month and comparing it to a known accu-

rate reference and recording deviation over a fixed

period of time. Calibration values, including the

number of seconds lost or gained in a given pe-

riod, can be found.

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

FFSDSDFFSDFDSFDFDSFSDPPPA

Recomended DC Operating Condtions

Parameter Symbol Min Typ Max Units

Supply Voltage Vcc 4.5 5 5.5 V

Logic 1 Voltage All inputs VIH 2.2 - Vcc + 0.3 V

Logic 1 Voltage All inputs VIL -0.3 - 0.8 V

DC Electrical Characetristics

Parameter Symbol Min Typ Max Units Notes

Average Vcc Power Icc1 30 55 mA

Supply Current

TTL Standby Current (CE = VIH, I

cc2 36mA

CE2 = VIL

CMOS Standby Current Icc3 24mA

CE = Vcc - 0.2V, CE2=GND = 0.2V)

Input Leakage Current IIL -1 1

Output Leakage Current IOL -1 1

Output Logic 1 Voltage

(IOUT = -1.0 mA) VOH 2.4 V

Output Logic 1 Voltage VOL 0.4 V

(IOUT =+2.1 mA)

Write Protection Voltage VTP 4.1 4.35 4.5 V

Capacitance

Parameter Symbol Min Typ Max Units

Capacitance on all pins

except DQ C17pF

Capacitance on DQ CDQ 10 pF

Absolute Maximum Ratings

Voltage on any pin relative to GND...........-0.3V to 7.0V

Operating Temperature...........................0oC to 70oC

Storage Temperature..............................-20oC to 70oC

Soldering Temperature...........................260oC for 10 seconds

µA

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

AC Electrical Characteristics

IM1644-12

Parameter Symbol Min Max Units

Read Cycle Time tRC 120 ns

Address Access Time tAA 120 ns

CE Access Time tCEA 120 ns

CE Data Off Time tCEZ 40 ns

Output Enable Access Time tOEA 100 ns

Output Enable Data Off Time tOEZ 35 ns

Output Enable to DQ Low-Z tOEL 5ns

CE to DQ Low-Z tCEL 5ns

Output Hold From Address tOH 5ns

Write Cycle Time tWC 120 ns

Address Setup Time tAS 0ns

CE and CE2 Pulse Width tCEW 100 ns

Address Hold from End of Write tAH 15 ns

Write Pulse Width tWEW 120 ns

WE Data Off Time tWEZ 40 ns

WE or CE Inactive Time tWR 10 ns

Data Setup Time tDS 85 ns

Data Hold Time High tDH 15 ns

AC Electrical Characteristics (Power- Up/ Down Timing)

Parameter Symbol Min. Typ Max. Units

CE or WE at VIH tPD 0µsec

before Power Down tF300 µsec

VPF (Max) to V PF (Min) Vcc Fall Time tFB 10 µsec

VPF (Min) to Vso Vcc Fall Time tRB 1µ sec

Vso (Min) to VPF (Max) Vcc Rise Time tR0µsec

Power Up tREC 40 200 ms

Expected Data Retention Time tDR 10 years

(Oscillator on)

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

A0-A12

OE

CE,CE2

WE

I/O0-I/O7

out

tRC tRC tRC

tAH

tAS

tAA

tCEA

tCEL

tOEA

tWR

tWEW

tOEZ

tOH

tOEL

READ CYCLE TIME

out IN

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

OE

I/OValid Out Valid In Valid In Valid Out

I/O7

WE

A0 - A12

CE,CE2

VCCVPF(max)

VPF(min) VPF

tR

VSO

tRB

tPD tREC

CE

IBATT Data Retention

tPB

tWC tWC tRC

tAS tWR

tCEW tAH

tAA

tOEA

tWR

tWEW

tDS

tDH tWEZ

tCEZ

WRITE CYCLE TIME

POWER DOWN/POWER UP TIMING

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

TRUTH TABLE

Vcc CE OE WE MODE DQ POWER

VIH X X Deselect High Z Standby

X X X Deselect High Z Standby

5 Volts + 10% VIL X VIL Write Data IN Active

VIL VIL VIH Read Dat Out Active

VIL VIH Read High Z Active

<4.5 Volts > Bat X X X X Deselect High Z CMOS Standby

< VBAT X X X X Deselect High Z Data Retention

Mode

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM

7FFFh

7FFEh

7FFDh

7FFCh

7FFBh

7FFAh

7FF9h

7FF8h

7FF7h

7FF6h

7FF5h

7FF4h

7FF3h

7FF2 h

7FF1h

7FF0h

Years

0

FT

0

10

R

0

years

X

0

10

0

10

Minutes

Seconds

S

0

10 M

Date

0

Hours

0

BL.

10

0

ST

W

0

1000

X

Date

0

Hours

0

100

0

Day of

Day

(24 Hour

Minutes

Seconds

Calibra

0

-

years

0

D7

Month

Format)

tion

0

Year

Month

Date

Day

Hour

Minutes

Secs

Control

-

century

Flags

D6 D5 D4 D3 D 2 D1 D0

Data

Address Function

BCD For

00 -99

01-12

01-31

01-07

00-23

00-59

01-12

01-31

00-23

00-59

00-99

Range

mat

0

FT - Fequency test bit

ST - Stop bit

W - Write bit

R - Read bit

BL - Battery low

S - Sign bit

REGISTER MAP

J

H

A

C

F

G

D

DIM IN INCHES MIN. MAX.

A 1.470 1.490

B 0.675 0.700

C 0.315 0.335

D 0.075 0.105

F 0.140 0.180

G 0.090 0.110

H 0.590 0.630

J 0.008 0.012

INNOVATIVE

IM 1644Y-12

Timekeeping + SRAM

mm - yy

B

K

K 0.015 0.021

INNOVATIVE IM1644

Nonvolatile Timekeeping RAM