1
FEATURES
D
3
2
5
81
OE VCC
A
GND
DCT PACKAGE
(TOP VIEW) YZP PACKAGE
(BOTTOM VIEW)
DCU PACKAGE
(TOP VIEW)
3
2
4 5
1
OE VCC
YA
GND
A
GND
VCC
C
B
See mechanical drawings for dimensions.
2
5
3
4
8
B D
C
BY
C
46
7
6
7
86
1
7
OE
D
Y
DESCRIPTION/ORDERING INFORMATION
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(µA) Dynamic-Power Consumption
(pF)
†Single, dual, and triple gates
3.3-V
Logic† 3.3-V
Logic†
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45
Time − ns
Voltage − V
†AUP1G08 data at CL = 15 pF
Switching Characteristics
at 25 MHz†
OutputInput
SN74AUP1G99LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007www.ti.com
2
•Available in the Texas Instruments •Wide Operating V
CC
Range of 0.8 V to 3.6 VNanoFree™ Package
•Optimized for 3.3-V Operation•Low Static-Power Consumption
•3.6-V I/O Tolerant to Support Mixed-Mode(I
CC
= 0.9 µA Max)
Signal Operation•Low Dynamic-Power Consumption
•t
pd
= 7.4 ns Max at 3.3 V(C
pd
= 5 pF Typ at 3.3 V)
•Suitable for Point-to-Point Applications•Low Input Capacitance (C
I
= 1.5 pF)
•Latch-Up Performance Exceeds 100 mA Per•Low Noise – Overshoot and Undershoot
JESD 78, Class II<10% of V
CC
•ESD Performance Tested Per JESD 22•Input-Disable Feature Allows Floating Input
– 2000-V Human-Body ModelConditions
(A114-B, Class II)•I
off
Supports Partial-Power-Down Mode
– 200-V Machine Model (A115-A)Operation
– 1000-V Charged-Device Model (C101)•Includes Schmitt-Trigger Inputs
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portableapplications. This family ensures a very low static- and dynamic-power consumption across the entire V
CC
rangeof 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (seeFigures 1 and 2).
xxxxxx
Figure 1. AUP - The Lowest-Power Family
Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has theinput-disable feature, which allows floating input signals. The inputs and output are disabled when theoutput-enable ( OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input.The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, andbuffer. All inputs can be connected to V
CC
or GND.
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transitionand better switching noise immunity at the input.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
NanoFree™ – WCSP (DSBGA)0.23-mm Large Bump – YZP Tape and reel SN74AUP1G99YZPR _ _ HY_(Pb-free)– 40 °C to 85 °C
SSOP – DCT Tape and reel SN74AUP1G99DCTR H99_ _ _VSSOP – DCU Tape and reel SN74AUP1G99DCUR H99_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.DCU: The actual top-side marking has one additional character that designates the assembly/test site.YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one followingcharacter to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
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A2
B3
C
7
D6
Y
5
OE 1
SN74AUP1G99LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
FUNCTION TABLE
INPUTS
OUTPUT
YOE D C B A
L L L L L LL L L L H HL L L H L LL L L H H HL L H L L LL L H L H LL L H H L HL L H H H HL H L L L HL H L L H LL H L H L HL H L H H LL H H L L HL H H L H HL H H H L LL H H H H LH X
(1)
X
(1)
X
(1)
X
(1)
Z
(1) Floating inputs allowed.
LOGIC DIAGRAM (POSITIVE LOGIC)
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3-STATE BUFFER FUNCTIONS AVAILABLE
INPUT Y
3-STATE INVERTER FUNCTIONS AVAILABLE
INPUT Y
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
FUNCTION SELECTION TABLE
PRIMARY FUNCTION COMPLEMENTARY FUNCTION PAGE
3-state buffer 43-state inverter 43-state 2-to-1 data selector MUX 53-state 2-to-1 data selector MUX, inverted out 53-state 2-input AND 3-state 2-input NOR, both inputs inverted 53-state 2-input AND, 1 input inverted 3-state 2-input NOR, 1 input inverted 53-state 2-input AND, both inputs inverted 3-state 2-input NOR 53-state 2-input NAND 3-state 2-input OR, both inputs inverted 63-state 2-input NAND, 1 input inverted 3-state 2-input OR, 1 input inverted 63-state 2-input NAND, both inputs inverted 3-state 2-input OR 63-state 2-input XOR 63-state 2-input XNOR 3-state 2-input XOR, 1 input inverted 7
FUNCTION OE A B C D
Input X L LX Input H LL H Input L3-state buffer L H L Input HH X L InputX L H InputL L X Input
FUNCTION OE A B C D
Input X L HX Input H HL H Input H3-state inverter L H L Input LH X L InputX H H InputH H X Input
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3-STATE MUX FUNCTIONS AVAILABLE
Input 1
Input 2
A/B
YInput 1
Input 2
A/B
Y
3-STATE AND/NOR FUNCTIONS AVAILABLE
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
SN74AUP1G99LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
FUNCTION OE A B C D
3-state 2-to-1, data selector MUX Input 1 Input 2 Input 1 or Input 2 L3-state 2-to-1, data selector MUX Input 2 Input 1 Input 2 or Input 1 LL3-state 2-to-1, data selector MUX, inverted out Input 1 Input 2 Input 1 or Input 2 H3-state 2-to-1, data selector MUX, inverted out Input 2 Input 1 Input 2 or Input 1 H
NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION OE A B C D
2 3-state AND 3-state NOR, both inputs inverted L Input 1 Input 2 LL2 3-state AND 3-state NOR, both inputs inverted L Input 2 Input 1 L
NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION OE A B C D
2 3-state AND, with A inverted 3-state NOR, with B inverted Input 2 L Input 1 LL2 3-state AND, with A inverted 3-state NOR, with B inverted H Input 1 Input 2 H
NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION OE A B C D
2 3-state AND, with B inverted 3-state NOR, with A inverted Input 1 L Input 2 LL2 3-state AND, with B inverted 3-state NOR, with A inverted H Input 2 Input 1 H
NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION OE A B C D
2 3-state AND, both inverted inputs 3-state NOR Input 1 H Input 2 HL2 3-state AND, both inverted inputs 3-state NOR Input 2 H Input 1 H
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3-STATE NAND/OR FUNCTIONS AVAILABLE
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
3-STATE XOR/XNOR FUNCTIONS AVAILABLE
Input 1 Y
Input 2
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION OE A B C D
2 3-state NAND 3-state OR, with both inputs inverted L Input 1 Input 2 HL2 3-state NAND 3-state OR, with both inputs inverted L Input 2 Input 1 H
NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION OE A B C D
2 3-state NAND, with A inverted 3-state OR, with B inverted Input 2 L Input 1 HL2 3-state NAND, with A inverted 3-state OR, with B inverted H Input 1 Input 2 L
NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION OE A B C D
2 3-state NAND, with B inverted 3-state OR, with A inverted Input 1 L Input 2 HL2 3-state NAND, with B inverted 3-state OR, with A inverted H Input 2 Input 1 L
NO. OF INPUTS AND/NAND FUNCTION OR/NOR FUNCTION OE A B C D
2 3-state NAND, with both inputs inverted 3-state OR Input 1 H Input 2 LL2 3-state NAND, with both inputs inverted 3-state OR Input 2 H Input 1 L
FUNCTION OE A B C D
Input 1 X L Input 2Input 2 X L Input 1X Input 1 H Input 23-state XOR L
X Input 2 H Input 1L H Input 1 Input 2L H Input 2 Input 1
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3-STATE XOR/XNOR FUNCTIONS AVAILABLE (continued)
Input 1 Y
Input 2
Input 1 Y
Input 2
Input 1 Y
Input 2
Absolute Maximum Ratings
(1)
SN74AUP1G99LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
FUNCTION OE A B C D
3-state XOR, with A inverted L H L Input 1 Input 2
FUNCTION OE A B C D
3-state XOR, with B inverted L H L Input 1 Input 2
FUNCTION OE A B C D
3-state XNOR H L Input 1 Input 2L3-state XNOR H L Input 2 Input 1
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range – 0.5 4.6 VV
I
Input voltage range
(2)
– 0.5 4.6 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
– 0.5 4.6 VV
O
Output voltage range in the high or low state
(2)
– 0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 – 50 mAI
OK
Output clamp current V
O
< 0 – 50 mAI
O
Continuous output current ± 20 mAContinuous current through V
CC
or GND ± 50 mADCT package 220θ
JA
Package thermal impedance
(3)
DCU package 227 °C/WYZP package 102T
stg
Storage temperature range – 65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
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Recommended Operating Conditions
(1)
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
MIN MAX UNIT
V
CC
Supply voltage 0.8 3.6 VV
I
Input voltage 0 3.6 VActive state 0 V
CCV
O
Output voltage V3-state 0 3.6V
CC
= 0.8 V – 20 µAV
CC
= 1.1 V – 1.1V
CC
= 1.4 V – 1.7I
OH
High-level output current
V
CC
= 1.65 V – 1.9 mAV
CC
= 2.3 V – 3.1V
CC
= 3 V – 4V
CC
= 0.8 V 20 µAV
CC
= 1.1 V 1.1V
CC
= 1.4 V 1.7I
OL
Low-level output current
V
CC
= 1.65 V 1.9 mAV
CC
= 2.3 V 3.1V
CC
= 3 V 4
Δt/ Δv Input transition rise or fall rate V
CC
= 0.8 V to 3.6 V 200 ns/VT
A
Operating free-air temperature – 40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics
SN74AUP1G99LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
T
A
= – 40 °CT
A
= 25 °C
to 85 °CPARAMETER TEST CONDITIONS V
CC
UNITMIN TYP MAX MIN MAX
0.8 V 0.3 0.6 0.3 0.61.1 V 0.53 0.9 0.53 0.9V
T+
1.4 V 0.74 1.11 0.74 1.11Positive-going
Vinput threshold
1.65 V 0.91 1.29 0.91 1.29voltage
2.3 V 1.37 1.77 1.37 1.773 V 1.88 2.29 1.88 2.290.8 V 0.1 0.6 0.1 0.61.1 V 0.26 0.65 0.26 0.65V
T –
1.4 V 0.39 0.75 0.39 0.75Negative-going
Vinput threshold
1.65 V 0.47 0.84 0.47 0.84voltage
2.3 V 0.69 1.04 0.69 1.043 V 0.88 1.24 0.88 1.240.8 V 0.07 0.5 0.07 0.51.1 V 0.08 0.46 0.08 0.46
ΔV
T
1.4 V 0.18 0.56 0.18 0.56Hysteresis V1.65 V 0.27 0.66 0.27 0.66(V
T+
– V
T –
)
2.3 V 0.53 0.92 0.53 0.923 V 0.79 1.31 0.79 1.31I
OH
= – 20 µA 0.8 V to 3.6 V V
CC
– 0.1 V
CC
– 0.1I
OH
= – 1.1 mA 1.1 V 0.75 ×V
CC
0.7 ×V
CC
I
OH
= – 1.7 mA 1.4 V 1.11 1.03I
OH
= – 1.9 mA 1.65 V 1.32 1.3V
OH
VI
OH
= – 2.3 mA 2.05 1.972.3 VI
OH
= – 3.1 mA 1.9 1.85I
OH
= – 2.7 mA 2.72 2.673 VI
OH
= – 4 mA 2.6 2.55I
OL
= 20 µA 0.8 V to 3.6 V 0.1 0.1I
OL
= 1.1 mA 1.1 V 0.3 ×V
CC
0.3 ×V
CC
I
OL
= 1.7 mA 1.4 V 0.31 0.37I
OL
= 1.9 mA 1.65 V 0.31 0.35V
OL
VI
OL
= 2.3 mA 0.31 0.332.3 VI
OL
= 3.1 mA 0.44 0.45I
OL
= 2.7 mA 0.31 0.333 VI
OL
= 4 mA 0.44 0.45AllI
I
V
I
= GND to 3.6 V 0 V to 3.6 V 0.1 0.5 µAinputsI
off
V
I
or V
O
= 0 V to 3.6 V 0 V 0.2 0.6 µA
ΔI
off
V
I
or V
O
= 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 µAI
OZ
V
O
= V
CC
or GND 3.6 V 0.1 0.5 µAV
I
= GND or (V
CC
to 3.6 V),I
CC
0.8 V to 3.6 V 0.5 0.9 µAOE = GND, I
O
= 0
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Switching Characteristics
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
Electrical Characteristics (continued)over recommended operating free-air temperature range (unless otherwise noted)
T
A
= – 40 °CT
A
= 25 °C
to 85 °CPARAMETER TEST CONDITIONS V
CC
UNITMIN TYP MAX MIN MAX
Data
40 50inputs
V
I
= V
CC
– 0.6 V,
(1)
I
O
= 0 3.3 V µA
ΔI
CC
OE 110 120All
V
I
= GND to 3.6 V, OE = V
CC
(2)
0.8 V to 3.6 V 0 nAinputs
0 V 1.5C
I
V
I
= V
CC
or GND pF3.6 V 1.5C
o
V
O
= V
CC
or GND 3.6 V 3 pF
(1) One input at V
CC
– 0.6 V, other input at V
CC
or GND(2) To show I
CC
is very low when the input-disable feature is enabled.
over recommended operating free-air temperature range, C
L
= 5 pF (unless otherwise noted) (see Figure 3 and Figure 4 )
T
A
= – 40 °CT
A
= 25 °CFROM TO
to 85 °CPARAMETER V
CC
UNIT(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
0.8 V 321.2 V ± 0.1 V 0.5 9.9 20.1 0.5 26.61.5 V ± 0.1 V 1.4 6.6 11.9 0.5 16.8t
pd
A, B, C, or D Y ns1.8 V ± 0.15 V 1.8 5.3 8.9 1 132.5 V ± 0.2 V 2.1 3.9 5.8 1.3 8.93.3 V ± 0.3 V 1.9 3.3 4.8 1.2 7.40.8 V 351.2 V ± 0.1 V 0.6 11.1 21.7 0.5 25.21.5 V ± 0.1 V 2.3 7.4 12.6 1.4 16.4t
en
OE Y ns1.8 V ± 0.15 V 2 5.7 9.4 1.1 12.82.5 V ± 0.2 V 2.1 4.1 6.2 1.2 8.53.3 V ± 0.3 V 1.9 3.4 5 1.1 6.70.8 V 9.81.2 V ± 0.1 V 1.4 4.5 7.7 1.5 8.21.5 V ± 0.1 V 1.7 3.2 4.8 1.7 6t
dis
OE Y ns1.8 V ± 0.15 V 1.5 3 4.7 1.3 6.12.5 V ± 0.2 V 0.9 1.9 3 0.7 4.23.3 V ± 0.3 V 0.8 2.5 4.4 0.7 4.5
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Switching Characteristics
SN74AUP1G99LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
over recommended operating free-air temperature range, C
L
= 10 pF (unless otherwise noted) (see Figure 3 and Figure 4 )
T
A
= – 40 °CT
A
= 25 °CFROM TO
to 85 °CPARAMETER V
CC
UNIT(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
0.8 V 361.2 V ± 0.1 V 0.4 10.7 21.1 0.7 29.81.5 V ± 0.1 V 2 7.2 12.6 1.1 18.5t
pd
A, B, C, or D Y ns1.8 V ± 0.15 V 2.3 5.8 9.5 1.5 14.52.5 V ± 0.2 V 2.5 4.4 6.3 1.7 10.53.3 V ± 0.3 V 2.3 3.7 5.2 1.5 8.40.8 V 01.2 V ± 0.1 V 1.4 12.1 22.8 0.8 29.31.5 V ± 0.1 V 2.8 8 13.3 2 18.7t
en
OE Y ns1.8 V ± 0.15 V 2.5 6.2 10 1.6 14.82.5 V ± 0.2 V 2.5 4.5 6.7 1.6 9.93.3 V ± 0.3 V 2.3 3.8 5.4 1.5 8.20.8 V 01.2 V ± 0.1 V 2 5.6 9.3 2 101.5 V ± 0.1 V 2.5 4.1 5.8 2.4 7.6t
dis
OE Y ns1.8 V ± 0.15 V 2.9 4.2 5.7 2.7 7.92.5 V ± 0.2 V 1.1 2.7 4.4 1.1 5.53.3 V ± 0.3 V 1.9 3.5 5.2 1.9 5.8
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Switching Characteristics
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
over recommended operating free-air temperature range, C
L
= 15 pF (unless otherwise noted) (see Figure 3 and Figure 4 )
T
A
= – 40 °CT
A
= 25 °CFROM TO
to 85 °CPARAMETER V
CC
UNIT(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
0.8 V 381.2 V ± 0.1 V 0.9 11.4 22 0.5 30.81.5 V ± 0.1 V 2.5 7.8 13.2 1.6 19.2t
pd
A, B, C, or D Y ns1.8 V ± 0.15 V 2.7 6.3 10 1.9 15.12.5 V ± 0.2 V 2.8 4.7 6.6 2 10.83.3 V ± 0.3 V 2.6 4 5.5 1.8 8.80.8 V 441.2 V ± 0.1 V 1.8 13 24.2 1.3 30.61.5 V ± 0.1 V 3.2 8.6 14.1 2.4 19.5t
en
OE Y ns1.8 V ± 0.15 V 2.9 6.7 10.6 2 15.42.5 V ± 0.2 V 2.8 4.9 7 1.9 10.33.3 V ± 0.3 V 2.6 4.1 5.7 1.8 8.60.8 V 131.2 V ± 0.1 V 2.7 6.3 9.9 2.8 10.71.5 ± 0.1 V 3.2 4.6 6.1 3.1 8t
dis
OE Y ns1.8 V ± 0.15 V 3.2 4.8 6.6 3 8.82.5 V ± 0.2 V 2.2 3.4 4.7 2 63.3 V ± 0.3 V 2.4 4.4 6.5 2.3 7.2
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Switching Characteristics
Operating Characteristics
SN74AUP1G99LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
over recommended operating free-air temperature range, C
L
= 30 pF (unless otherwise noted) (see Figure 3 and Figure 4 )
T
A
= – 40 °CT
A
- 25 °CFROM TO
to 85 °CPARAMETER V
CC
UNIT(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
0.8 V 481.2 V ± 0.1 V 3.1 14 24.9 2.6 36.11.5 V ± 0.1 V 4.2 9.6 15.1 3.3 23.1t
pd
A, B, C, or D Y ns1.8 V ± 0.15 V 4.1 7.9 11.7 3.3 182.5 V ± 0.2 V 4.1 5.9 7.9 3.1 12.73.3 V ± 0.3 V 3.7 5.1 6.7 2.8 10.40.8 V 501.2 V ± 0.1 V 4.4 16 27.6 3.9 36.81.5 V ± 0.1 V 5.3 10.7 16.2 4.3 23.6t
en
OE Y ns1.8 V ± 0.15 V 4.6 8.5 12.4 3.6 18.62.5 V ± 0.2 V 4.2 6.3 8.5 3.2 12.63.3 V ± 0.3 V 3.8 5.4 7.1 2.9 10.20.8 V 191.2 V ± 0.1 V 6 10.1 14.2 6 14.61.5 V ± 0.1 V 5.1 7.4 10.6 5 10.1t
dis
OE Y ns1.8 V ± 0.15 V 5.5 8.6 11.6 5.5 12.12.5 V ± 0.2 V 3.3 5.9 8.3 3.3 8.93.3 V ± 0.3 V 6 8.7 10.9 5.9 11.8
T
A
= 25 °C
PARAMETER TEST CONDITIONS V
CC
TYP UNIT
0.8 V 41.2 ± 0.1 V 41.5 ± 0.1 V 4Outputs enabled
1.8 V ± 0.15 V 42.5 V ± 0.2 V 53.3 V ± 0.3 V 5C
pd
Power dissipation capacitance f = 10 MHz pF0.8 V 01.2 ± 0.1 V 01.5 ± 0.1 V 0Outputs disabled
1.8 V ± 0.15 V 02.5 V ± 0.2 V 03.3 V ± 0.3 V 0
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN74AUP1G99
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VM
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
1 MΩ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Output
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, for propagation delays
tr/tf = 3 ns, for setup and hold times and pulse width tr/tf = 1.2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.
E. All parameters and waveforms are not applicable to all devices.
VMVM
VMVM
VM
5, 10, 15, 30 pF
VCC/2
VCC
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V VCC = 1.5 V
± 0.1 V VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
CL
VM
VI
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
th
tsu
Data Input
Timing Input VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2 VCC/2
VCC/2
VCC/2
VCC
VCC/2
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
(Propagation Delays, Setup and Hold Times, and Pulse Width)
Figure 3. Load Circuit and Voltage Waveforms
14 Submit Documentation Feedback Copyright © 2004 – 2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G99
www.ti.com
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V VCC = 1.5 V
± 0.1 V VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
CL
VM
VI
V∆
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V∆
VOH - V∆
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Control VCC/2 VCC/2
VCC/2
VCC/2
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
TEST S1
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
GND
5 kΩ
5 kΩ
2 × VCC
SN74AUP1G99LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATEWITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
(Enable and Disable Times)
Figure 4. Load Circuit and Voltage Waveforms
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN74AUP1G99
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74AUP1G99DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCTRE4 ACTIVE SM8 DCT 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCTRG4 ACTIVE SM8 DCT 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCTT ACTIVE SM8 DCT 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCTTE4 ACTIVE SM8 DCT 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCTTG4 ACTIVE SM8 DCT 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCUR ACTIVE US8 DCU 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCUT ACTIVE US8 DCU 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCUTE4 ACTIVE US8 DCU 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99DCUTG4 ACTIVE US8 DCU 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G99YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2008
Addendum-Page 1
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AUP1G99DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74AUP1G99YZPR DSBGA YZP 8 3000 180.0 8.4 1.02 2.02 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-May-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUP1G99DCUR US8 DCU 8 3000 202.0 201.0 28.0
SN74AUP1G99YZPR DSBGA YZP 8 3000 220.0 220.0 34.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-May-2011
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
0,60
0,20
0,25
0°– 8°
0,15 NOM
Gage Plane
4188781/C 09/02
4,25
5
0,30
0,15
2,90 3,75
2,70
8
4
3,15
2,75
1
0,10
0,00
1,30 MAX
Seating Plane
0,10
M
0,13
0,65
PIN 1
INDEX AREA
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
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