TMS320LF2406APZAR - Texas Instruments

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

DHigh-Performance Static CMOS Technology

− 25-ns Instruction Cycle Time (40 MHz)

− 40-MIPS Performance

− Low-Power 3.3-V Design

DBased on TMS320C2xx DSP CPU Core

− Code-Compatible With F243/F241/C242

− Instruction Set and Module Compatible

With F240

DFlash (LF) and ROM (LC) Device Options

− LF240xA: LF2407A, LF2406A,

LF2403A, LF2402A

− LC240xA: LC2406A, LC2404A,

LC2403A, LC2402A

DOn-Chip Memory

− Up to 32K Words x 16 Bits of Flash

EEPROM (4 Sectors) or ROM

− Programmable “Code-Security” Feature

for the On-Chip Flash/ROM

− Up to 2.5K Words x 16 Bits of

Data/Program RAM

− 544 Words of Dual-Access RAM

− Up to 2K Words of Single-Access RAM

DBoot ROM (LF240xA Devices)

− SCI/SPI Bootloader

DUp to Two Event-Manager (EV) Modules

(EVA and EVB), Each Includes:

− Two 16-Bit General-Purpose Timers

− Eight 16-Bit Pulse-Width Modulation

(PWM) Channels Which Enable:

− Three-Phase Inverter Control

− Center- or Edge-Alignment of PWM

Channels

− Emergency PWM Channel Shutdown

With External PDPINTx Pin

− Programmable Deadband (Deadtime)

Prevents Shoot-Through Faults

− Three Capture Units for Time-Stamping

of External Events

− Input Qualifier for Select Pins

− On-Chip Position Encoder Interface

Circuitry

− Synchronized A-to-D Conversion

− Designed for AC Induction, BLDC,

Switched Reluctance, and Stepper Motor

Control

− Applicable for Multiple Motor and/or

Converter Control

DExternal Memory Interface (LF2407A)

− 192K Words x 16 Bits of Total Memory:

64K Program, 64K Data, 64K I/O

DWatchdog (WD) Timer Module

D10-Bit Analog-to-Digital Converter (ADC)

− 8 or 16 Multiplexed Input Channels

− 500-ns MIN Conversion Time

− Selectable Twin 8-State Sequencers

Triggered by Two Event Managers

DController Area Network (CAN) 2.0B Module

(LF2407A, 2406A, 2403A)

DSerial Communications Interface (SCI)

D16-Bit Serial Peripheral Interface (SPI)

(LF2407A, 2406A, LC2404A, 2403A)

DPhase-Locked-Loop (PLL)-Based Clock

Generation

DUp to 40 Individually Programmable,

Multiplexed General-Purpose Input/Output

(GPIO) Pins

DUp to Five External Interrupts (Power Drive

Protection, Reset, Two Maskable Interrupts)

DPower Management:

− Three Power-Down Modes

− Ability to Power Down Each Peripheral

Independently

DReal-Time JTAG-Compliant Scan-Based

Emulation, IEEE Standard 1149.1† (JTAG)

DDevelopment Tools Include:

− Texas Instruments (TI) ANSI C Compiler,

Assembler/Linker, and Code Composer

Studio Debugger

− Evaluation Modules

− Scan-Based Self-Emulation (XDS510)

− Broad Third-Party Digital Motor Control

Support

DPackage Options

− 144-Pin LQFP PGE (LF2407A)

− 100-Pin LQFP PZ (2406A, LC2404A)

− 64-Pin TQFP PAG (LF2403A, LC2403A,

LC2402A)

− 64-Pin QFP PG (2402A)

DExtended Temperature Options (A and S)

− A: − 40°C to 85°C

− S: − 40°C to 125°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Code Composer Studio and XDS510 are trademarks of Texas Instruments.

Other trademarks are the property of their respective owners.

†IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Description 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320x240xA Device Summary 5. . . . . . . . . . . . . . . . .

Functional Block Diagram of the 2407A

DSP Controller 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pinouts 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Functions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Maps 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Memory Map of the 2407A/2406A 29. . . . . . .

Device Reset and Interrupts 30. . . . . . . . . . . . . . . . . . . . .

DSP CPU Core 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320x240xA Instruction Set 34. . . . . . . . . . . . . . . . . . .

Scan-Based Emulation 34. . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Block Diagram of the 2407A DSP CPU 35. .

Internal Memory 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripherals 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Event Manager Modules (EVA, EVB) 45. . . . . . . . . . . .

Enhanced Analog-to-Digital Converter

(ADC) Module 49. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Communications Interface (SCI) Module 53. . . .

Controller Area Network (CAN) Module 51. . . . . . . . . .

Serial Peripheral Interface (SPI) Module 55. . . . . . . . . .

PLL-Based Clock Module 57. . . . . . . . . . . . . . . . . . . . . .

Digital I/O and Shared Pin Functions 60. . . . . . . . . . . . .

External Memory Interface (LF2407A) 64. . . . . . . . . . . .

Watchdog (WD) Timer Module 65. . . . . . . . . . . . . . . . . .

Development Support 67. . . . . . . . . . . . . . . . . . . . . . . . . . .

Documentation Support 70. . . . . . . . . . . . . . . . . . . . . . . . .

LF240xA and LC240xA Electrical

Specifications Data 71. . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 71. . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 71. . . . . . . . . . . . .

Migrating From LF240xA (Flash) Devices to

LC240xA (ROM) Devices 110. . . . . . . . . . . . . . . . . . .

Migrating From 240x Devices to 240xA Devices 111. . .

Migrating From LF240x Devices to

LC240xA Devices 112. . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Register Description 113. . . . . . . . . . . . . . . . . .

Mechanical Data 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table of Contents

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

REVISION HISTORY

PAGE HIGHLIGHTS

11 Added the VCCA pin to final note on Table 2

27 Modified LC2403A memory map (Figure 7) in location 8200

50 Added a sentence to the paragraph following Figure 12

59 Added 1/4 W to second column header in Table 10, Loop Filter Component Values With Damping Factor = 2.0

71 Added a note to recommended operating conditions table

72 Added a note to electrical characteristics table

77 Added Figure 23

101 Changed parameter td(WRN) in switching characteristics over recommended operating conditions for an external

memory interface write at 40 MHz [H = 0.5tc(CO)] table

108 Changed MAX value for ICCA in operating characteristics over recommended operating condition ranges table

110 Added note to Table 18

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

description

The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of

digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs. The

240xA devices offer the enhanced TMS320DSP architectural design of the C2xx core CPU for low-cost,

low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital

motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While

code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing

performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary

section for device-specific features.

The 240xA generation offers an array of memory sizes and different peripherals tailored to meet the specific

price/performance points required by various applications. Flash devices of up to 32K words offer a

cost-effective reprogrammable solution for volume production. The 240xA devices offer a password-based

“code security” feature which is useful in preventing unauthorized duplication of proprietary code stored in

on-chip Flash/ROM. Note that Flash-based devices contain a 256-word boot ROM to facilitate in-circuit

programming. The 240xA family also includes ROM devices that are fully pin-to-pin compatible with their Flash

counterparts.

All 240xA devices offer at least one event manager module which has been optimized for digital motor control

and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM

generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital

conversion. Devices with dual event managers enable multiple motor and/or converter control with a single

240xA DSP controller. Select EV pins have been provided with an “input-qualifier” circuitry, which minimizes

inadvertent pin-triggering by glitches.

The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 375 ns and

offers up to 16 channels of analog input. The autosequencing capability of the ADC allows a maximum of

16 conversions to take place in a single conversion session without any CPU overhead.

A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication

to other devices in the system. For systems requiring additional communication interfaces, the 2407A, 2406A,

2404A, and 2403A offer a 16-bit synchronous serial peripheral interface (SPI). The 2407A, 2406A, and 2403A

offer a controller area network (CAN) communications module that meets 2.0B specifications. To maximize

device flexibility, functional pins are also configurable as general-purpose inputs/outputs (GPIOs).

To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices.

This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite

of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger

supports this family. Numerous third-party developers not only offer device-level development tools, but also

system-level design and development support.

TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320x240xA device summary

Note that throughout this data sheet, 240xA is used as a generic name for the LF240xA/LC240xA generation

of devices.

Table 1. Hardware Features of 240xA Devices

FEATURE LF2407A LF2406A LF2403A LF2402A LC2406A LC2404A LC2403A LC2402A

C2xx DSP Core Yes Yes Yes Yes Yes Yes Yes Yes

Instruction Cycle 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns

MIPS (40 MHz) 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS

RAM (16 bit word)

Dual-Access

RAM (DARAM) 544 544 544 544 544 544 544 544

RAM (16-bit word) Single-Access

RAM (SARAM) 2K 2K 512 512 2K 1K 512 —

3.3-V On-chip Flash (16-bit word)

(4 sectors: 4K, 12K, 12K, 4K) 32K 32K 16K 8K — — — —

On-chip ROM (16-bit word) — — — — 32K 16K 16K 6K

Code Security for On-Chip Flash/ROM Yes Yes Yes Yes Yes Yes Yes Yes

Boot ROM Yes Yes Yes Yes — — — —

External Memory Interface Yes ———————

Event Managers A and B (EVA and EVB) EVA,

EVB

EVA,

EVB EVA EVA EVA,

EVB

EVA,

EVB EVA EVA

SGeneral-Purpose (GP) Timers 4 4 2 2 4 4 2 2

SCompare (CMP)/PWM 12/16 12/16 6/8 6/8 12/16 12/16 6/8 6/8

SCapture (CAP)/QEP 6/4 6/4 3/2 3/2 6/4 6/4 3/2 3/2

SInput qualifier circuitry on

PDPINTx, CAPx, QEPx,

XINT1/2, and ADCSOC pins

Yes Yes Yes Yes Yes Yes Yes Yes

SStatus of PDPINTx pin reflected

in COMCONx register Yes Yes Yes Yes Yes Yes Yes Yes

Watchdog Timer Yes Yes Yes Yes Yes Yes Yes Yes

10-Bit ADC Yes Yes Yes Yes Yes Yes Yes Yes

SChannels 16 16 8 8 16 16 8 8

SConversion Time (minimum) 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns

SPI Yes Yes Yes —Yes Yes Yes —

SCI Yes Yes Yes Yes Yes Yes Yes Yes

CAN Yes Yes Yes —Yes —Yes —

Digital I/O Pins

(Shared) 41 41 21 21 41 41 21 21

External Interrupts 5 5 3 3 5 5 3 3

Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V

Packaging 144-pin

PGE

100-pin

64-pin

PAG

64-pin

100-pin

64-pin

PAG

64-pin

PG, PAG

Product Status:

Product Preview (PP)

Advance Information (AI)

Production Data (PD)

PD PD PD PD PD PD PD PD

Denotes features that are different/new compared to 240x devices.

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

functional block diagram of the 2407A DSP controller

XTAL1/CLKIN

XTAL2

PLLVCCA

PLLF2

PLLF

VSSA

VREFHI

ADCIN08−ADCIN15

VCCA

ADCIN00−ADCIN07

SCIRXD/IOPA1

SPISIMO/IOPC2

XINT2/ADCSOC/IOPD0

SCITXD/IOPA0

VREFLO

Port A(0−7) IOPA[0:7]

SPICLK/IOPC4

SPISTE/IOPC5

SPISOMI/IOPC3

Port E(0−7) IOPE[0:7]

Port F(0−6) IOPF[0:6]

Port C(0−7) IOPC[0:7]

Port D(0) IOPD[0]

Port B(0−7) IOPB[0:7]

TDO

TDI

CANRX/IOPC7

TRST

CANTX/IOPC6

EMU1

PDPINTB

TCK

EMU0

TMS

CAP5/QEP4/IOPF0

CAP4/QEP3/IOPE7

PWM7/IOPE1

PWM8/IOPE2

CAP6/IOPF1

PWM10/IOPE4

PWM9/IOPE3

PWM11/IOPE5

PWM12/IOPE6

T4PWM/T4CMP/IOPF3

T3PWM/T3CMP/IOPF2

TDIRB/IOPF4

TCLKINB/IOPF5

DARAM (B0)

256 Words

DARAM (B1)

256 Words

DARAM (B2)

32 Words

C2xx

DSP

Core

PLL Clock

10-Bit ADC

(With Twin

Autosequencer)

ÈÈÈÈÈÈÈ

CLKOUT/IOPE0

XINT1/IOPA2

BIO/IOPC1

MP/MC

TMS2

A0−A15

D0−D15

TP1

TP2

BOOT_EN/XF

READY

STRB

R/W

PS, DS, IS

VIS_OE

ENA_144

CAP3/IOPA5

PWM1/IOPA6

CAP1/QEP1/IOPA3

CAP2/QEP2/IOPA4

PDPINTA

PWM5/IOPB2

PWM6/IOPB3

PWM3/IOPB0

PWM4/IOPB1

PWM2/IOPA7

T2PWM/T2CMP/IOPB5

T1PWM/T1CMP/IOPB4

TCLKINA/IOPB7

TDIRA/IOPB6

VDD (3.3 V)

VSS

VCCP(5V)

ÈÈÈÈÈÈÈ

SARAM (2K Words)

Flash/ROM

(32K Words:

4K/12K/12K/4K)

External Memory

Interface

Event Manager A

D3 × Capture Input

D6 × Compare/PWM

Output

D2 × GP

Timers/PWM

SCI

SPI

Digital I/O

(Shared With

Other Pins)

CAN

JTAG Port

Event Manager B

D3 × Capture Input

D6 × Compare/PWM

Output

D2 × GP

Timers/PWM

ÈÈÈ

Indicates optional modules.

The memory size and peripheral selection of these modules change for different 240xA devices.

See Table 1 for device-specific details.

W/R / IOPC0

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pinouts

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

108

107

106

105

104

103

102

101

100

111

110

109

TMS320LF2407A PGE

PDPINTA

PLLF

TDIRA/IOPB6

XINT2/ADCSOC/IOPD0

CLKOUT/IOPE0

PDPINTB

XTAL1/CLKIN

XTAL2

PLLVCCA

PLLF2

BOOT_EN/XF

CCP

TP1

TP2

IOPF6

EMU0

EMU1/OFF

TCK

TDI

TDO

TMS

TMS2

TRST

R/W

W/R/IOPC0

STRB

READY

MP/MC

ENA_144

VIS_OE

A10

A11

A12

A13

A14

A15

D10

D11

D12

D13

D14

D15

PLLVCCA

VDD

VDDO

DDO

VDDO

DDO

VSS

VSSO

SSO

VSSO

SSO

CAP1/QEP1/IOPA3

CAP2/QEP2/IOPA4

CAP3/IOPA5

PWM1/

PWM2/

PWM3/

PWM4/

PWM5/

PWM6/

T1PWM/T1CMP/IOPB4

T2PWM/T2CMP/IOPB5

TCLKINA/

CAP4/QEP3/IOPE7

CAP5/QEP4/IOPF0

CAP6/

PWM7/

PWM8/

PWM9/

PWM10/

PWM11/

PWM12/

T3PWM/T3CMP/IOPF2

T4PWM/T4CMP/IOPF3

TDIRB/IOPF4

TCLKINB/

ADCIN00

ADCIN01

ADCIN02

ADCIN03

ADCIN04

ADCIN05

ADCIN06

ADCIN07

ADCIN08

ADCIN09

ADCIN10

ADCIN11

ADCIN12

ADCIN13

ADCIN14

ADCIN15

REFHI

REFLO

CCA

SSA

CANRX/

CANTX/

SCITXD/IOPA0

SCIRXD/IOPA1

SPICLK/IOPC4

SPISIMO/IOPC2

SPISOMI/IOPC3

SPISTE/IOPC5

XINT1/IOPA2

†Bold, italicized pin names indicate pin function after reset.

‡BOOT_EN is available only on Flash devices.

IOPB7

IOPE6

IOPB3

IOPB2

IOPE5

IOPB1

IOPB0

IOPA7

IOPE4

IOPA6

IOPE3

IOPE2

IOPE1

IOPF1

IOPC7

IOPC6

IOPF5

IOPC1BIO/

PGE PACKAGE†

(TOP VIEW)

‡

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pinouts (continued)

SCIRXD/

TMS

TDO

VDDO

VSSO

TDI

PDPINTB

TCK

IOPF6

VDD

VSS

TCLKINB/IOPF5

XTAL2

XTAL1/CLKIN

BOOT_EN/XF§

BIO/IOPC1

VSSA

VCCA

VREFHI

VREFLO

ADCIN08

ADCIN00

ADCIN09

ADCIN01

ADCIN10

TCLKINA/IOPB7

PWM12/IOPE6

PWM6/IOPB3

VSSO

VDDO

PWM5/IOPB2

PWM11/IOPE5

PWM4/IOPB1

VSS

VDD

PWM3/IOPB0

PWM2/IOPA7

PWM10/IOPE4

PWM1/IOPA6

VCCP¶

PWM9/IOPE3

TP1

PWM8/IOPE2

TP2

PWM7/IOPE1

VSSO

VDDO

CAP6/IOPF1

CANRX/IOPC7‡

CANTX/IOPC6‡

26100

25242322212019181716151413121110987654321

51525354555657585960616263646566676869707172737475

ADCIN11

ADCIN02

ADCIN12

ADCIN03

ADCIN13

ADCIN04

ADCIN05

ADCIN14

ADCIN06

ADCIN07

ADCIN15

EMU1/

EMU0

CAP4/QEP3/

CAP1/QEP1/

CAP5/QEP4/

CAP2/QEP2/

CAP3/

/IOPE0

DDO

TRST

TDIRB/

T4PWM/T4CMP/

PDPINTA

PLLF2

PLLF

T1PWM/T1CMP/

T2PWM/T2CMP/

XINT2/ADCSOC/

SCITXD/

SPISOMI/

SPISTE/

SPICLK/

DDO

PZ PACKAGE†

( TOP VIEW)

TDIRA/

TMS320LC2404A PZ

TMS320LC2406A PZ

TMS320LF2406A PZ

T3PWM/T3CMP/

XINT1/

PLLVCCA

TMS2

VDD

VDDO

VSS

VSSO

†Bold, italicized pin names indicate pin function after reset.

‡CANTX and CANRX are not available on LC2404A devices.

§BOOT_EN is available only on Flash devices.

¶On the ROM devices (LC240xA), VCCP is a No Connect (NC).

IOPF4

IOPF3

IOPF2

IOPB6

IOPB4

IOPB5

IOPC0

IOPD0

IOPA2

IOPA0

IOPA1

SPISIMO/IOPC2

IOPC3

IOPC5

IOPC4

IOPE7

CLKOUT

IOPA3

IOPF0

IOPA4

IOPA5

TDIRB/ IOPF4

OFF

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pinouts (continued)

PAG PACKAGE†‡

(TOP VIEW)

64 17

TMS320LF2403A PAG

TMS320LC2403A PAG

TMS320LC2402A PAG

CLKOUT/IOPE0

CAP3/IOPA5

234567 89101112131415

47 46 45 44 4342 41 40 39 38 37 36 35 34

1863

1962

2061

2160

2259

2358

2457

2556

2655

2853

2952

3051

3150

CAP2/QEP2/IOPA4

CAP1/QEP1/IOPA3

VSS

EMU0

EMU1/ OFF

VSSO

DDO

ADCIN07

ADCIN06

ADCIN05

ADCIN04

ADCIN03

ADCIN02

VREFHI

VCCA

VSSA

BOOT_EN/XF§

XTAL1/CLKIN

XTAL2

VSS

VDD

TCK

TDI

TDO

TMS

VREFLO

ADCIN00

ADCIN01CANTX/IOPC6

CANRX/IOPC7

TP2

TP1

VCCP¶

PWM1/IOPA6

PWM2/IOPA7

PWM3/IOPB0

VDD

VSS

PWM4/IOPB1

PWM5/IOPB2

VDDO

VSSO

PWM6/IOPB3

TCLKINA/IOPB7

TRST

VSSO

DDO

PDPINTA

PLLF2

PLLF

PLLVCCA

T1PWM/T1CMP/IOPB4

T2PWM/T2CMP/IOPB5

XINT2/ADCSOC/IOPD0

SCITXD/IOPA0

SCIRXD/IOPA1

TMS2

†Bold, italicized pin names indicate pin function after reset.

‡For LC2402A, the following pins are different from what is shown:

Pin 45: IOPC2

Pin 46: IOPC3

Pin 47: IOPC4

Pin 63: IOPC7

Pin 64: IOPC6

§BOOT_EN is available only on flash devices.

¶On the ROM devices (LC240xA), VCCP is a No Connect (NC).

SPICLK/

SPISOMI/

SPISIMO/

IOPC4

IOPC3

IOPC2

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pinouts (continued)

VREFHI

VCCA

VSSA

BOOT_EN/XF‡

XTAL1/CLKIN

XTAL2

VSS

VDD

TCK

TDI

TDO

TMS

VDDO

IOPC6

IOPC7

TP2

TP1

VCCP§

PWM1/IOPA6

PWM2/IOPA7

PWM3/IOPB0

VDD

VSS

PWM4/IOPB1

PWM5/IOPB2

ADCIN00

PDPINTA

PLLF2

PLLF

T1PWM/T1CMP/

T2PWM/T2CMP/

SCITXD/

EMU0

TMS2

TCLKINA/

PWM6/

CAP1/QEP1/

CAP2/QEP2/

CAP3/

CLKOUT

ADCIN01

ADCIN02

ADCIN03

ADCIN04

ADCIN05

ADCIN06

ADCIN07

REFLO

SCIRXD/

XINT2/ADCSOC/

PLLVCCA

EMU1/

TRST

TMS320LC2402A PG

TMS320LF2402A PG

VSSO

DDO

VSSO

VDD

VSS

IOPB4

IOPB5

IOPD0

IOPA0

IOPA1

IOPC2

IOPC3

IOPC4

IOPB7

IOPB3

/IOPE0

IOPA5

IOPA4

IOPA3

OFF

191 2 3 4 5 6 7 8 9101112131415161718

3351 343550 49 48 47 46 45 44 43 42 41 40 3938 37 36

PG PACKAGE†

(TOP VIEW)

†Bold, italicized pin names indicate pin function after reset.

‡BOOT_EN is available only on Flash devices.

§On the ROM devices (LC240xA), VCCP is a No Connect (NC).

VSSO

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions

The TMS320LF2407A device is the superset of all the 240xA devices. All signals are available on the 2407A

device. Table 2 lists the signals available in the 240xA generation of devices.

Table 2. LF240xA and LC240xA Pin List and Package Options†‡

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

EVENT MANAGER A (EVA)

CAP1/QEP1/IOPA3 83 57 57 4 Capture input #1/quadrature encoder pulse input #1 (EVA) or

GPIO (↑)

CAP2/QEP2/IOPA4 79 55 55 3 Capture input #2/quadrature encoder pulse input #2 (EVA) or

GPIO (↑)

CAP3/IOPA5 75 52 52 2 Capture input #3 (EVA) or GPIO (↑)

PWM1/IOPA6 56 39 39 59 Compare/PWM output pin #1 (EVA) or GPIO (↑)

PWM2/IOPA7 54 37 37 58 Compare/PWM output pin #2 (EVA) or GPIO (↑)

PWM3/IOPB0 52 36 36 57 Compare/PWM output pin #3 (EVA) or GPIO (↑)

PWM4/IOPB1 47 33 33 54 Compare/PWM output pin #4 (EVA) or GPIO (↑)

PWM5/IOPB2 44 31 31 53 Compare/PWM output pin #5 (EVA) or GPIO (↑)

PWM6/IOPB3 40 28 28 50 Compare/PWM output pin #6 (EVA) or GPIO (↑)

T1PWM/T1CMP/IOPB4 16 12 12 40 Timer 1 compare output (EVA) or GPIO (↑)

T2PWM/T2CMP/IOPB5 18 13 13 41 Timer 2 compare output (EVA) or GPIO (↑)

TDIRA/IOPB6 14 11 11

Counting direction for general-purpose (GP) timer (EVA) or

GPIO. If TDIRA = 1, upward counting is selected. If

TDIRA = 0, downward counting is selected. (↑)

TCLKINA/IOPB7 37 26 26 49 External clock input for GP timer (EVA) or GPIO. Note that

the timer can also use the internal device clock. (↑)

EVENT MANAGER B (EVB)

CAP4/QEP3/IOPE7 88 60 60 Capture input #4/quadrature encoder pulse input #3 (EVB) or

GPIO (↑)

CAP5/QEP4/IOPF0 81 56 56 Capture input #5/quadrature encoder pulse input #4 (EVB) or

GPIO (↑)

CAP6/IOPF1 69 48 48 Capture input #6 (EVB) or GPIO (↑)

PWM7/IOPE1 65 45 45 Compare/PWM output pin #7 (EVB) or GPIO (↑)

PWM8/IOPE2 62 43 43 Compare/PWM output pin #8 (EVB) or GPIO (↑)

PWM9/IOPE3 59 41 41 Compare/PWM output pin #9 (EVB) or GPIO (↑)

PWM10/IOPE4 55 38 38 Compare/PWM output pin #10 (EVB) or GPIO (↑)

PWM11/IOPE5 46 32 32 Compare/PWM output pin #11 (EVB) or GPIO (↑)

PWM12/IOPE6 38 27 27 Compare/PWM output pin #12 (EVB) or GPIO (↑)

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

EVENT MANAGER B (EVB) (CONTINUED)

T3PWM/T3CMP/IOPF2 8 7 7 Timer 3 compare output (EVB) or GPIO (↑)

T4PWM/T4CMP/IOPF3 6 5 5 Timer 4 compare output (EVB) or GPIO (↑)

TDIRB/IOPF4 2 2 2

Counting direction for general-purpose (GP) timer

(EVB) or GPIO. If TDIRB = 1, upward counting is

selected. If TDIRB = 0, downward counting is

selected. (↑)

TCLKINB/IOPF5 126 89 89

External clock input for GP timer (EVB) or GPIO.

Note that the timer can also use the internal

device clock. (↑)

ANALOG-TO-DIGITAL CONVERTER (ADC)

ADCIN00 112 79 79 18 Analog input #0 to the ADC

ADCIN01 110 77 77 17 Analog input #1 to the ADC

ADCIN02 107 74 74 16 Analog input #2 to the ADC

ADCIN03 105 72 72 15 Analog input #3 to the ADC

ADCIN04 103 70 70 14 Analog input #4 to the ADC

ADCIN05 102 69 69 13 Analog input #5 to the ADC

ADCIN06 100 67 67 12 Analog input #6 to the ADC

ADCIN07 99 66 66 11 Analog input #7 to the ADC

ADCIN08 113 80 80 Analog input #8 to the ADC

ADCIN09 111 78 78 Analog input #9 to the ADC

ADCIN10 109 76 76 Analog input #10 to the ADC

ADCIN11 108 75 75 Analog input #11 to the ADC

ADCIN12 106 73 73 Analog input #12 to the ADC

ADCIN13 104 71 71 Analog input #13 to the ADC

ADCIN14 101 68 68 Analog input #14 to the ADC

ADCIN15 98 65 65 Analog input #15 to the ADC

VREFHI 115 82 82 20 ADC analog high-voltage reference input

VREFLO 114 81 81 19 ADC analog low-voltage reference input

VCCA 116 83 83 21 Analog supply voltage for ADC (3.3 V)§

VSSA 117 84 84 22 Analog ground reference for ADC

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)

CANRX/IOPC7

CANRX 70 49 −63 CAN receive data or GPIO (LF2403A) (↑)

CANRX/IOPC7 IOPC7 70 49 49 63 GPIO only (2402A) (↑)

CANTX/IOPC6

CANTX 72 50 −64 CAN transmit data or GPIO (LF2403A) (↑)

CANTX/IOPC6 IOPC6 72 50 50 64 GPIO only (2402A) (↑)

SCITXD/IOPA0 25 17 17 43 SCI asynchronous serial port transmit data or GPIO (↑)

SCIRXD/IOPA1 26 18 18 44 SCI asynchronous serial port receive data or or

GPIO (↑)

SPICLK/IOPC4

SPICLK 35 24 24 47 SPI clock or GPIO (LF2403A) (↑)

SPICLK/IOPC4 IOPC4 35 24 24 47 GPIO only (2402A) (↑)

SPISIMO/IOPC2

SPISIMO 30 21 21 45 SPI slave in, master out or GPIO (LF2403A) (↑)

SPISIMO/IOPC2 IOPC2 30 21 21 45 GPIO only (2402A) (↑)

SPISOMI/IOPC3

SPISOMI 32 22 22 46 SPI slave out, master in or GPIO (LF2403A) (↑)

SPISOMI/IOPC3 IOPC3 32 22 22 46 GPIO only (2402A) (↑)

SPISTE/IOPC5

SPISTE 33 23 23 −

SPI slave transmit enable (optional) or GPIO (↑)

SPISTE/IOPC5 IOPC5 33 23 23 −SPI slave transmit-enable (optional) or GPIO (↑)

EXTERNAL INTERRUPTS, CLOCK

RS 133 93 93 28

Device Reset (in) and Watchdog Reset (out).

Device reset. RS causes the device to terminate execution

and to set PC = 0. When RS is brought to a high level,

execution begins at location 0x0000 of program memory.

This pin is driven low by the DSP when a watchdog reset

occurs. During watchdog reset, the RS pin will be driven

low for the watchdog reset duration of 128 CLKIN cycles.

The output buffer of this pin is an open-drain with an

internal pullup (20 µA, typical). It is recommended that this

pin be driven by an open-drain device. (↑)

PDPINTA 7 6 6 36

Power drive protection interrupt input. This interrupt, when

activated, puts the PWM output pins (EVA) in the

high-impedance state should motor drive/power converter

abnormalities, such as overvoltage or overcurrent, etc.,

arise. PDPINTA is a falling-edge-sensitive interrupt. (↑)

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

EXTERNAL INTERRUPTS, CLOCK (CONTINUED)

XINT1/IOPA2 23 16 16

External user interrupt 1 or GPIO. Both XINT1 and XINT2

are edge-sensitive. The edge polarity is

programmable. (↑)

XINT2/ADCSOC/IOPD0 21 15 15 42

External user interrupt 2 and ADC start of conversion or

GPIO. External “start-of-conversion” input for ADC/GPIO.

Both XINT1 and XINT2 are edge-sensitive. The edge

polarity is programmable. (↑)

CLKOUT/IOPE0 73 51 51 1

Clock output or GPIO. This pin outputs either the CPU clock

(CLKOUT) or the watchdog clock (WDCLK). The selection

is made by the CLKSRC bit (bit 14) of the system control

and status register (SCSR). This pin can be used as a GPIO

if not used as a clock output pin. (↑)

PDPINTB 137 95 95

Power drive protection interrupt input. This interrupt, when

activated, puts the PWM output pins (EVB) in the

high-impedance state should motor drive/power converter

abnormalities, such as overvoltage or overcurrent, etc.,

arise. PDPINTB is a falling-edge-sensitive interrupt. (↑)

OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS

XTAL1/CLKIN 123 87 87 24

PLL oscillator input pin. Crystal input to PLL/clock source

input to PLL. XTAL1/CLKIN is tied to one side of a reference

crystal.

XTAL2 124 88 88 25

Crystal output. PLL oscillator output pin. XTAL2 is tied to

one side of a reference crystal. This pin goes in the

high-impedance state when EMU1/OFF is active low.

PLLVCCA 12 10 10 39 PLL supply (3.3 V)

IOPF6 131 92 92 General-purpose I/O (↑)

BOOT

EN /

BOOT_EN 121 86 −23

Boot ROM enable, GPO, XF. This pin will be sampled as

input (BOOT_EN) to update SCSR2.3 (BOOT_EN bit)

durin

reset and then driven as an out

ut si

nal for XF. After

BOOT

EN /

XF 121 86 86 23

during reset and then driven as an output signal for XF

After

reset, XF is driven high. ROM devices do not have boot

ROM, hence, no BOOT_EN modes. The BOOT_EN pin

must be driven with a passive circuit only. (↑)

PLLF 11 9 9 38 PLL loop filter input 1

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED)

PLLF2 10 8 8 37 PLL loop filter input 2

VCCP (5V) 58 40 40 60

Flash programming voltage pin. This pin must be connected to

a 5-V supply for Flash programming. The Flash cannot be

programmed if this pin is connected to GND. When not

programming the Flash (i.e., during normal device operation),

this pin can either be left connected to the 5-V supply or it can

be tied to GND. This pin must not be left floating at any time. Do

not use any current-limiting resistor in series with the 5-V supply

on this pin. This pin is a “no connect” (NC) on ROM parts (i.e.,

this pin is not connected to any circuitry internal to the device).

Connecting this pin to 5 V or leaving it open makes no difference

on ROM parts.

TP1 60 42 42 61 Test pin 1. Do not connect.

TP2 63 44 44 62 Test pin 2. Do not connect.

BIO/IOPC1 119 85 85

Branch control input. BIO is polled by the BCND pma,BIO

instruction. If BIO is low, a branch is executed. If BIO is not used,

it should be pulled high. This pin is configured as a branch

control input by all device resets. It can be used as a GPIO, if

not used as a branch control input. (↑)

EMULATION AND TEST

EMU0 90 61 61 7

Emulator I/O #0 with internal pullup. When TRST is driven high,

this pin is used as an interrupt to or from the emulator system

and is defined as input/output through the JTAG scan. (↑)

EMU1/OFF 91 62 62 8

Emulator pin 1. Emulator pin 1 disables all outputs. When TRST

is driven high, EMU1/OFF is used as an interrupt to or from the

emulator system and is defined as an input/output through the

JTAG scan. When TRST is driven low, this pin is configured as

OFF. EMU1/OFF, when active low, puts all output drivers in the

high-impedance state. Note that OFF is used exclusively for

testing and emulation purposes (not for multiprocessing

applications). Therefore, for the OFF condition, the following

apply:

TRST = 0

EMU0 = 1

EMU1/OFF = 0 (↑)

TCK 135 94 94 29 JTAG test clock with internal pullup (↑)

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately

for proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

EMULATION AND TEST (CONTINUED)

TDI 139 96 96 30

JTAG test data input (TDI) with internal pullup. TDI

is clocked into the selected register (instruction or

data) on a rising edge of TCK. (↑)

TDO 142 99 99 31

JTAG scan out, test data output (TDO). The

contents of the selected register (instruction or

data) is shifted out of TDO on the falling edge of

TCK. (↓)

TMS 144 100 100 32

JTAG test-mode select (TMS) with internal pullup.

This serial control input is clocked into the TAP

controller on the rising edge of TCK. (↑)

TMS2 36 25 25 48

JTAG test-mode select 2 (TMS2) with internal

pullup. This serial control input is clocked into the

TAP controller on the rising edge of TCK. Used for

test and emulation only. This pin can be left

unconnected in user applications. If the PLL bypass

mode is desired, TMS2, TMS, and TRST should be

held low during reset. (↑)

TRST 1 1 1 33

JTAG test reset with internal pulldown. TRST, when

driven high, gives the scan system control of the

operations of the device. If this signal is not

connected or driven low, the device operates in its

functional mode, and the test reset signals are

ignored. (↓)

NOTE: Do not use pullup resistors on TRST; it has

an internal pulldown device. TRST is an active high

test pin and must be maintained low at all times

during normal device operation. In a low-noise

environment, TRST may be left floating. In other

instances, an external pulldown resistor is highly

recommended. The value of this resistor should be

based on drive strength of the debugger pods

applicable to the design. A 2.2-kΩ resistor generally

offers adequate protection. Since this is

application−specific, it is recommended that each

target board be validated for proper operation of the

debugger and the application. (I ↓)

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS

DS 87

Data space strobe. IS, DS, and PS are always

high unless low-level asserted for access to the

relevant external memory space or I/O. They are

placed in the high-impedance state.¶

IS 82

I/O space strobe. IS, DS, and PS are always high

unless low-level asserted for access to the

relevant external memory space or I/O. They are

placed in the high-impedance state.¶

PS 84

Program space strobe. IS, DS, and PS are always

high unless low-level asserted for access to the

relevant external memory space or I/O. They are

placed in the high-impedance state.¶

R/W 92

Read/write qualifier signal. R/W indicates transfer

direction during communication to an external

device. It is normally in read mode (high), unless

low level is asserted for performing a write

operation. R/W is placed in the high-impedance

state.¶

W/R / IOPC0

W/R 19

Write/Read qualifier or GPIO. This is an inverted

R/W signal useful for zero-wait-state memory

interface. It is normall

low

unless a memor

write

W/R / IOPC0

IOPC0 19 14 14

interface

It is normally low

unless a memory write

operation is performed. See Table 12, Port C

section, for reset note regarding LF2406A and

LF2402A. (↑)

RD 93

Read-enable strobe. Read-select indicates an

active, external read cycle. RD is active on all

external program, data, and I/O reads. RD is

placed in the high-impedance state.¶

WE 89

Write-enable strobe. The falling edge of WE

indicates that the device is driving the external

data bus (D15−D0). WE is active on all external

program, data, and I/O writes. WE is placed in the

high-impedance state.¶

STRB 96

External memory access strobe. STRB is always

high unless asserted low to indicate an external

bus cycle. STRB is active for all off-chip

accesses. STRB is placed in the high-impedance

state.¶

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)

READY 120

READY is pulled low to add wait states for external accesses.

READY indicates that an external device is prepared for a bus

transaction to be completed. If the device is not ready, it pulls the

READY pin low. The processor waits one cycle and checks

READY again. Note that the processor performs

READY-detection if at least one software wait state is

programmed. To meet the external READY timing parameters,

the wait-state generator control register (WSGR) should be

programmed for at least one wait state. (↑)

MP/MC 118

Microprocessor/Microcomputer mode select. If this pin is low

during reset, the device is put in microcomputer mode and

program execution begins at 0000h of internal program memory

(Flash EEPROM). A high value during reset puts the device in

microprocessor mode and program execution begins at 0000h

of external program memory. This line sets the MP/MC bit (bit 2

in the SCSR2 register). (↓)

ENA_144 122

Active high to enable external interface signals. If pulled low, the

2407A behaves like the 2406A/2403A/2402A—i.e., it has no

external memory and generates an illegal address if DS is

asserted. This pin has an internal pulldown. (↓)

VIS_OE 97

Visibility output enable (active when data bus is output). This pin

is active (low) whenever the external data bus is driving as an

output during visibility mode. Can be used by external decode

logic to prevent data bus contention while running in visibility

mode.

A0 80 Bit 0 of the 16-bit address bus

A1 78 Bit 1 of the 16-bit address bus

A2 74 Bit 2 of the 16-bit address bus

A3 71 Bit 3 of the 16-bit address bus

A4 68 Bit 4 of the 16-bit address bus

A5 64 Bit 5 of the 16-bit address bus

A6 61 Bit 6 of the 16-bit address bus

A7 57 Bit 7 of the 16-bit address bus

A8 53 Bit 8 of the 16-bit address bus

A9 51 Bit 9 of the 16-bit address bus

A10 48 Bit 10 of the 16-bit address bus

A11 45 Bit 11 of the 16-bit address bus

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)

A12 43 Bit 12 of the 16-bit address bus

A13 39 Bit 13 of the 16-bit address bus

A14 34 Bit 14 of the 16-bit address bus

A15 31 Bit 15 of the 16-bit address bus

D0 127 Bit 0 of 16-bit data bus (↑)

D1 130 Bit 1 of 16-bit data bus (↑)

D2 132 Bit 2 of 16-bit data bus (↑)

D3 134 Bit 3 of 16-bit data bus (↑)

D4 136 Bit 4 of 16-bit data bus (↑)

D5 138 Bit 5 of 16-bit data bus (↑)

D6 143 Bit 6 of 16-bit data bus (↑)

D7 5 Bit 7 of 16-bit data bus (↑)

D8 9 Bit 8 of 16-bit data bus (↑)

D9 13 Bit 9 of 16-bit data bus (↑)

D10 15 Bit 10 of 16-bit data bus (↑)

D11 17 Bit 11 of 16-bit data bus (↑)

D12 20 Bit 12 of 16-bit data bus (↑)

D13 22 Bit 13 of 16-bit data bus (↑)

D14 24 Bit 14 of 16-bit data bus (↑)

D15 27 Bit 15 of 16-bit data bus (↑)

POWER SUPPLY

29 20 20 6

50 35 35 27

Core supply 3 3 V Digital logic supply voltage

VDD#

86 59 59 56 Core supply +3.3 V. Digital logic supply voltage.

129 91 91

4 4 4 10

42 30 30 35

67 47 47 52 I/O buffer suppl

+3.3 V. Di

ital lo

ic and buffer suppl

VDDO#

77 54 54

I/O buffer supply +3

3 V

Digital logic and buffer supply

voltage.

95 64 64

141 98 98

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

POWER SUPPLY (CONTINUED)

28 19 19 5

49 34 34 26

Core ground Digital logic ground reference

VSS#

85 58 58 55 Core ground. Digital logic ground reference.

128 90 90

3 3 3 9

41 29 29 34

66 46 46 51

VSSO#76 53 53 I/O buffer ground. Digital logic and buffer ground reference.

VSSO

94 63 63

I/O buffer ground. Digital logic and buffer ground reference.

125 97 97

140

†Bold, italicized pin names indicate pin function after reset.

‡GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for

proper device operation.

LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory maps

ÈÈÈÈÈÈÈÈÈ

ÉÉÉÉÉÉÉÉÉ

Reserved

0000

Hex Program

On-Chip Flash Memory (Sectored) − if MP/MC = 0

External Program Memory − if MP/MC = 1

7FFF

8000

0000

005F

0060

Hex Data

Memory-Mapped

Registers/Reserved Addresses

007F

0080

On-Chip DARAM B2

01FF

Illegal

02FF

0300

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

ÈÈÈÈÈÈÈÈÈ

03FF

0400

On-Chip DARAM (B1)¶

07FF

0800

Reserved

6FFF

7000

Illegal

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, SPI, CAN, I/O, Interrupts)

7FFF

8000

External

0000

Hex I/O

FEFF

FF00

FF0E

FF0F

Reserved

External

FFFF

FEFF

FF00

FDFF

FE00

External

On-Chip DARAM (B0)‡ (CNF = 1)

External (CNF = 0)

FFFF

FFFE

Wait-State Generator Control

FF10

Flash Control Mode Register

SARAM (See Table 1 for details.)

FFFF

SARAM (2K)

Internal (PON = 1)

External (PON=0)

87FF

8800

0FFF

1000

3FFF

Flash Sector 1 (12K)

Flash Sector 2 (12K)

Flash Sector 3 (4K)

4000

6FFF

7000

0FFF

1000

0200

ÉÉÉÉÉÉÉÉÉ

SARAM (2K)

Internal (DON = 1)

Reserved (DON=0)

ÉÉÉ

ÈÈÈ

Reserved or Illegal

Flash Sector 0 (4K)

Interrupt Vectors (0000−003Fh)

Reserved† (0040−0043h)

User code begins at 0044h

Reserved‡ (CNF = 1)

External (CNF = 0)

Reserved

00FF

0100

Illegal

04FF

0500

NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.

†Addresses 0040h−0043h in on-chip program memory are reserved for code security passwords.

‡When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For

example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved when

CNF = 1.

§When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,

a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.

¶Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h

has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.

Figure 1. TMS320LF2407A Memory Map

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory maps (continued)

ÈÈÈÈÈÈÈÈÈÈ

Reserved

On-Chip Flash Memory (Sectored)

0000

005F

0060

Hex Data

Memory-Mapped

Registers/Reserved Addresses

007F

0080

On-Chip DARAM B2

ÈÈÈÈÈÈÈÈÈÈ

01FF

0200

Illegal

02FF

0300

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

03FF

0400

On-Chip DARAM (B1)¶

ÈÈÈÈÈÈÈÈÈÈ

07FF

0800

Illegal

ÉÉÉÉÉÉÉÉÉÉ

SARAM (2K)

Internal (DON = 1)

Reserved (DON = 0)

ÈÈÈÈÈÈÈÈÈÈ

6FFF

7000

Illegal

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, SPI, CAN, I/O, Interrupts)

7FFF

8000

Illegal

0000

Hex I/O

FEFF

FF00

ÈÈÈÈÈÈÈÈÈÈ

FF0E

FF0F

Reserved

Illegal

FFFF

FFFE

Reserved

FF10

Flash Control Mode Register

ÉÉÉ

SARAM (See Table 1 for details.)

FFFF

0FFF

1000

ÉÉÉÉÉÉÉÉÉÉ

Hex Program

7FFF

8000

FFFF

FEFF

FF00

FDFF

FE00

On-Chip DARAM (B0)‡ (CNF = 1)

External (CNF = 0)

SARAM (2K)

Internal (PON = 1)

Reserved (PON=0)

87FF

8800

Flash Sector 3 (4K)

6FFF

7000

Illegal

ÈÈÈ

Reserved or Illegal

0000

0FFF

1000

3FFF

Flash Sector 1 (12K)

Flash Sector 2 (12K)

Flash Sector 0 (4K)

4000

Interrupt Vectors (0000−003Fh)

Reserved† (0040−0043h)

User code begins at 0044h

Reserved‡

Reserved

00FF

0100

Reserved

04FF

0500

NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.

†Addresses 0040h−0043h in program memory are reserved for code security passwords.

‡When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For

example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.

§When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,

a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.

¶Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h

has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.

Figure 2. TMS320LF2406A Memory Map

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory maps (continued)

ÈÈÈÈÈÈÈÈÈ

Reserved

On-Chip Flash Memory (Sectored)

0000

005F

0060

Hex Data

Memory-Mapped

Registers/Reserved Addresses

007F

0080

On-Chip DARAM B2

ÈÈÈÈÈÈÈÈÈ

01FF

0200

Illegal

02FF

0300

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

03FF

0400

On-Chip DARAM (B1)¶

07FF

0800

Reserved

ÈÈÈÈÈÈÈÈÈ

6FFF

7000

Illegal

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, I/O, Interrupts)

ÈÈÈÈÈÈÈÈÈ

7FFF

8000

Illegal

0000

Hex I/O

FEFF

FF00

ÈÈÈÈÈÈÈÈÈ

FF0E

FF0F

Reserved

Illegal

FFFF

FFFE

FF10

Flash Control Mode Register

FFFF

0FFF

1000

Reserved

0000

Program

FFFF

FEFF

FF00

FDFF

FE00

On-Chip DARAM (B0)‡ (CNF = 1)

Reserved (CNF = 0)

0FFF

Hex

7FFF

8000

FFFF

FEFF

FF00

FDFF

FE00

Illegal

Flash Sector 0 (4K)

Flash Sector 1 (12K)

Reserved

87FF

8800

4000

Reserved

1000

3FFF

ÈÈÈ

Reserved or Illegal

ÉÉÉÉÉÉÉÉÉ

81FF

8200

SARAM (512 words)

Internal (PON = 1)

Reserved (PON = 0)

ÉÉÉÉÉÉÉÉÉ

SARAM (512 words)

Internal (DON = 1)

Reserved (DON = 0)

09FF

0A00