AD21365WBSWZ1XXF - Analog Devices, Inc.

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC Processors

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Technical Support www.analog.com

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—3M bits of on-chip SRAM

Code compatible with all other members of the SHARC family

The ADSP-2136x processors are available with up to 333 MHz

core instruction rate with unique audiocentric peripherals

such as the digital applications interface, S/PDIF trans-

ceiver, DTCP (digital transmission content protection

protocol), serial ports, precision clock generators, and

more. For complete ordering information, see Ordering

Guide on Page 56.

DEDICATED AUDIO COMPONENTS

S/PDIF-compatible digital audio receiver/transmitter

8 channels of asynchronous sample rate converters (SRC)

16 PWM outputs configured as four groups of four outputs

ROM-based security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Available in 136-ball CSP_BGA and 144-lead LQFP_EP

packages

Figure 1. Functional Block Diagram

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 stage

Sequencer

PEx PEy

PMD 64-BIT

Core Bus

Cross Bar

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

DAG1/2 Timer

IOD BUS

MTM/

DTCP

PERIPHERAL BUS

32-BIT

Internal Memory

DMD 64-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DAI Peripherals Peripherals

SIMD Core

Core

Flags

SPI PWM

0 PP

PP Pin MUX

PDAP/

IDP7-0

ASRC

TIMER

CORE

FLAGS

S/PDIF

Tx/Rx

PCG

B SPI B SPORT

DAI Routing/Pins

IOD 32-BIT

FLAGx/IRQx/

TMREXP JTAG

PMD 64-BIT

DMD 64-BIT

Rev. J | Page 2 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

TABLE OF CONTENTS

Summary ............................................................... 1

Dedicated Audio Components .................................... 1

General Description ................................................. 3

SHARC Family Core Architecture ............................ 4

Family Peripheral Architecture ................................ 6

I/O Processor Features ........................................... 8

System Design ...................................................... 8

Development Tools ............................................... 9

Additional Information ........................................ 10

Related Signal Chains .......................................... 10

Pin Function Descriptions ....................................... 11

Specifications ........................................................ 14

Operating Conditions .......................................... 14

Electrical Characteristics ....................................... 15

Package Information ........................................... 16

ESD Caution ...................................................... 16

Maximum Power Dissipation ................................. 16

Absolute Maximum Ratings ................................... 16

Timing Specifications ........................................... 16

Output Drive Currents ......................................... 46

Test Conditions .................................................. 46

Capacitive Loading .............................................. 46

Thermal Characteristics ........................................ 47

144-Lead LQFP_EP Pin Configurations ....................... 48

136-Ball BGA Pin Configurations ............................... 50

Package Dimensions ............................................... 53

Surface-Mount Design .......................................... 54

Automotive Products .............................................. 55

Ordering Guide ..................................................... 56

REVISION HISTORY

7/13—Revision I to Revision J

Updated Development Tools .......................................9

Added Nominal Value column in Operating Conditions .. 14

Changed Max values in Table 30 in Pulse-Width Modulation

Generators ............................................................ 35

Updated Ordering Guide .......................................... 56

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 3 of 60 | July 2013

GENERAL DESCRIPTION

The ADSP-2136x SHARC

processor is a member of the SIMD

SHARC family of DSPs that feature Analog Devices, Inc., Super

Harvard Architecture. The processor is source code-compatible

with the ADSP-2126x and ADSP-2116x DSPs, as well as with

first generation ADSP-2106x SHARC processors in SISD

(single-instruction, single-data) mode. The ADSP-2136x are

32-/40-bit floating-point processors optimized for high

performance automotive audio applications. They contain a

large on-chip SRAM and ROM, multiple internal buses to elim-

inate I/O bottlenecks, and an innovative digital audio interface

(DAI).

As shown in the functional block diagram on Page 1, the

ADSP-2136x uses two computational units to deliver a signifi-

cant performance increase over the previous SHARC processors

on a range of signal processing algorithms. With its SIMD com-

putational hardware, the ADSP-2136x can perform two

GFLOPS running at 333 MHz.

Table 1 shows performance benchmarks for these devices.

Table 2 shows the features of the individual product offerings.

The diagram on Page 1 shows the two clock domains that make

up the ADSP-2136x processors. The core clock domain contains

the following features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• One periodic interval timer with pinout

•On-chip SRAM (3M bit)

• On-chip mask-programmable ROM (4M bit)

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points, which allow flexible exception handling.

The diagram on Page 1 also shows the following architectural

features:

• I/O processor that handles 32-bit DMA for the peripherals

• Six full duplex serial ports

• Two SPI-compatible interface ports—primary on dedi-

cated pins, secondary on DAI pins

• 8-bit or 16-bit parallel port that supports interfaces to off-

chip memory peripherals

• Digital audio interface that includes two precision clock

generators (PCG), an input data port with eight serial inter-

faces (IDP), an S/PDIF receiver/transmitter, 8-channel

asynchronous sample rate converter (ASRC), DTCP

cipher, six serial ports, a 20-bit parallel input data port

(PDAP), 10 interrupts, six flag outputs, six flag inputs,

three timers, and a flexible signal routing unit (SRU)

Table 1. Benchmarks (at 333 MHz)

Benchmark Algorithm

Speed

(at 333 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs

FIR Filter (per tap)

Assumes two files in multichannel SIMD mode.

1.5 ns

IIR Filter (per biquad)

6.0 ns

Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]

13.5 ns

23.9 ns

Divide (y/x) 10.5 ns

Inverse Square Root 16.3 ns

Table 2. ADSP-2136x Family Features

Feature ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366

RAM

ROM

3M bit

4M bit

3M bit

4M bit

3M bit

4M bit

3M bit

4M bit

3M bit

4M bit

Audio Decoders in ROM

No No No Yes Yes

Pulse-Width Modulation Yes Yes Yes Yes Yes

S/PDIF Yes No Yes Yes Yes

DTCP

Yes No No Yes No

SRC SNR Performance –128 dB No SRC –140 dB –128 dB –128 dB

Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay,

speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system

configurations. Please visit www.analog.com for complete information.

The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices

sales office for more information.

Rev. J | Page 4 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SHARC FAMILY CORE ARCHITECTURE

The ADSP-2136x is code-compatible at the assembly level with

the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the

first generation ADSP-2106x SHARC processors. The

ADSP-2136x shares architectural features with the ADSP-2126x

and ADSP-2116x SIMD SHARC processors, as shown in

Figure 2 and detailed in the following sections.

SIMD Computational Engine

The processor contains two computational processing elements

that operate as a single-instruction, multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY can be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive signal

processing algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the

bandwidth between memory and the processing elements.

When using the DAGs to transfer data in SIMD mode, two data

values are transferred with each access of memory or

the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing

elements. These computation units support IEEE 32-bit,

single-precision floating-point, 40-bit extended-precision

floating-point, and 32-bit fixed-point data formats.

Figure 2. SHARC Core Block Diagram

SIMD Core

CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1

16x32

MRF

80-BIT

ALU

MULTIPLIER SHIFTER

Rx/Fx

PEx

16x40-BIT

JTAG

DMD/PMD 64

PM DATA 48

ASTATx

STYKx

ASTATy

STYKy

TIMER

Sx/SFx

PEy

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

USTAT

4x32-BIT

64-BIT

DAG2

16x32

ALU MULTIPLIER

SHIFTER

DATA

SWAP

PM ADDRESS 24

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 5 of 60 | July 2013

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register (16 primary, 16 secondary) files, combined

with the ADSP-2136x enhanced Harvard architecture, allow

unconstrained data flow between computation units and inter-

nal memory. The registers in PEX are referred to as R0–R15 and

in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result register all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

Universal Registers

The universal registers are general purpose registers. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all system registers (control/status) of

the core.

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM/DM data bus. These

registers contain hardware to handle the data width difference.

Timer

A core timer that can generate periodic software interrupts. The

core timer can be configured to use FLAG3 as a timer expired

signal.

Single-Cycle Fetch of Instruction and Four Operands

The processor features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 2). With the its separate program and data memory

buses and on-chip instruction cache, the processor can simulta-

neously fetch four operands (two over each data bus) and one

instruction (from the cache), all in a single cycle.

Instruction Cache

The processor includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The processor’s two data address generators (DAGs) are used

for indirect addressing and implementing circular data buffers

in hardware. Circular buffers allow efficient programming of

delay lines and other data structures required in digital signal

processing, and are commonly used in digital filters and Fourier

transforms. The two DAGs contain sufficient registers to allow

the creation of up to 32 circular buffers (16 primary register sets,

16 secondary). The DAGs automatically handle address pointer

wraparound, reduce overhead, increase performance, and sim-

plify implementation. Circular buffers can start and end at any

memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations for concise programming. For example, the

processor can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

On-Chip Memory

The processor contains 3M bits of internal SRAM and 4M bits

of internal ROM. Each block can be configured for different

combinations of code and data storage (see Table 3). Each

memory block supports single-cycle, independent accesses by

the core processor and I/O processor. The processor’s memory

architecture, in combination with its separate on-chip buses,

allows two data transfers from the core and one from the I/O

processor, in a single cycle.

The SRAM can be configured as a maximum of 96K words of

32-bit data, 192K words of 16-bit data, 64K words of 48-bit

instructions (or 40-bit data), or combinations of different word

sizes up to 3M bits. All of the memory can be accessed as 16-bit,

32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage

format is supported that effectively doubles the amount of data

that can be stored on-chip. Conversion between the 32-bit

floating-point and 16-bit floating-point formats is performed in

a single instruction. While each memory block can store combi-

nations of code and data, accesses are most efficient when one

block stores data using the DM bus for transfers, and the other

block stores instructions and data using the PM bus for

transfers.

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

On-Chip Memory Bandwidth

The internal memory architecture allows three accesses at the

same time to any of the four blocks, assuming no block con-

flicts. The total bandwidth is gained with DMD and PMD buses

(2 × 64-bits, core CLK) and the IOD bus (32-bit, PCLK).

ROM-Based Security

The processor has a ROM security feature that provides hard-

ware support for securing user software code by preventing

unauthorized reading from the internal code. When using this

feature, the processor does not boot-load any external code, exe-

cuting exclusively from internal ROM. Additionally, the

processor is not freely accessible via the JTAG port. Instead, a

unique 64-bit key, which must be scanned in through the JTAG

Rev. J | Page 6 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

or test access port, is assigned to each customer. The device

ignores a wrong key. Emulation features and external boot

modes are only available after the correct key is scanned.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2136x family contains a rich set of peripherals that

support a wide variety of applications, including high quality

audio, medical imaging, communications, military, test equip-

ment, 3D graphics, speech recognition, monitor control,

imaging, and other applications.

Parallel Port

The parallel port provides interfaces to SRAM and peripheral

devices. The multiplexed address and data pins (AD15–0) can

access 8-bit devices with up to 24 bits of address, or 16-bit

devices with up to 16 bits of address. In either mode, 8-bit or

16-bit, the maximum data transfer rate is f

PCLK

/4.

DMA transfers are used to move data to and from internal

memory. Access to the core is also facilitated through the paral-

lel port register read/write functions. The RD, WR, and ALE

(address latch enable) pins are the control pins for the

parallel port.

Serial Peripheral (Compatible) Interface

The processors contain two serial peripheral interface ports

(SPIs). The SPI is an industry-standard synchronous serial link,

enabling the processor’s SPI-compatible port to communicate

with other SPI-compatible devices. The SPI consists of two data

pins, one device select pin, and one clock pin. It is a full-duplex

synchronous serial interface, supporting both master and slave

modes and can operate at a maximum baud rate of f

PCLK

/4.

The SPI port can operate in a multimaster environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The ADSP-2136x SPI-

compatible peripheral implementation also features program-

mable baud rate, clock phase, and polarities. The SPI-

compatible port uses open drain drivers to support a multimas-

ter configuration and to avoid data contention.

Pulse-Width Modulation

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

Table 3. ADSP-2136x Internal Memory Space

IOP Registers 0x0000 0000–0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM

0x0004 0000–0x0004 7FFF

Block 0 ROM

0x0008 0000–0x0008 AAA9

Block 0 ROM

0x0008 0000–0x0008 FFFF

Block 0 ROM

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 BFFF

Reserved

0x0009 0000–0x0009 7FFF

Reserved

0x0012 0000–0x0012 FFFF

Block 0 SRAM

0x0004 C000–0x0004 FFFF

Block 0 SRAM

0x0009 0000–0x0009 5554

Block 0 SRAM

0x0009 8000–0x0009 FFFF

Block 0 SRAM

0x0013 0000–0x0013 FFFF

Block 1 ROM

0x0005 0000–0x0005 7FFF

Block 1 ROM

0x000A 0000–0x000A AAA9

Block 1 ROM

0x000A 0000–0x000A FFFF

Block 1 ROM

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 BFFF

Reserved

0x000B 0000–0x000B 7FFF

Reserved

0x0016 0000–0x0016 FFFF

Block 1 SRAM

0x0005 C000–0x0005 FFFF

Block 1 SRAM

0x000B 0000–0x000B 5554

Block 1 SRAM

0x000B 8000–0x000B FFFF

Block 1 SRAM

0x0017 0000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 1FFF

Block 2 SRAM

0x000C 0000–0x000C 2AA9

Block 2 SRAM

0x000C 0000–0x000C 3FFF

Block 2 SRAM

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000–0x0006 FFFF

Reserved

0x000C 4000–0x000D FFFF

Reserved

0x0018 8000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 1FFF

Block 3 SRAM

0x000E 0000–0x000E 2AA9

Block 3 SRAM

0x000E 0000–0x000E 3FFF

Block 3 SRAM

0x001C 0000–0x001C 7FFF

Reserved

0x0007 2000–0x0007 FFFF

Reserved

0x000E 4000–0x000F FFFF

Reserved

0x001C 8000–0x001F FFFF

Reserved

0x0020 0000–0xFFFF FFFF

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 7 of 60 | July 2013

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode,

the duty cycle values are programmable only once per PWM

period. This results in PWM patterns that are symmetrical

about the midpoint of the PWM period. In double update

mode, a second updating of the PWM registers is implemented

at the midpoint of the PWM period. In this mode, it is possible

to produce asymmetrical PWM patterns that produce lower

harmonic distortion in 3-phase PWM inverters.

Digital Audio Interface (DAI)

The digital audio interface (DAI) provides the ability to connect

various peripherals to any of the DSP’s DAI pins (DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU, shown in Figure 1).

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the

DAI-associated peripherals for a wider variety of applications by

using a larger set of algorithms than is possible with nonconfig-

urable signal paths.

The DAI includes six serial ports, an S/PDIF receiver/transmit-

ter, a DTCP cipher, a precision clock generator (PCG), eight

channels of asynchronous sample rate converters, an input data

port (IDP), an SPI port, six flag outputs and six flag inputs, and

three timers. The IDP provides an additional input path to the

ADSP-2136x core, configurable as either eight channels of I

serial data or as seven channels plus a single 20-bit wide syn-

chronous parallel data acquisition port. Each data channel has

its own DMA channel that is independent from the processor’s

serial ports.

Serial Ports

The processor features six synchronous serial ports that provide

an inexpensive interface to a wide variety of digital and mixed-

signal peripheral devices such as Analog Devices’ AD183x fam-

ily of audio codecs, ADCs, and DACs. The serial ports are made

up of two data lines, a clock, and a frame sync and they can

operate at maximum f

PCLK

/4. The data lines can be pro-

grammed to either transmit or receive and each data line has a

dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of audio data when all six SPORTs are enabled,

or six full duplex TDM streams of 128 channels per frame.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in four modes:

• Standard DSP serial mode

•Multichannel (TDM) mode

•I

S mode

• Left-justified sample pair mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF transmitter has no separate DMA channels. It

receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the transmitter

can be formatted as left-justified, I

S, or right-justified with

word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

transmitter are routed through the signal routing unit (SRU).

They can come from a variety of sources such as the SPORTs,

external pins, the precision clock generators (PCGs), or the

sample rate converters (SRC) and are controlled by the SRU

control registers.

Digital Transmission Content Protection (DTCP)

The DTCP specification defines a cryptographic protocol for

protecting audio entertainment content from illegal copying,

intercepting, and tampering as it traverses high performance

digital buses, such as the IEEE 1394 standard. Only legitimate

entertainment content delivered to a source device via another

approved copy protection system (such as the DVD content

scrambling system) is protected by this copy protection system.

This feature is available on the ADSP-21362 and

ADSP-21365 processors only. Licensing through DTLA is

required for these products. Visit www.dtcp.com for more

information.

Memory-to-Memory (MTM)

If the DTCP module is not used, the memory-to-memory DMA

module allows internal memory copies for a standard DMA.

Synchronous/Asynchronous Sample Rate Converter (SRC)

The sample rate converter (SRC) contains four SRC blocks and

is the same core as that used in the AD1896 192 kHz stereo

asynchronous sample rate converter and provides up to 140 dB

SNR. The SRC block is used to perform synchronous or

asynchronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-

vert multichannel audio data without phase mismatches.

Finally, the SRC is used to clean up audio data from jittery clock

sources such as the S/PDIF receiver.

The S/PDIF and SRC are not available on the ADSP-21363

models.

Input Data Port (IDP)

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

Rev. J | Page 8 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

audio channels in I2S, left-justified sample pair, or right-justi-

fied mode. One frame sync cycle indicates one 64-bit left/right

pair, but data is sent to the FIFO as 32-bit words (that is, one-

half of a frame at a time). The processor supports 24- and 32-bit

S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit

right-justified formats.

Precision Clock Generator (PCG)

The precision clock generators (PCG) consist of two units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A and B, are identi-

cal in functionality and operate independently of each other.

The two signals generated by each unit are normally used as a

serial bit clock/frame sync pair.

Peripheral Timers

The following three general-purpose timers can generate peri-

odic interrupts and be independently set to operate in one of

three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

Each general-purpose timer has one bidirectional pin and four

registers that implement its mode of operation: a 6-bit configu-

ration register, a 32-bit count register, a 32-bit period register,

and a 32-bit pulse width register. A single control and status

independently.

I/O PROCESSOR FEATURES

The processor’s I/O provides many channels of DMA and con-

trols the extensive set of peripherals described in the previous

sections.

DMA Controller

The processor’s on-chip DMA controllers allow data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the processor’s internal memory and its serial ports, the

SPI-compatible (serial peripheral interface) ports, the IDP

(input data port), the parallel data acquisition port (PDAP), or

the parallel port (PP). See Table 4.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory of the processor boots at system power-up

from an 8-bit EPROM via the parallel port, an SPI master, an

SPI slave, or an internal boot. Booting is determined by the boot

configuration (BOOT_CFG1–0) pins in Table 5. Selection of the

boot source is controlled via the SPI as either a master or slave

device, or it can immediately begin executing from ROM.

Phase-Locked Loop

The processors use an on-chip phase-locked loop (PLL) to gen-

erate the internal clock for the core. On power-up, the

CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and

6:1. After booting, numerous other ratios can be selected via

software control.

The ratios are made up of software configurable numerator val-

ues from 1 to 64 and software configurable divisor values of 1, 2,

4, and 8.

Power Supplies

The processor has a separate power supply connection for the

internal (V

DDINT

), external (V

DDEXT

), and analog (A

VDD

VSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement for K, B, and Y grade models, and the 1.0 V

requirement for Y models. (For information on the temperature

ranges offered for this product, see Operating Conditions on

Page 14, Package Information on Page 16, and Ordering Guide

on Page 56.) The external supply must meet the 3.3 V require-

ment. All external supply pins must be connected to the same

power supply.

Note that the analog supply pin (A

VDD

) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

VDD

pin. Place the filter components as close as possible to the

VDD

VSS

pins. For an example circuit, see Figure 3. (A

recommended ferrite chip is the muRata BLM18AG102SN1D.)

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V

DDINT

and GND. Use wide traces

to connect the bypass capacitors to the analog power (A

VDD

)

and ground (A

VSS

) pins. Note that the A

VDD

and A

VSS

pins

specified in Figure 3 are inputs to the processor and not the ana-

log ground plane on the board—the A

VSS

pin should connect

directly to digital ground (GND) at the chip.

Table 4. DMA Channels

Peripheral ADSP-2136x

SPORTs 12

IDP/PDAP 8

SPI 2

MTM/DTCP 2

Parallel Port 1

Total DMA Channels 25

Table 5. Boot Mode Selection

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot

01 SPI Master Boot

10 Parallel Port Boot via EPROM

11 No booting occurs. Processor executes

from internal ROM after reset.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 9 of 60 | July 2013

Target Board JTAG Emulator Connector

Analog Devices’ DSP Tools product line of JTAG emulators

uses the IEEE 1149.1 JTAG test access port of the processor to

monitor and control the target board processor during emula-

tion. Analog Devices’ DSP Tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor’s JTAG interface ensures that the

emulator does not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, refer to the

appropriate emulator user’s guide.

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore

Embed-

ded Studio and/or VisualDSP++

), evaluation products,

emulators, and a wide variety of software add-ins.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

The newest IDE, CrossCore Embedded Studio, is based on the

Eclipse

framework. Supporting most Analog Devices proces-

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information visit

www.analog.com/cces.

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite

evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders

, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

EZ-KIT Lite Evaluation Kits

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

Board Support Packages for Evaluation Hardware

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

•www.analog.com/ucos3

•www.analog.com/ucfs

•www.analog.com/ucusbd

•www.analog.com/lwip

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

Figure 3. Analog Power (A

VDD

) Filter Circuit

HIGH-Z FERRITE

BEAD CHIP

LOCATE ALL COMPONENTS

CLOSE TO A

VDD

AND A

VSS

PINS

VDD

VSS

100nF 10nF 1nF ADSP-213xx

DDINT

Rev. J | Page 10 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the Engineer-to-Engineer

Note “Analog Devices JTAG Emulation Technical Reference”

(EE-68) on the Analog Devices website (www.analog.com)—use

site search on “EE-68.” This document is updated regularly to

keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

processor’s architecture and functionality. For detailed informa-

tion on the ADSP-2136x family core architecture and

instruction set, refer to the ADSP-2136x SHARC Processor

Hardware Reference and the ADSP-2136x SHARC Processor

Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab

site

(http://www.analog.com/signalchains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 11 of 60 | July 2013

PIN FUNCTION DESCRIPTIONS

The processor’s pin definitions are listed below. Inputs identi-

fied as synchronous (S) must meet timing requirements with

respect to CLKIN (or with respect to TCK for TMS and TDI).

Inputs identified as asynchronous (A) can be asserted asynchro-

nously to CLKIN (or to TCK for TRST). Tie or pull unused

inputs to V

DDEXT

or GND, except for the following:

DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, and

AD15–0. Note: These pins have pull-up resistors.

Table 6. Pin Descriptions

Pin Type

State During and

After Reset Function

AD15–0 I/O/T

(pu)

Three-state with

pull-up enabled

Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding DMA

unit output addresses and data for peripherals on these multiplexed pins. The multiplex

state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit

mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. For details about the AD pin

operation, refer to the ADSP-2136x SHARC Processor Hardware Reference.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16

external address bits, ADDR23–8; ALE is used in conjunction with an external latch to

retain the values of the ADDR23–8.

For detailed information on I/O operations and pin multiplexing, refer to the ADSP-2136x

SHARC Processor Hardware Reference.

RD O

(pu)

Three-state, driven

high

Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or 16-

bit data from an external memory device. When AD15–0 are flags, this pin remains

deasserted. RD has a 22.5 kΩ internal pull-up resistor.

WR O

(pu)

Three-state, driven

high

Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or

16-bit data to an external memory device. When AD15–0 are flags, this pin remains

deasserted. WR has a 22.5 kΩ internal pull-up resistor.

ALE O

(pd)

Three-state, driven

low

Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives a

new address on the parallel port address pins. On reset, ALE is active high. However, it

can be reconfigured using software to be active low. When AD15–0 are flags, this pin

remains deasserted. ALE has a 20 kΩ internal pull-down resistor.

FLAG[0]/IRQ0/SPI

FLG[0]

I/O FLAG[0] INPUT FLAG0/Interrupt Request0/SPI0 Slave Select.

FLAG[1]/IRQ1/SPI

FLG[1]

I/O FLAG[1] INPUT FLAG1/Interrupt Request1/SPI1 Slave Select.

FLAG[2]/IRQ2/SPI

FLG[2]

I/O FLAG[2] INPUT FLAG2/Interrupt Request 2/SPI2 Slave Select.

FLAG[3]/TMREXP/

SPIFLG[3]

I/O FLAG[3] INPUT FLAG3/Timer Expired/SPI3 Slave Select.

DAI_P20–1 I/O/T

(pu)

Three-state with

programmable

pull-up

Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The

SRU configuration registers define the combination of on-chip peripheral inputs or

outputs connected to the pin and to the pin’s output enable. The configuration registers

of these peripherals then determine the exact behavior of the pin. Any input or output

signal present in the SRU can be routed to any of these pins. The SRU provides the

connection from the serial ports, input data port, precision clock generators and timers,

sample rate converters and SPI to the DAI_P20–1 pins. These pins have internal 22.5 kΩ

pull-up resistors that are enabled on reset. These pull-ups can be disabled using the

DAI_PIN_PULLUP register.

The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,

S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.

Rev. J | Page 12 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPICLK I/O

(pu)

Three-state with

pull-up enabled,

driven high in SPI-

master boot mode

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the

rate at which data is transferred. The master can transmit data at a variety of baud rates.

SPICLK cycles once for each bit transmitted. SPICLK is a gated clock active during data

transfers, only for the length of the transferred word. Slave devices ignore the serial clock

if the slave select input is driven inactive (high). SPICLK is used to shift out and shift in

the data driven on the MISO and MOSI lines. The data is always shifted out on one clock

edge and sampled on the opposite edge of the clock. Clock polarity and clock phase

relative to data are programmable into the SPICTL control register and define the transfer

format. SPICLK has a 22.5 kΩ internal pull-up resistor.

SPIDS I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select the

processor as an SPI slave device. This input signal behaves like a chip select, and is

provided by the master device for the slave devices. In multimaster mode the processor’s

SPIDS signal can be driven by a slave device to signal to the processor (as SPI master)

that an error has occurred, as some other device is also trying to be the master device. If

asserted low when the device is in master mode, it is considered a multimaster error. For

a single-master, multiple-slave configuration where flag pins are used, this pin must be

tied or pulled high to V

DDEXT

on the master device. For processor to processor SPI inter-

action, any of the master processor’s flag pins can be used to drive the SPIDS signal on

the SPI slave device.

MOSI I/O (O/D)

(pu)

Three-state with

pull-up enabled,

driven low in SPI-

master boot mode

SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin

becomes a data transmit (output) pin, transmitting output data. If the processor is

configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input

data. In an SPI interconnection, the data is shifted out from the MOSI output pin of the

master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pull-

up resistor.

MISO I/O (O/D)

(pu)

Three-state with

pull-up enabled

SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin

becomes a data receive (input) pin, receiving input data. If the processor is configured

as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data.

In an SPI interconnection, the data is shifted out from the MISO output pin of the slave

and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up

resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register.

Note: Only one slave is allowed to transmit data at any given time. To enable broadcast

transmission to multiple SPI slaves, the processor’s MISO pin can be disabled by setting

Bit 5 (DMISO) of the SPICTL register equal to 1.

CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input. It

configures the ADSP-2136x to use either its internal clock generator or an external clock

source. Connecting the necessary components to CLKIN and XTAL enables the internal

clock generator. Connecting the external clock to CLKIN while leaving XTAL uncon-

nected configures the processors to use the external clock source such as an external

clock oscillator. The core is clocked either by the PLL output or this clock input depending

on the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated

below the specified frequency.

XTAL O Output only

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

CLK_CFG1–0 I Input only Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the

operating frequency can be changed by programming the PLL multiplier and divider in

the PMCTL register at any time after the core comes out of reset. The allowed values are:

00 = 6:1

01 = 32:1

10 = 16:1

11 = reserved.

Table 6. Pin Descriptions (Continued)

Pin Type

State During and

After Reset Function

The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,

S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 13 of 60 | July 2013

BOOT_CFG1–0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor.

The BOOT_CFG pins must be valid before reset is asserted. For a description of the boot

mode, refer to Table 5, Boot Mode Selection.

RESETOUT O Output only Reset Out. Drives out the core reset signal to an external device.

RESET I/A Input only Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is a

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

TCK I Input only

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the processors.

TMS I/S

(pu)

Three-state with

pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

TDI I/S

(pu)

Three-state with

pull-up enabled

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

TDO O Three-state

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST I/A

(pu)

Three-state with

pull-up enabled

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-2136x. TRST has a 22.5 kΩ

internal pull-up resistor.

EMU O (O/D)

(pu)

Three-state with

pull-up enabled

Emulation Status. Must be connected to the processor’s JTAG emulators target board

connector only. EMU has a 22.5 kΩ internal pull-up resistor.

DDINT

PCore Power Supply. Supplies the processor’s core.

DDEXT

PI/O Power Supply.

VDD

PAnalog Power Supply. Supplies the processor’s internal PLL (clock generator). This pin

has the same specifications as V

DDINT

, except that added filtering circuitry is required. For

more information, see Power Supplies on Page 8.

VSS

GAnalog Power Supply Return.

GND G Power Supply Return.

RD, WR, and ALE are three-stated (and not driven) only when RESET is active.

Output only is a three-state driver with its output path always enabled.

Input only is a three-state driver with both output path and pull-up disabled.

Three-state is a three-state driver with pull-up disabled.

Table 6. Pin Descriptions (Continued)

Pin Type

State During and

After Reset Function

The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,

S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.

Rev. J | Page 14 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPECIFICATIONS

Specifications are subject to change without notice.

OPERATING CONDITIONS

K Grade B Grade Y Grade

Parameter Description Min Nom Max Min Nom Max Min Nom Max Unit

DDINT

Internal (Core) Supply

Voltage

1.14 1.2 1.26 1.14 1.2 1.26 0.95 1.0 1.05 V

VDD

Analog (PLL) Supply Voltage 1.14 1.2 1.26 1.14 1.2 1.26 0.95 1.0 1.05 V

DDEXT

External (I/O) Supply Voltage 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V

Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, and TRST.

High Level Input Voltage @

DDEXT

= Max

2.0 V

DDEXT

+ 0.5 2.0 V

DDEXT

+ 0.5 2.0 V

DDEXT

+ 0.5 V

Low Level Input Voltage @

DDEXT

= Min

–0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V

IH_CLKIN

Applies to input pin CLKIN.

High Level Input Voltage @

DDEXT

= Max

1.74 V

DDEXT

+ 0.5 1.74 V

DDEXT

+ 0.5 1.74 V

DDEXT

+ 0.5 V

IL_CLKIN

Low Level Input Voltage @

DDEXT

= Min

–0.5 +1.19 –0.5 +1.19 –0.5 +1.19 V

See Thermal Characteristics on Page 47 for information on thermal specifications.

See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for further information.

Junction Temperature

136-Ball CSP_BGA

0 +110 –40 +125 –40 +125 °C

3, 4

Junction Temperature

144-Lead LQFP_EP

0 +110 –40 +125 –40 +125 °C

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 15 of 60 | July 2013

ELECTRICAL CHARACTERISTICS

Parameter Description Test Conditions Min Max Unit

High Level Output Voltage @ V

DDEXT

= Min, I

= –1.0 mA

2.4 V

Low Level Output Voltage @ V

DDEXT

= Min, I

= 1.0 mA

0.4 V

3, 4

High Level Input Current @ V

DDEXT

= Max, V

= V

DDEXT

Max 10 μA

Low Level Input Current @ V

DDEXT

= Max, V

= 0 V 10 μA

ILPU

Low Level Input Current Pull-Up @ V

DDEXT

= Max, V

= 0 V 200 μA

OZH

5, 6

Three-State Leakage Current @ V

DDEXT

= Max, V

= V

DDEXT

Max 10 μA

OZL

Three-State Leakage Current @ V

DDEXT

= Max, V

= 0 V 10 μA

OZLPU

Three-State Leakage Current Pull-Up @ V

DDEXT

= Max, V

= 0 V 200 μA

DD-INTYP

7, 8

Supply Current (Internal) t

CCLK

= Min, V

DDINT

= Nom 800 mA

AVDD

Supply Current (Analog) A

VDD

= Max 10 mA

10,

Input Capacitance f

= 1 MHz, T

CASE

= 25°C, V

= 1.2 V 4.7 pF

Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, and XTAL.

See Output Drive Currents on Page 46 for typical drive current capabilities.

Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, and CLKIN.

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

Applies to three-stateable pins: FLAG3–0.

Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, and MOSI.

Typical internal current data reflects nominal operating conditions.

See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

Rev. J | Page 16 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

PACKAGE INFORMATION

The information presented in Figure 4 provides details about

the package branding for the ADSP-2136x processor. For a

complete listing of product availability, see Ordering Guide on

Page 56.

ESD CAUTION

MAXIMUM POWER DISSIPATION

See the Engineer-to-Engineer Note “Estimating Power for the

ADSP-21362 SHARC Processors” (EE-277) for detailed thermal

and power information regarding maximum power dissipation.

For information on package thermal specifications, see Thermal

Characteristics on Page 47.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 8 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. For

voltage reference levels, see Figure 39 on Page 46 under Test

Conditions.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

VCO

specified in Table 11.

Figure 4. Typical Package Brand

Table 7. Package Brand Information

Brand Key Field Description

t Temperature Range

pp Package Type

Z RoHS Compliant Designation

cc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

# RoHS Compliant Designation

yyww Date Code

tppZ-cc

ADSP-2136x

#yyww country_of_origin

vvvvvv.x n.n

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid

performance degradation or loss of functionality.

Table 8. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V

DDINT

)–0.3 V to +1.5 V

Analog (PLL) Supply Voltage (A

VDD

)–0.3 V to +1.5 V

External (I/O) Supply Voltage (V

DDEXT

)–0.3 V to +4.6 V

Input Voltage –0.5 V to +3.8 V

Output Voltage Swing –0.5 V to V

DDEXT

+ 0.5 V

Load Capacitance 200 pF

Storage Temperature Range –65°C to +150°C

Junction Temperature While Biased 125°C

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 17 of 60 | July 2013

• The product of CLKIN and PLLM must never exceed 1/2

VCO

(max) in Table 11 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f

VCO

(max) in Table 11 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

VCO

= 2 × PLLM × f

INPUT

CCLK

= (2 × PLLM × f

INPUT

) ÷ (2 × PLLN)

where:

VCO

= VCO output

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

PLLN = 1, 2, 4, 8 based on the PLLD value programmed on the

PMCTL register. During reset this value is 1.

INPUT

= Input frequency to the PLL.

INPUT

= CLKIN when the input divider is disabled or

INPUT

= CLKIN ÷ 2 when the input divider is enabled

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in Table 9. All

of the timing specifications for the ADSP-2136x peripherals are

defined in relation to t

PCLK

. Refer to the peripheral specific sec-

tion for each peripheral’s timing information.

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, refer to the ADSP-2136x SHARC Processor

Hardware Reference.

Table 9. Clock Periods

Timing

Requirements Description

CLKIN Clock Period

CCLK

Processor Core Clock Period

PCLK

Peripheral Clock Period = 2 × t

CCLK

Figure 5. Core Clock and System Clock Relationship to CLKIN

CLKOUT (TEST ONLY)*

LOOP

FILTER

PLL

fVCO ÷ (2 × PLLM)

VCO PLL

DIVIDER

PMCTL

(2 × PLLN)

fVCO

fCCLK

CLK_CFGx/

PMCTL (2 × PLLM)

CLKIN

PCLK

XTAL

CLKIN

DIVIDER

RESETOUT

DELAY OF

4096 CLKIN

CYCLES

RESET

BUF

PMCTL

(INDIV)

PMCTL

(PLLBP)

BYPASS

MUX

PIN MUX

DIVIDE

BY 2

RESETOUT

PMCTL (CLKOUTEN)

CCLK

CORERST

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

fINPUT

Rev. J | Page 18 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 10. Note that during power-up, when the V

DDINT

power

supply comes up after V

DDEXT

, a leakage current of the order of

three-state leakage current pull-up, pull-down, may be observed

on any pin, even if that is an input only (for example the RESET

pin) until the V

DDINT

rail has powered up.

Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

RESET Low Before V

DDINT

DDEXT

On 0 ns

IVDDEVDD

DDINT

On Before V

DDEXT

–50 +200 ms

CLKVDD

CLKIN Valid After V

DDINT

DDEXT

Valid 0 200 ms

CLKRST

CLKIN Valid Before RESET Deasserted 10

μs

PLLRST

PLL Control Setup Before RESET Deasserted 20 μs

Switching Characteristic

CORERST

Core Reset Deasserted After RESET Deasserted 4096t

+ 2 t

CCLK

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate

default states at all I/O pins.

The 4096 cycle count depends on t

SRST

specification in Table 12. If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles

maximum.

Figure 6. Power-Up Sequencing

tRSTVDD

tCLKVDD

tCLKRST

tCORERST

tPLLRST

VDDEXT

VDDINT

CLKIN

CLK_CFG1–0

RESET

RESETOUT

tIVDDEVDD

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 19 of 60 | July 2013

Clock Input

Clock Signals

The processor can use an external clock or a crystal. Refer to the

CLKIN pin description in Table 6 on Page 11. The user applica-

tion program can configure the processor to use its internal

clock generator by connecting the necessary components to the

CLKIN and XTAL pins. Figure 8 shows the component connec-

tions used for a fundamental frequency crystal operating in

parallel mode.

Note that the clock rate is achieved using a 16.67 MHz crystal

and a PLL multiplier ratio 16:1. (CCLK:CLKIN achieves a clock

speed of 266.72 MHz.) To achieve the full core clock rate, pro-

grams need to configure the multiplier bits in the

PMCTL register.

Table 11. Clock Input

Parameter

200 MHz

Applies to all 200 MHz models. See Ordering Guide on Page 56.

333 MHz

Applies to all 333 MHz models. See Ordering Guide on Page 56.

Unit

Min Max Min Max

Timing Requirements

CLKIN Period 30

Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in the PMCTL register.

100 18 100 ns

CKL

CLKIN Width Low 12.5 7.5 ns

CKH

CLKIN Width High 12.5 7.5 ns

CKRF

CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 ns

CCLK

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CCLK

CCLK Period 5.0 10 3.0 10 ns

VCO

See Figure 5 on Page 17 for VCO diagram.

VCO Frequency 200 600 200 800 MHz

CKJ

6, 7

Actual input jitter should be combined with AC specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN Jitter Tolerance –250 +250 –250 +250 ps

Figure 7. Clock Input

CLKIN

tCK

tCKL

tCKH

tCKJ

Figure 8. Recommended Circuit for Fundamental Mode Crystal Operation

22pF Y1

1M * XTAL

CLKIN

22pF

24.576MHz

ADSP-2136x

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS.

*TYPICAL VALUES

47Ω

Rev. J | Page 20 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 12. Reset

Parameter Min Unit

Timing Requirements

WRST

RESET Pulse Width Low 4 × t

SRST

RESET Setup Before CLKIN Low 8 ns

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

and CLKIN (not including start-up time of external clock oscillator).

Figure 9. Reset

CLKIN

RESET

tSRST

tWRST

Table 13. Interrupts

Parameter Min Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

PCLK

+2 ns

Figure 10. Interrupts

INTERRUPT

INPUTS

tIPW

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 21 of 60 | July 2013

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP pin).

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse-width modulation) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 14. Core Timer

Parameter Min Unit

Switching Characteristic

WCTIM

TMREXP Pulse Width 2 × t

PCLK

– 1 ns

Figure 11. Core Timer

FLAG3

(TMREXP)

tWCTIM

Table 15. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer Pulse Width Output 2 × t

PCLK

– 1 2 × (2

– 1) × t

PCLK

Figure 12. Timer PWM_OUT Timing

PWM

OUTPUTS

tPWMO

Rev. J | Page 22 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in WDTH_CAP (pulse width count and capture)

mode. Timer signals are routed to the DAI_P20–1 pins through

the SRU. Therefore, the timing specification provided below are

valid at the DAI_P20–1 pins.

DAI Pin to Pin Direct Routing

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 16. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

Timer Pulse Width 2 × t

PCLK

2 × (2

– 1) × t

PCLK

Figure 13. Timer Width Capture Timing

TIMER

CAPTURE

INPUTS

tPWI

Table 17. DAI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns

Figure 14. DAI Pin to Pin Direct Routing

DAI_Pn

DAI_Pm

tDPIO

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 23 of 60 | July 2013

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 through DAI_P20).

Table 18. Precision Clock Generator (Direct Pin Routing)

K and B Grade Y Grade

Parameter Min Max Max Unit

Timing Requirements

PCGIP

Input Clock Period t

PCLK

× 4 ns

STRIG

PCG Trigger Setup Before Falling

Edge of PCG Input Clock

4.5 ns

HTRIG

PCG Trigger Hold After Falling

Edge of PCG Input Clock

3ns

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync

Active Edge Delay After PCG Input

Clock

2.5 10 10 ns

DTRIGCLK

PCG Output Clock Delay After PCG

Trigger

2.5 + (2.5 × t

PCGIP

) 10 + (2.5 × t

PCGIP

) 12 + (2.5 × t

PCGIP

)ns

DTRIGFS

PCG Frame Sync Delay After PCG

Trigger

2.5 + ((2.5 + D – PH) × t

PCGIP

) 10 + ((2.5 + D – PH) × t

PCGIP

) 12 + ((2.5 + D – PH) × t

PCGIP

)ns

PCGOP

Output Clock Period 2 × t

PCGIP

– 1 ns

D = FSxDIV, PH = FSxPHASE. For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Gener-

ators” chapter.

In normal mode, t

PCGOP

(min) = 2 × t

PCGIP

Figure 15. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

PCG_TRIGx_I

DAI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

PCG_CLKx_O

DAI_Pz

PCG_FSx_O

tDTRIGFS

tDTRIGCLK

tDPCGIO

tSTRIG tHTRIG

tPCGOP

tDPCGIO

tPCGIP

Rev. J | Page 24 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Flags

The timing specifications provided below apply to the FLAG3–0

and DAI_P20–1 pins, the parallel port, and the serial peripheral

interface (SPI). See Table 6 on Page 11 for more information on

flag use.

Table 19. Flags

Parameter Min Unit

Timing Requirement

FIPW

FLAG3–0 IN Pulse Width 2 × t

PCLK

+ 3 ns

Switching Characteristic

FOPW

FLAG3–0 OUT Pulse Width 2 × t

PCLK

– 1 ns

Figure 16. Flags

FLAG

INPUTS

FLAG

OUTPUTS

tFOPW

tFIPW

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 25 of 60 | July 2013

Memory Read—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the processor is

accessing external memory space.

Table 20. 8-Bit Memory Read Cycle

Parameter

K and B Grade Y Grade

Min Max Min Max Unit

Timing Requirements

DRS

AD7–0 Data Setup Before RD High 3.3 4.5 ns

DRH

AD7–0 Data Hold After RD High 0 0 ns

DAD

AD15–8 Address to AD7–0 Data Valid D + t

PCLK

– 5.0 D + t

PCLK

– 5.0 ns

Switching Characteristics

ALEW

ALE Pulse Width 2 × t

PCLK

– 2.0 2 × t

PCLK

– 2.0 ns

ADAS

AD15–0 Address Setup Before ALE Deasserted t

PCLK

– 2.5 t

PCLK

– 2.5 ns

RRH

Delay Between RD Rising Edge to Next

Falling Edge

H + t

PCLK

– 1.4 H + t

PCLK

– 1.4 ns

ALERW

ALE Deasserted to Read Asserted 2 × t

PCLK

– 3.8 2 × t

PCLK

– 3.8 ns

RWALE

Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns

ADAH

AD15–0 Address Hold After ALE Deasserted t

PCLK

– 2.3 t

PCLK

– 2.3 ns

ALEHZ

ALE Deasserted to AD7–0 Address in High-Z t

PCLK

+ 3.0 t

PCLK

+ 3.8 ns

RD Pulse Width D – 2.0 D – 2.0 ns

RDDRV

AD7–0 ALE Address Drive After Read High F + H + t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 ns

ADRH

AD15–8 Address Hold After RD High H H ns

DAWH

AD15–8 Address to RD High D + t

PCLK

– 4.0 D + t

PCLK

– 4.0 ns

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 × t

PCLK

(if FLASH_MODE is set, else F = 0)

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 17. Read Cycle for 8-Bit Memory Timing

ALE

AD15–8

AD7–0

tALEW tALERW

tRWALE

tRW

tRRH

tRDDRV

tDAWH

tADAS tADAH

VALID ADDRESSVALID ADDRESS

VALID ADDRESS

VALID ADDRESS VALID

ADDRESS

VALID

ADDRESS

VALID

DATA

VALID

DATA

tADRH

tDAD tDRS tDRH

tALEHZ

NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY

TWO MEMORY READS TO PROVIDE THE NECESSARY TIMING INFORMATION.

Rev. J | Page 26 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 21. 16-Bit Memory Read Cycle

Parameter

K and B Grade Y Grade

Min Max Min Max Unit

Timing Requirements

DRS

AD15–0 Data Setup Before RD High 3.3 4.5 ns

DRH

AD15–0 Data Hold After RD High 0 0 ns

Switching Characteristics

ALEW

ALE Pulse Width 2 × t

PCLK

– 2.0 2 × t

PCLK

– 2.0 ns

ADAS

AD15–0 Address Setup Before ALE Deasserted t

PCLK

– 2.5 t

PCLK

– 2.5 ns

ALERW

ALE Deasserted to Read Asserted 2 × t

PCLK

– 3.8 2 × t

PCLK

– 3.8 ns

RRH

Delay Between RD Rising Edge to Next Falling

Edge

H + t

PCLK

– 1.4 H + t

PCLK

– 1.4 ns

RWALE

Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns

RDDRV

ALE Address Drive After Read High F + H + t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 ns

ADAH

AD15–0 Address Hold After ALE Deasserted t

PCLK

– 2.3 t

PCLK

– 2.3 ns

ALEHZ1

ALE Deasserted to Address/Data15–0 in High-Z t

PCLK

+ 3.0 t

PCLK

+ 3.8 ns

RD Pulse Width D – 2.0 D – 2.0 ns

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 × t

PCLK

(if FLASH_MODE is set, else F = 0)

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

This parameter is only available when in EMPP = 0 mode.

Figure 18. Read Cycle for 16-Bit Memory Timing

tRWALE

tRDDRV

VALID

ADDRESS

VALID DATAVALID DATAVALID ADDRESS

ALE

AD15–0

tADAS tADAH

tALEHZ

tDRS tDRH

tALEW tALERW

tRW

tRRH

NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ⬆ 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 27 of 60 | July 2013

Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the processor is

accessing external memory space.

Table 22. 8-Bit Memory Write Cycle

Parameter

K and B Grade Y Grade

Min Min Unit

Switching Characteristics

ALEW

ALE Pulse Width 2 × t

PCLK

– 2.0 2 × t

PCLK

– 2.0 ns

ADAS

AD15–0 Address Setup Before ALE Deasserted t

PCLK

– 2.8 t

PCLK

– 2.8 ns

ALERW

ALE Deasserted to Write Asserted 2 × t

PCLK

– 3.8 2 × t

PCLK

– 3.8 ns

RWALE

Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns

WRH

Delay Between WR Rising Edge to Next WR Falling Edge F + H + t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 ns

ADAH

AD15–0 Address Hold After ALE Deasserted t

PCLK

– 0.5 t

PCLK

– 0.5 ns

WR Pulse Width D – F – 2.0 D – F – 2.0 ns

ADWL

AD15–8 Address to WR Low t

PCLK

– 2.8 t

PCLK

– 3.5 ns

ADWH

AD15–8 Address Hold After WR High H H ns

DWS

AD7–0 Data Setup Before WR High D – F + t

PCLK

– 4.0 D – F + t

PCLK

– 4.0 ns

DWH

AD7–0 Data Hold After WR High H H ns

DAWH

AD15–8 Address to WR High D – F + t

PCLK

– 4.0 D – F + t

PCLK

– 4.0 ns

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 × t

PCLK

(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be  9 × t

PCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 19. Write Cycle for 8-Bit Memory Timing

AD15

8VALID

ADDRESS VALID ADDRESS

tADAS

AD7

ALE

tADAH

tADWH

tADWL

VALID DATA

tDAWH

tWRH

tRWALE

VALID

ADDRESS VALID DATA

tALEW

tALERW

tWW

tDWS

tDWH

VALID ADDRESS

NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE

SHOWS ONLY TWO MEMORY WRITES TO PROVIDE THE NECESSARY TIMING INFORMATION.

Rev. J | Page 28 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 23. 16-Bit Memory Write Cycle

Parameter

K and B Grade Y Grade

Min Min Unit

Switching Characteristics

ALEW

ALE Pulse Width 2 × t

PCLK

– 2.0 2 × t

PCLK

– 2.0 ns

ADAS

AD15–0 Address Setup Before ALE Deasserted t

PCLK

– 2.5 t

PCLK

– 2.5 ns

ALERW

ALE Deasserted to Write Asserted 2 × t

PCLK

– 3.8 2 × t

PCLK

– 3.8 ns

RWALE

Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns

WRH

Delay Between WR Rising Edge to Next WR Falling Edge F + H + t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 ns

ADAH

AD15–0 Address Hold After ALE Deasserted t

PCLK

– 2.3 t

PCLK

– 2.3 ns

WR Pulse Width D – F – 2.0 D – F – 2.0 ns

DWS

AD15–0 Data Setup Before WR High D – F + t

PCLK

– 4.0 D – F + t

PCLK

– 4.0 ns

DWH

AD15–0 Data Hold After WR High H H ns

D = (the value set by the PPDUR Bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 × t

PCLK

(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be  9 × t

PCLK

= (peripheral) clock period = 2 × t

CCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

This parameter is only available when in EMPP = 0 mode.

Figure 20. Write Cycle for 16-Bit Memory Timing

AD15

0VALID

ADDRESS VALID DATA

tADAS

ALE

tADAH

tWRH

tRWALE

tALEW tALERW

tWW

tDWS

tDWH

VALID DATA VALID

ADDRESS

NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP 0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 29 of 60 | July 2013

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync (FS) delay and frame sync setup and

hold, 2) data delay and data setup and hold, and 3) serial clock

(SCLK) width.

Serial port signals are routed to the DAI_P20–1 pins using the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 24. Serial Ports—External Clock

K and B Grade Y Grade

Parameter Min Max Max Unit

Timing Requirements

SFSE

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

HFSE

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

SDRE

Receive Data Setup Before Receive SCLK 2.5 ns

HDRE

Receive Data Hold After SCLK 2.5 ns

SCLKW

SCLK Width (t

PCLK

× 4) ÷ 2 – 2 ns

SCLK

SCLK Period t

PCLK

× 4 ns

Switching Characteristics

DFSE

Frame Sync Delay After SCLK

(Internally Generated Frame Sync in Either Transmit or Receive Mode) 9.5 11 ns

HOFSE

Frame Sync Hold After SCLK

(Internally Generated Frame Sync in Either Transmit or Receive Mode) 2 ns

DDTE

Transmit Data Delay After Transmit SCLK 9.5 11 ns

HDTE

Transmit Data Hold After Transmit SCLK 2 ns

Referenced to sample edge.

Referenced to drive edge.

Table 25. Serial Ports—Internal Clock

K and B Grade Y Grade

Parameter Min Max Max Unit

Timing Requirements

SFSI

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode) 7 ns

HFSI

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

SDRI

Receive Data Setup Before SCLK 7 ns

HDRI

Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

DFSI

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 3 3.5 ns

HOFSI

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0 ns

DFSIR

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 8 9.5 ns

HOFSIR

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0 ns

DDTI

Transmit Data Delay After SCLK 3 4.0 ns

HDTI

Transmit Data Hold After SCLK –1.0 ns

SCLKIW

Transmit or Receive SCLK Width 2 × t

PCLK

– 2 2 × t

PCLK

+ 2 2 × t

PCLK

+ 2 ns

Referenced to the sample edge.

Referenced to drive edge.

Rev. J | Page 30 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Figure 21. Serial Ports

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSI tHFSI

tHDRI

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHFSI

tDDTI

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSE

tHOFSI

tHDTI

tHFSE

tHDTE

tDDTE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSE tHFSE

tHDRE

DATA RECEIVE—EXTERNAL CLOCK

tSCLKIW

tDFSI

tSFSI

tSDRI

tSCLKW

tDFSE

tSFSE

tSDRE

tDFSE

tSFSE

tSFSI

tDFSI

tSCLKIW tSCLKW

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 31 of 60 | July 2013

Table 26. Serial Ports—External Late Frame Sync

K and B Grade Y Grade

Parameter Min Max Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit Frame Sync

or External Receive FS with MCE = 1, MFD = 0 9 10.5 ns

DDTENFS

Data Enable for MCE = 1, MFD = 0 0.5 ns

The t

DDTLFSE

and t

DDTENFS

parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0.

Figure 22. External Late Frame Sync

DRIVE SAMPLE

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

tDDTE/I

tHDTE/I

tDDTLFSE

tDDTENFS

tSFSE/I

DRIVE SAMPLE

LATE EXTERNAL TRANSMIT FS

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

tDDTE/I

tHDTE/I

tDDTLFSE

tDDTENFS

tSFSE/I

tHFSE/I

Rev. J | Page 32 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 27. Serial Ports—Enable and Three-State

K and B Grade Y Grade

Parameter Min Max Max Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK 2 ns

DDTTE

Data Disable from External Transmit SCLK 7 8.5 ns

DDTIN

Data Enable from Internal Transmit SCLK –1 ns

Referenced to drive edge.

Figure 23. Enable and Three-State

DRIVE EDGE

tDDTIN

tDDTEN tDDTTE

DAI_P20–1

(SCLK, INT)

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(SCLK, EXT)

DAI_P20–1

(DATA

CHANNEL A/B)

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 33 of 60 | July 2013

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 28. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 28. IDP

Parameter Min Unit

Timing Requirements

SISFS

Frame Sync Setup Before Clock Rising Edge 3 ns

SIHFS

Frame Sync Hold After Clock Rising Edge 3 ns

SISD

Data Setup Before Clock Rising Edge 3 ns

SIHD

Data Hold After Clock Rising Edge 3 ns

IDPCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

IDPCLK

Clock Period t

PCLK

× 4 ns

The data, clock, and frame sync signals can come from any of the DAI pins. Clock and frame sync can also come via the PCGs or SPORTs. The PCG’s input can be either

CLKIN or any of the DAI pins.

Figure 24. IDP Master Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tIDPCLK

tIDPCLKW

tSISFS tSIHFS

tSIHD

tSISD

Rev. J | Page 34 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 29. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the IDP, refer to the

ADSP-2136x SHARC Processor Hardware Reference, “Input

Data Port” chapter.

Note that the most significant 16 bits of external 20-bit PDAP

data can be provided through either the parallel port AD15–0

pins or the DAI_P20–5 pins. The remaining 4 bits can only be

sourced through DAI_P4–1. The timing below is valid at the

DAI_P20–1 pins or at the AD15–0 pins.

Table 29. Parallel Data Acquisition Port (PDAP)

Parameter Min Unit

Timing Requirements

SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns

HPCLKEN

PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns

PDSD

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.0 ns

PDHD

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns

PDCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 3 ns

PDCLK

Clock Period t

PCLK

× 4 ns

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t

PCLK

– 1 ns

PDSTRB

PDAP Strobe Pulse Width 2 × t

PCLK

– 1.5 ns

Data source pins are AD15–0 and DAI_P4–1, or DAI pins. Source pins for serial clock and frame sync are DAI pins.

Figure 25. PDAP Timing

DAI_P20–1

(PDAP_CLK)

SAMPLE EDGE

DAI_P20–1

(PDAP_HOLD)

DAI_P20–1

(PDAP_STROBE)

tPDSTRB

tPDHLDD

tPDHD

tPDSD

tSPHOLD tHPHOLD

tPDCLK

tPDCLKW

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 35 of 60 | July 2013

Pulse-Width Modulation Generators

Sample Rate Converter—Serial Input Port

The SRC input signals are routed from the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided in

Table 31 are valid at the DAI_P20–1 pins. This feature is not

available on the ADSP-21363 models.

Table 30. PWM Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWM Output Pulse Width t

PCLK

– 2 (2

– 2) × t

PCLK

PWMP

PWM Output Period 2 × t

PCLK

– 1.5 (2

– 1) × t

PCLK

Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins).

Figure 26. PWM Timing

PWM

OUTPUTS

tPWMW

tPWMP

Table 31. SRC, Serial Input Port

Parameter Min Unit

Timing Requirements

SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge 3 ns

SRCHFS

Frame Sync Hold After Serial Clock Rising Edge 3 ns

SRCSD

SDATA Setup Before Serial Clock Rising Edge 3 ns

SRCHD

SDATA Hold After Serial Clock Rising Edge 3 ns

SRCCLKW

Clock Width 36 ns

SRCCLK

Clock Period 80 ns

The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via the PCGs or SPORTs. The PCG’s

input can be either CLKIN or any of the DAI pins.

Rev. J | Page 36 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Figure 27. SRC Serial Input Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS tSRCHFS

tSRCHD

tSRCSD

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 37 of 60 | July 2013

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and should

meet setup and hold times with regard to the serial clock on the

output port. The serial data output has a hold time and delay

specification with regard to serial clock. Note that the serial

clock rising edge is the sampling edge and the falling edge is the

drive edge.

Table 32. SRC, Serial Output Port

K and B Grade Y Grade

Parameter Min Max Max Unit

Timing Requirements

SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge 3 ns

SRCHFS

Frame Sync Hold After Serial Clock Rising Edge 3 ns

Switching Characteristics

SRCTDD

Transmit Data Delay After Serial Clock Falling Edge 10.5 12.5 ns

SRCTDH

Transmit Data Hold After Serial Clock Falling Edge 2 ns

The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be

either CLKIN or any of the DAI pins.

Figure 28. SRC Serial Output Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS tSRCHFS

tSRCTDD

tSRCTDH

Rev. J | Page 38 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left justified, I

S, or right justified with word widths of 16-, 18-,

20-, or 24-bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 29 shows the right-justified mode. Frame sync is high for

the left channel and low for the right channel. Data is valid on

the rising edge of serial clock. The MSB is delayed the minimum

in 24-bit output mode or the maximum in 16-bit output mode

from a frame sync transition, so that when there are 64 serial

clock periods per frame sync period, the LSB of the data is right-

justified to the next frame sync transition.

Table 33. S/PDIF Transmitter Right-Justified Mode

Parameter Nominal Unit

Timing Requirement

RJD

FS to MSB Delay in Right-Justified Mode

16-Bit Word Mode

18-Bit Word Mode

20-Bit Word Mode

24-Bit Word Mode

SCLK

Figure 29. Right-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tRJD

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 39 of 60 | July 2013

Figure 30 shows the default I

S-justified mode. The frame sync

is low for the left channel and high for the right channel. Data is

valid on the rising edge of serial clock. The MSB is left-justified

to the frame sync transition but with a delay.

Figure 31 shows the left-justified mode. The frame sync is high

for the left channel and low for the right channel. Data is valid

on the rising edge of serial clock. The MSB is left-justified to the

frame sync transition with no delay.

Table 34. S/PDIF Transmitter I

S Mode

Parameter Nominal Unit

Timing Requirement

I2SD

FS to MSB Delay in I

S Mode 1 SCLK

Figure 30. I

S-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tI2SD

Table 35. S/PDIF Transmitter Left-Justified Mode

Parameter Nominal Unit

Timing Requirement

LJD

FS to MSB Delay in Left-Justified Mode 0 SCLK

Figure 31. Left-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tLJD

Rev. J | Page 40 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 36. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input.

This high frequency clock (TxCLK) input is divided down to

generate the internal biphase clock.

Table 36. S/PDIF Transmitter Input Data Timing

K Grade Y Grade

Parameter Min Max Min Max Unit

Timing Requirements

SISFS

Frame Sync Setup Before Serial Clock Rising Edge 3 3 ns

SIHFS

Frame Sync Hold After Serial Clock Rising Edge 3 3 ns

SISD

Data Setup Before Serial Clock Rising Edge 3 3 ns

SIHD

Data Hold After Serial Clock Rising Edge 3 3 ns

SITXCLKW

Transmit Clock Width 9 9.5 ns

SITXCLK

Transmit Clock Period 20 20 ns

SISCLKW

Clock Width 36 36 ns

SISCLK

Clock Period 80 80 ns

The serial clock, data and frame sync signals can come from any of the DAI pins.The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

Figure 32. S/PDIF Transmitter Input Timing

SAMPLE EDGE

DAI_P20–1

(TxCLK)

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSITXCLKW tSITXCLK

tSISCLKW

tSISCLK

tSISFS tSIHFS

tSISD tSIHD

Table 37. Oversampling Clock (TxCLK) Switching Characteristics

Parameter Max Unit

Frequency for TxCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync <= 1/t

SITXCLK

MHz

Frequency for TxCLK = 256 × Frame Sync 49.2 MHz

Frame Rate (FS) 192.0 kHz

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 41 of 60 | July 2013

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver. This feature is not available on the

ADSP-21363 processors.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode)

Parameter Min Max Unit

Switching Characteristics

DFSI

Frame Sync Delay After Serial Clock 5 ns

HOFSI

Frame Sync Hold After Serial Clock –2 ns

DDTI

Transmit Data Delay After Serial Clock 5 ns

HDTI

Transmit Data Hold After Serial Clock –2 ns

SCLKIW

Transmit Serial Clock Width 38 ns

Serial clock frequency is 64 ×FS where FS = the frequency of frame sync.

Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

DRIVE EDGE

tSCLKIW

tDFSI

tHOFSI

tDDTI

tHDTI

Rev. J | Page 42 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPI Interface—Master

The processor contains two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DAI. The

timing provided in Table 39 and Table 40 applies to both ports.

Table 39. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

K and B Grade Y Grade

Min Max Min Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time) 5.2 6.2 ns

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2) 8.2 9.5 ns

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid 2 2 ns

Switching Characteristics

SPICLKM

Serial Clock Cycle 8 × t

PCLK

– 2 8 × t

PCLK

– 2 ns

SPICHM

Serial Clock High Period 4 × t

PCLK

– 2 4 × t

PCLK

– 2 ns

SPICLM

Serial Clock Low Period 4 × t

PCLK

– 2 4 × t

PCLK

– 2 ns

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time) 3.0 3.0 ns

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2) 8.0 9.5 ns

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t

PCLK

– 2 4 × t

PCLK

– 2 ns

SDSCIM

FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge 4 × t

PCLK

– 2.5 4 × t

PCLK

– 3.0 ns

SDSCIM

FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2) 4 × t

PCLK

– 2.5 4 × t

PCLK

– 3.0 ns

HDSM

Last SPICLK Edge to FLAG3–0IN High 4 × t

PCLK

– 2 4 × t

PCLK

– 2 ns

SPITDM

Sequential Transfer Delay 4 × t

PCLK

– 1 4 × t

PCLK

– 1 ns

Figure 34. SPI Master Timing

tSPICHM

tSDSCIM tSPICLM tSPICLKM tHDSM tSPITDM

tDDSPIDM

tHSPIDM

tSSPIDM

DPI

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHASE = 1

CPHASE = 0

tHDSPIDM

tHSPIDM

tSSPIDM tSSPIDM

tDDSPIDM

tHDSPIDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 43 of 60 | July 2013

SPI Interface—Slave

Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications

K and B Grade Y Grade

Parameter Min Max Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle 4 × t

PCLK

– 2 ns

SPICHS

Serial Clock High Period 2 × t

PCLK

– 2 ns

SPICLS

Serial Clock Low Period 2 × t

PCLK

– 2 ns

SDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t

PCLK

2 × t

PCLK

HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t

PCLK

SSPIDS

Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

SDPPW

SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t

PCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active 0 5 5 ns

DSOE

SPIDS Assertion to Data Out Active (SPI2) 0 8 9 ns

DSDHI

SPIDS Deassertion to Data High Impedance 0 5 5.5 ns

DSDHI

SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 10 ns

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 11.0 ns

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

DSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

PCLK

5 × t

PCLK

The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, refer to the ADSP-2136x SHARC Processor Hardware

Reference, “Serial Peripheral Interface Port” chapter.

Rev. J | Page 44 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Figure 35. SPI Slave Timing

tSPICHS tSPICLS tSPICLKS tHDS tSDPPW

tSDSCO

tDSOE

tDDSPIDS

tDSDHI

tHDSPIDS

tHSPIDS

tSSPIDS

tDSDHI

tDSOV

tHSPIDS

tHDSPIDS

SPIDS

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

CPHASE = 1

CPHASE = 0

SPICLK

(CP = 0,

CP = 1)

(INPUT)

tSSPIDS

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 45 of 60 | July 2013

JTAG Test Access Port and Emulation

Table 41. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

TCK Period t

STAP

TDI, TMS Setup Before TCK High 5 ns

HTAP

TDI, TMS Hold After TCK High 6 ns

SSYS

System Inputs Setup Before TCK High 7 ns

HSYS

System Inputs Hold After TCK High 18 ns

TRSTW

TRST Pulse Width 4 × t

Switching Characteristics

DTDO

TDO Delay from TCK Low 7 ns

DSYS

System Outputs Delay After TCK Low t

÷ 2 + 7 ns

System Inputs = ADDR15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0.

System Outputs = MISO, MOSI, SPICLK, DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.

Figure 36. IEEE 1149.1 JTAG Test Access Port

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP tHTAP

tDTDO

tSSYS tHSYS

tDSYS

Rev. J | Page 46 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

OUTPUT DRIVE CURRENTS

Figure 37 shows typical I-V characteristics for the output driv-

ers of the processor. The curves represent the current drive

capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 12 on Page 20 through Table 41 on Page 45. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 38.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 39. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 38). Figure 42 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 40, Figure 41, and Figure 42 may not be linear

outside the ranges shown for Typical Output Delay versus Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) versus Load Capacitance.

Figure 37. ADSP-2136x Typical Drive

Figure 38. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 39. Voltage Reference Levels for AC Measurements

SWEEP (VDDEXT) VOLTAGE (V)

03.50.5 1.5 2.5

SOURCE(V

DDEXT

)CURRENT(mA)

VOL

3.11V, +125°C

3.3V, +25°C

3.47V,

45°C

VOH

3.11V, +125°C

3.3V, +25°C

3.47V,

45°C

1.0 2.0 3.0

OUTPUT

ȍ

VLOAD

30pF

1.5V

INPUT

OUTPUT

1.5V

Figure 40. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Max)

Figure 41. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Min)

LOAD CAPACITANCE (pF)

0100 250

RISEANDFALLTIMES(ns)

20015050

FALL

y = 0.0467x + 1.6323

y = 0.045x + 1.524

RISE

LOAD CAPACITANCE (pF)

0 50 100 150 200 250

RISEANDFALLTIMES(ns)

RISE

FALL

y = 0.049x + 1.5105

y=0.0482x + 1.4604

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 47 of 60 | July 2013

THERMAL CHARACTERISTICS

The processor is rated for performance over the temperature

range specified in Operating Conditions on Page 14.

Table 42 through Table 44 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board and

thermal via design comply with JEDEC standards JESD51-9

(BGA) and JESD51-5 (LQFP_EP). The junction-to-case mea-

surement complies with MIL-STD-883. All measurements use a

2S2P JEDEC test board.

Industrial applications using the BGA package require thermal

vias, to an embedded ground plane, in the PCB. Refer to JEDEC

standard JESD51-9 for printed circuit board thermal ball land

and thermal via design information.

Industrial applications using the LQFP_EP package require

thermal trace squares and thermal vias, to an embedded ground

plane, in the PCB. Refer to JEDEC standard JESD51-5 for more

information.

To determine the junction temperature of the device while on

the application PCB, use:

where:

= junction temperature (°C)

= case temperature (°C) measured at the top center of the

package

= junction-to-top (of package) characterization parameter

is the typical value from Table 42 through Table 44.

= power dissipation. See the Engineer-to-Engineer Note

“Estimating Power for the ADSP-21362 SHARC Processors”

(EE-277) for more information.

Values of θ

are provided for package comparison and PCB

design considerations.

Values of θ

are provided for package comparison and PCB

design considerations when an exposed pad is required. Note

that the thermal characteristics values provided in Table 42

through Table 44 are modeled values.

Figure 42. Typical Output Delay or Hold versus Load Capacitance

(at Ambient Temperature)

LOAD CAPACITANCE (pF)

0 20050 100 150

OUTPUTDELAYORHOLD(ns)

y=0.0488x

1.5923

TJTTJT PD

+=

Table 42. Thermal Characteristics for BGA (No Thermal vias

in PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 25.40 °C/W

JMA

Airflow = 1 m/s 21.90 °C/W

JMA

Airflow = 2 m/s 20.90 °C/W

5.07 °C/W

Airflow = 0 m/s 0.140 °C/W

JMT

Airflow = 1 m/s 0.330 °C/W

JMT

Airflow = 2 m/s 0.410 °C/W

Table 43. Thermal Characteristics for BGA (Thermal vias in

PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 23.40 °C/W

JMA

Airflow = 1 m/s 20.00 °C/W

JMA

Airflow = 2 m/s 19.20 °C/W

5.00 °C/W

Airflow = 0 m/s 0.130 °C/W

JMT

Airflow = 1 m/s 0.300 °C/W

JMT

Airflow = 2 m/s 0.360 °C/W

Table 44. Thermal Characteristics for LQFP_EP (with

Exposed Pad Soldered to PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 16.80 °C/W

JMA

Airflow = 1 m/s 14.20 °C/W

JMA

Airflow = 2 m/s 13.50 °C/W

7.25 °C/W

Airflow = 0 m/s 0.51 °C/W

JMT

Airflow = 1 m/s 0.72 °C/W

JMT

Airflow = 2 m/s 0.80 °C/W

Rev. J | Page 48 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

144-LEAD LQFP_EP PIN CONFIGURATIONS

The following table shows the processor’s pin names and, when

applicable, their default function after reset in parentheses.

Table 45. LQFP_EP Pin Assignments

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

DDINT

37 V

DDEXT

73 GND 109

CLK_CFG0 2 GND 38 GND 74 V

DDINT

110

CLK_CFG1 3 RD 39 V

DDINT

75 GND 111

BOOT_CFG0 4 ALE 40 GND 76 V

DDINT

112

BOOT_CFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113

GND 6 AD14 42 DAI_P11 (SD3A) 78 V

DDINT

114

DDEXT

7 AD13 43 DAI_P12 (SD3B) 79 GND 115

GND 8 GND 44 DAI_P13 (SCLK3) 80 V

DDEXT

116

DDINT

DDEXT

45 DAI_P14 (SFS3) 81 GND 117

GND 10 AD12 46 DAI_P15 (SD4A) 82 V

DDINT

118

DDINT

11 V

DDINT

47 V

DDINT

83 GND 119

GND 12 GND 48 GND 84 V

DDINT

120

DDINT

13 AD11 49 GND 85 RESET 121

GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS 122

FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123

FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V

DDINT

124

AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK5) 89 SPICLK 125

GND 18 V

DDINT

54 V

DDINT

90 MISO 126

DDINT

19 GND 55 GND 91 MOSI 127

GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128

DDEXT

21 DAI_P3 (SCLK0) 57 V

DDEXT

93 V

DDINT

129

GND 22 GND 58 DAI_P20 (SFS5) 94 V

DDEXT

130

DDINT

23 V

DDEXT

59 GND 95 A

vdd

131

AD6 24 V

DDINT

60 V

DDINT

96 A

vss

132

AD5 25 GND 61 FLAG2 97 GND 133

AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 RESETOUT 134

DDINT

27 DAI_P5 (SD1A) 63 V

DDINT

99 EMU 135

GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136

AD3 29 DAI_P7 (SCLK1) 65 V

DDINT

101 TDI 137

AD2 30 V

DDINT

66 GND 102 TRST 138

DDEXT

31 GND 67 V

DDINT

103 TCK 139

GND 32 V

DDINT

68 GND 104 TMS 140

AD1 33 GND 69 V

DDINT

105 GND 141

AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142

WR 35 DAI_P9 (SD2A) 71 V

DDINT

107 XTAL 143

DDINT

36 V

DDINT

72 V

DDINT

108 V

DDEXT

144

GND 145*

*The ePAD is electrically connected to GND inside the chip (see Figure 43 and Figure 44), therefore connecting the pad to GND is optional.

For better thermal performance the ePAD should be soldered to the board and thermally connected to the GND plane with vias.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 49 of 60 | July 2013

Figure 43 shows the top view of the 144-lead LQFP_EP pin con-

figuration. Figure 44 shows the bottom view of the 144-lead

LQFP_EP lead configuration.

Figure 43. 144-Lead LQFP_EP Lead Configuration (Top View)

Figure 44. 144-Lead LQFP_EP Lead Configuration (Bottom View)

LEAD 1

LEAD 36

LEAD 108

LEAD 73

LEAD 144 LEAD 109

LEAD 37 LEAD 72

LEAD 1 INDICATOR

ADSP-2136x

144-LEAD LQFP_EP

TOP VIEW

LEAD 108

LEAD 73

LEAD 1

LEAD 36

LEAD 109 LEAD 144

LEAD 72 LEAD 37

LEAD 1 INDICATOR

GND PAD

(LEAD 145)

ADSP-2136x

144-LEAD LQFP_EP

BOTTOM VIEW

Rev. J | Page 50 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

136-BALL BGA PIN CONFIGURATIONS

The following table shows the processor’s ball names and, when

applicable, their default function after reset in parentheses.

Table 46. BGA Pin Assignments

Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.

CLK_CFG0 A01 CLK_CFG1 B01 BOOT_CFG1 C01 V

DDINT

D01

XTAL A02 GND B02 BOOT_CFG0 C02 GND D02

TMS A03 V

DDEXT

B03 GND C03 GND D04

TCK A04 CLKIN B04 GND C12 GND D05

TDI A05 TRST B05 GND C13 GND D06

RESETOUT A06 A

VSS

B06 V

DDINT

C14 GND D09

TDO A07 A

VDD

B07 GND D10

EMU A08 V

DDEXT

B08 GND D11

MOSI A09 SPICLK B09 GND D13

MISO A10 RESET B10 V

DDINT

D14

SPIDS A11 V

DDINT

B11

DDINT

A12 GND B12

GND A13 GND B13

GND A14 GND B14

DDINT

E01 FLAG1 F01 AD7 G01 AD6 H01

GND E02 FLAG0 F02 V

DDINT

G02 V

DDEXT

H02

GND E04 GND F04 V

DDEXT

G13 DAI_P18 (SD5B) H13

GND E05 GND F05 DAI_P19 (SCLK5) G14 DAI_P17 (SD5A) H14

GND E06 GND F06

GND E09 GND F09

GND E10 GND F10

GND E11 GND F11

GND E13 FLAG2 F13

FLAG3 E14 DAI_P20 (SFS5) F14

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 51 of 60 | July 2013

Figure 45 and Figure 46 show BGA pin assignments from the

bottom and top, respectively.

Note: Use the center block of ground pins to provide thermal

pathways to your printed circuit board’s ground plane.

AD5 J01 AD3 K01 AD2 L01 AD0 M01

AD4 J02 V

DDINT

K02 AD1 L02 WR M02

GND J04 GND K04 GND L04 GND M03

GND J05 GND K05 GND L05 GND M12

GND J06 GND K06 GND L06 DAI_P12 (SD3B) M13

GND J09 GND K09 GND L09 DAI_P13 (SCLK3) M14

GND J10 GND K10 GND L10

GND J11 GND K11 GND L11

DDINT

J13 GND K13 GND L13

DAI_P16 (SD4B) J14 DAI_P15 (SD4A) K14 DAI_P14 (SFS3) L14

AD15 N01 AD14 P01

ALE N02 AD13 P02

RD N03 AD12 P03

DDINT

N04 AD11 P04

DDEXT

N05 AD10 P05

AD8 N06 AD9 P06

DDINT

N07 DAI_P1 (SD0A) P07

DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08

DDEXT

N09 DAI_P5 (SD1A) P09

DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10

DDINT

N11 DAI_P7 (SCLK1) P11

DDINT

N12 DAI_P8 (SFS1) P12

GND N13 DAI_P9 (SD2A) P13

DAI_P10 (SD2B) N14 DAI_P11 (SD3A) P14

Table 46. BGA Pin Assignments (Continued)

Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.

Rev. J | Page 52 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Figure 45. BGA Pin Assignments (Bottom View, Summary)

VSS

DDINT

DDEXT

I/O SIGNALS

VDD

GND

KEY

12345678910111214 13

Figure 46. BGA Pin Assignments (Top View, Summary)

VSS

DDINT

DDEXT

I/O SIGNALS

VDD

GND

KEY

123456789101112 1413

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 53 of 60 | July 2013

PACKAGE DIMENSIONS

The processor is available in 136-ball BGA and 144-lead

exposed pad (LQFP_EP) packages.

Figure 47. 144-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP

]

(SW-144-1)

Dimensions shown in millimeters

For information relating to the exposed pad on the SW-144-1 package, see the table endnote on Page 48.

COMPLIANT TO JEDEC STANDARDS MS-026-BFB-HD

0.27

0.22

0.17

0.75

0.60

0.45

0.50

BSC

LEAD PITCH

20.20

20.00 SQ

19.80

22.20

22.00 SQ

21.80

EXPOSED*

PAD

72 37

108

144 109 144

109

PIN 1

1.60 MAX

SEATING

PLANE

*EXPOSED PAD IS COINCIDENT WITH BOTTOM SURFACE AND

DOES NOT PROTRUDE BEYOND IT. EXPOSED PAD IS CENTERED.

8.80 SQ

0.15

0.10

0.05 0.08

COPLANARITY

0.20

0.15

0.09

1.45

1.40

1.35

7°

3.5°

0°

VIEW A

ROTATED 90° CCW

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

VIEW A

Rev. J | Page 54 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SURFACE-MOUNT DESIGN

Table 47 is provided as an aid to PCB design. For industry stan-

dard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

Figure 48. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-136-1)

Dimensions shown in millimeters

0.25 MIN

*0.50

0.45

0.40

1.31

1.21

1.10

1.70 MAX

14 11 10 876321

12.10

12.00 SQ

11.90

10.40

BSC SQ

*COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1

WITH EXCEPTION TO BALL DIAMETER.

COPLANARITY

0.12

BALL DIAMETER

0.80

BSC

DETAIL A

A1 BALL

CORNER

A1 BALL

CORNER

DETAIL A

BOTTOM VIEW

TOP VIEW

SEATING

PLANE

Table 47. BGA Data for Use with Surface-Mount Design

Package Package Ball Attach Type

Package Solder Mask

Opening Package Ball Pad Size

136-Ball CSP_BGA (BC-136-1) Solder Mask Defined 0.40 mm diameter 0.53 mm diameter

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 55 of 60 | July 2013

AUTOMOTIVE PRODUCTS

Some ADSP-2136x models are available for automotive applica-

tions with controlled manufacturing. Note that these special

models may have specifications that differ from the general

release models.

The automotive grade products shown in Table 48 are available

for use in automotive applications. Contact your local ADI

account representative or authorized ADI product distributor

for specific product ordering information. Note that all automo-

tive products are RoHS compliant.

Table 48. Automotive Products

Model Notes

Temperature

Range

Instruction

Rate

On-Chip

SRAM ROM Package Description

Package

Option

AD21362WBBCZ1xx

–40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

AD21362WBSWZ1xx

–40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21362WYSWZ2xx

–40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21363WBBCZ1xx –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

AD21363WBSWZ1xx –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21363WYSWZ2xx –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21364WBBCZ1xx –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

AD21364WBSWZ1xx –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21364WYSWZ2xx –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21365WBSWZ1xxA

2, 3,

–40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21365WBSWZ1xxF

–40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21365WYSWZ2xxA

2, 3,

–40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21366WBBCZ1xxA

–40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

AD21366WBSWZ1xxA

–40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21366WYSWZ2xxA

–40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (T

)

specification which is the only temperature specification.

License from DTLA required for these products.

Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/sharc.

License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products.

Rev. J | Page 56 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

ORDERING GUIDE

Model

Z = RoHS compliant part.

Notes

Temperature

Range

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (T

)

specification which is the only temperature specification.

Instruction

Rate

On-Chip

SRAM ROM

Package

Description

Package

Option

ADSP-21363KBC-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

ADSP-21363KBCZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

ADSP-21363KSWZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

ADSP-21363BBC-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

ADSP-21363BBCZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

ADSP-21363BSWZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

ADSP-21363YSWZ-2AA

License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products.

–40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

ADSP-21364KBCZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

ADSP-21364KSWZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

ADSP-21364BBCZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

ADSP-21364BSWZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

ADSP-21364YSWZ-2AA –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

ADSP-21366KBCZ-1AR

Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/sharc.

R = Tape and reel.

0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

ADSP-21366KBCZ-1AA

0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

ADSP-21366KSWZ-1AA

0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 57 of 60 | July 2013

Rev. J | Page 58 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. J | Page 59 of 60 | July 2013

Rev. J | Page 60 of 60 | July 2013

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

registered trademarks are the property of their respective owners.

D06359-0-7/13(J)