[AKD4497-SA] AK4497 Evaluation Board Rev.0 1. General Description The AKD4497-SA is an evaluation board for the AK4497 (Premium 32-bit 2ch DAC) that supports Network-Audios, USB-DAC, Car-Audio Systems. It integrates differential output low pass filters, allowing quick evaluation with digital audio interface. Ordering Guide AKD4497-SA -- Evaluation Board for the AK4497 (A USB I/F board for IBM-AT compatible computers and control software are included in this package.) 2. Function 10-pin Header for Serial Control Low Pass Filters (LPF) for Pre-amplifier Outputs Digital Audio Interface (AK4118A) 2nd Order LPF Lch DIR COAX In AK4118A Opt In AK4497 Rch Figure 1. AKD4497-SA Block Diagram (Note 1) Note 1. Circuit schematics are attached at the end of this document. < KM122100> 2015/10 - 1- [AKD4497-SA] 3. Board Appearance Appearance Diagram J300 Regulator Block4 Regulator Block3 J402 Regulator Block1 Filter Block1-2 PORT300 SW300 Filter Block1-1 J400 Filter Block2-1 J401 J501 Bottom Side U300 J500 U1 PORT200 J404 SW200 PORT201 SW100 Filter Block2-2 Regulator Block2 J403 Figure 2. AKD4497-SA Outline View Description (1) Connectors for Power Supply and GND ( J500 / +15V, J404 / -15V, J501 / GND ) Connectors for power supply and the ground Refer to the "Power Supply Connections" for details. (2) SPDIF Input Connectors (J300 / BNC Connector, PORT300 / Optical Connector) Input a SPDIF signal to the AK4118A. Set the R303 resistance to short when using the J300 (BNC Connector) jack. Set the R302 resistance to short when using the PORT300 (Optical Connector). (3) Analog Differential Output Terminals (J400 / J401, XLR Connector) Differential Analog Output Connector (4) Analog Output Terminals (J402 / J403, BNC Connector) Single-ended Analog Output Connector < KM122100> 2015/10 - 2- [AKD4497-SA] (5) EXT PORT (PORT200) 10-pin Header for External Interfacing External digital audio devices are interfaced to this port. Set the R202, R204, R206 and R208 resistances to short when using the PORT200 (EXT). Pin 1 2 3 4 5 I/O I I I I I Function pin I/O Function MCLK 10 P GND BICK 9 P GND SDTO 8 P GND LRCK 7 P GND WCK 6 P GND Table 1. PORT200 (EXT) Pin Assignments (6) AK4118A (U300) The AK4118A is a digital audio transceiver. It is used when evaluating sound quality of the AK4497 by SPDIF signals. (7) P-IF PORT (PORT201) 10-pin Header for the USB I/F board Connect the USB I/F board for IBM-AT compatible computers to this port for a connection to a USB port of a PC. Refer to the "Serial Control Mode" for details (8) Dip Switches (SW100 / SW300) Setting Switches for the AK4497 and the AK4118A. Upside is "H" (ON) and Downside is "L" (OFF). Refer to " Resistance and DIP Switch Settings" for details. (9) SW200 ( Toggle switch ) Toggle type-switch PDN for AK4497 and the AK4118A. "H" : PDN = High "L" : PDN = Low < KM122100> 2015/10 - 3- [AKD4497-SA] 4. Operation Sequence Operation sequence 1). Power Supply Connections 2). Evaluation Mode 3). Resistance and DIP Switch Settings 4). Power-up Power Supply Connections Name Color Voltage J500 Red +10 to +15V Blue -10 to -15V Black 0V (REG(+15V)) J404 MVDD (AK4497), Op-Amp Op-Amp This jack is always needed. Default Setting +15V This jack is always needed. -15V Ground This jack is always needed. 0V Content Note (REG(-15V)) J501 (AVSS) Table 2. Power Supply Connections < KM122100> 2015/10 - 4- [AKD4497-SA] Evaluation Mode (1) Evaluation with a DIR (COAX) < Default > The J300 (COAX) jack is used in this mode. The DIR (AK4118A) generates MCLK, BICK, LRCK and SDATA from the input data of the J300 (COAX) connector. Set the R303 resistance to short, and set the R201 (MCLK), R203 (BICK), R207 (LRCK) and R205 (SDTO) resistances to short. Resistance Settings with DIR: COAX / OPT : R303 = short (COAX) MCLK : R201 = short (DIR) BICK : R203 = short (DIR) LRCK : R207 = short (DIR) SDTO : R205 = short (DIR) (2) Evaluation with a DIR (OPTICAL) The PORT300 (OPTICAL) is used in this mode. The DIR (AK4118A) generates MCLK, BICK, LRCK and SDATA from the input data of the PORT300 (OPTICAL) connector. Set the R302 resistance to shot, and set the R201 (MCLK), R203 (BICK), R207 (LRCK) and R205 (SDTO) jumper pins to "DIR". Resistance Settings with DIR: COAX / OPT : R302 = short (OPT) MCLK : R201 = short (DIR) BICK : R203 = short (DIR) LRCK : R207 = short (DIR) SDTO : R205 = short (DIR) (3) In the case that all interface clocks including the master clock are input externally. (PORT200) Input all interface clocks including the master clock to the PORT200 (DSP). Set R202 (MCLK), R204 (BICK), R208 (LRCK) and R206 (SDTO) resistances to short. Resistance Settings with External Clocks: COAX / OPT : R303 = short (COAX) <default> MCLK : R202 = short (EXT) BICK : R204 = short (EXT) LRCK : R208 = short (EXT) SDTO : R206 = short (EXT) < KM122100> 2015/10 - 5- [AKD4497-SA] Resistance and DIP Switch Settings (1) Resistance Settings [R201 / R202 (MCLK)]: MCLK pin input select R201 short: MCLK signal is supplied from the DIR (AK4118A). < Default > R202 short: MCLK signal is supplied from the PORT200. [R203 / R204 (BICK)]: BICK pin input select R203 short: BICK signal is supplied from the DIR (AK4118A). < Default > R204 short: BICK signal is supplied from the PORT200. [R205 / R206 (SDTO)]: SDATA pin input select R205 short: SDATA signal is supplied from the DIR (AK4118A). < Default > R206 short: SDATA signal is supplied from the PORT200. [R207 / R208 (LRCK)]: LRCK pin input select R207 short: LRCK signal is supplied from the DIR (AK4118A). < Default > R208 short: LRCK signal is supplied from the PORT200. [R303 / R302 (COAX / OPT)]: SPDIF signal for AK4118A R303 short: SPDIF signal is supplied from the J300 (COAX) connector. < Default > R302 short: SPDIF signal is supplied from the PORT300. < KM122100> 2015/10 - 6- [AKD4497-SA] (2) DIP Switch Setting Upside is ON ("H"), and Downside is OFF ("L"). [SW300]: Setting of the AK4118A No. Name ON ("H") OFF ("L") 1 OCKS1 Master Clock setting for AK4118A Refer to Table 5. 2 OCKS0 Table 3. SW300 Setting Default L L [SW100]: Setting of the AK4497 No. Name ON ("H") OFF ("L") 1 SSLOW Digital Filter Setting Refer to Table 6. 2 SD ( In Pararell Control Mode) 3 SLOW Heavy Load Mode Normal Mode HLOAD ( In Pararell Control Mode) 4 /I2C I2C-Bus 3-wire Control Mode Serial Control Mode 5 PSN 6 ACKS /CAD1 Mode 0 1 2 3 SSLOW L L L L H H H H PSN pin= "H" (Pararell Control Mode) PSN pin= "L" Serial Control Mode) Auto Setting Mode Manual Setting Mode ( In Pararell Control Mode) CAD1 pin= "H" CAD1 pin= "L" Table 4. SW100 Setting OCKS1 OCKS0 MCKO1 L L 256fs L H 256fs H L 512fs H H 128fs Table 5. Master Clock Setting fs (max) 96 kHz 96 kHz 48 kHz 192 kHz SD SLOW Mode L L Sharp roll-off filter L H Slow roll-off filter H L Short delay sharp roll-off filter H H Short delay slow roll-off filter L L Super Slow roll-off filter L H Reserved H L Low dispersion Shot Delay filter / Programable FIR filter H H Table 6. Digital Filter Setting < KM122100> Default L H L L L L < Default > < Default > 2015/10 - 7- [AKD4497-SA] Power-up Upside is ON ("H"), and Downside is OFF ("L"). [SW200] (PDN): DAC / DIR Reset control. It must be set to "H" during operation. After power-up, the AKD4497-SA must be reset once. To reset the AKD4497-SA, set the SW200 toggle switch to "L" and power down the AK4497 and the AK4118A. Then, release the power-down by setting back the SW200 to "H". < KM122100> 2015/10 - 8- [AKD4497-SA] Serial Control Mode (PSN pin = "L") When using this evaluation board in serial control mode, settings of the CAD1 pin and the CAD2 pin on the board must match the Chip Address settings of the control software. (1) 3-wire Serial Control Mode: (I2C pin= "L") (2) I2C Bus Control Mode: (I2C pin= "H") The AKD4497-SA should be connected to a PC (IBM-AT compatible) via a USB control box (AKDUSBIF-B) included in this package. The USB control box is connected to a PC with a USB cable and the AKD4497-SA with a 10-pin flat cable. (Note 2, Note 3) Note 2. The AKD4497-SA accepts only one AKDUSBIF-B at one time. It does not operate if two or more AKDUSBIF-Bs are connected. Note 3. Connect the 10pin Flat Cable as the red line of the cable is connected to the 1 pin of the 10pin Header of the board. Evaluation Board AKDXXXX-YY 10pin Flat Cable AKDUSBIF-B PC Device AKXXXX USB Cable USB Connector Set Red line to No.1 pin side. 10pin Connector Figure 3. AKDUSBIF-B Connection PC Evaluation Board AKDUSBIF-B Figure 4. AKDUSBIF-B < KM122100> 2015/10 - 9- [AKD4497-SA] 5. Control Software Manual Evaluation Board and Control Software Manual 1. Set up the evaluation board as needed, according to the previous terms. 2. Connect the evaluation board to a PC with USB cable. 3. USB control is recognized as HID (Human Interface Device) on PC. When it is not recognized properly, please reconnect the evaluation board to PC. 4. Insert the CD-ROM labeled "AKD4497-SA Evaluation Kit" into the CD-ROM drive. 5. Access the CD-ROM drive and double-click the icon "AKD4497-SA.exe" to open the control program. 6. Begin evaluation by following the procedure below. [Supported OS] Windows XP / Vista / 7 (32bit) (XP compatible mode is recommended for Vista / 7) 64bit OS is not supported. Figure 5. Control Program Window < KM122100> 2015/10 - 10- [AKD4497-SA] Operation Overview Register map is controlled by this control software. Frequently used buttons, such as the register initializing button "Write Default", are located outside of the switching tab window. Refer to the " Dialog Box" section for details of each dialog box setting. 1.[Port Reset]: Reset connection to PC Click this button after the control software starts up and the evaluation board is connected to the PC via USB cable. 2.[Write Default]: Register Initialization Use this button to initialize the registers when the device is reset by a hardware reset. 3.[All Write]: Execute write command for all registers displayed. 4.[All Read]: Execute read command for all registers displayed. (Note 2) 5.[Save]: Save current register settings to a file. 6.[Load]: Execute data write from a saved file. 7.[All Reg Write]: [All Reg Write] dialog box pops up. 8.[Data R/W]: [Data R/W] dialog box pops up. 9.[Sequence]: [Sequence] dialog box pops up. 10.[Sequence(File)]: [Sequence(File)] dialog box pops up. Note 2. The [All Read] button is only valid when the interface mode for register control is in I2C bus control mode. < KM122100> 2015/10 - 11- [AKD4497-SA] Tab Functions 1. [REG] Tab: Register Map This tab is for register read and write. Each bit on the register map is a push-button switch. Button Down indicates "1" and the bit name is shown in red (when read-only the name is shown in dark red). Button Up indicates "0" and the bit name is shown in blue (when read-only the name is shown in gray) Grayed out registers are Read-Only registers. They cannot be controlled. The registers which are not defined on the datasheet are indicated as "---". Figure 6. REG Window < KM122100> 2015/10 - 12- [AKD4497-SA] [Write] button: Data Write Dialog Select the [Write] button located on the right of the each corresponding address when changing two or more bits on the same address simultaneously. Click the [Write] button for the register pop-up dialog box shown below. When the checkbox next to the register is checked, the data will become "1". When the checkbox is not checked, the data will become "0". Click [OK] to write the set values to the registers, or click [Cancel] to cancel this setting. Figure 7. Register Set Window [Read] button: Data Read (Only in I2C-bus Control Mode) Click the [Read] button located on the right of the each corresponding address to execute a register read. The current register value will be displayed in the register window as well as in the upper right hand DEBUG window. Button Down indicates "1" and the bit name is shown in red (when read only the bit name is shown in dark red). Button Up indicates "0" and the bit name is shown in blue (when read only the bit name is shown in gray) < KM122100> 2015/10 - 13- [AKD4497-SA] Dialog Box 1. [All Reg Write]: All Register Write dialog box Click [All Reg Write] button in the main window to open register setting file window shown below. Register setting files saved by [SAVE] button may be applied. Figure 8. [All Reg Write] Window [Open (left)]: Select a register setting file (*.akr). [Write]: Execute register write with selected setting file. [Write All]: Execute register write with all selected setting files. Selected files are executed in descending order. [Help]: Open help window. [Save]: Save register setting file assignment. File name is "*.mar". [Open (right)]: Open saved register setting file assignment "*. mar". [Close]: Close dialog box and finish process. ~ Operating Suggestions ~ 1. Files saved by [Save] button and opened by [Open] button on the right of the dialog "*.mar" should be stored in the same folder. 2. When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings. < KM122100> 2015/10 - 14- [AKD4497-SA] 2. [Data R/W]: Data R/W Dialog Box Click the [Data R/W] button in the main window for data read/write dialog box. Data is written to the specified address. Figure 9. [Data R/W] Window [Address] Box: Input data write address in hexadecimal numbers. [Data] Box: Input write data in hexadecimal numbers. [Mask] Box: Input mask data in hexadecimal numbers. This value "ANDed" with the write data becomes the input data. [Write]: Write data generated from Data and Mask value is written to the address specified in "Address" box. (Note 3) [Read]: Read data from the address specified in "Address" box. (Note 4) [Close]: Close dialog box and finish process. Data write will not be executed unless [Write] is clicked. Note 3. The register map will be updated after executing the [Write] command. Note 4. The [Read] button is only valid when the interface mode for register control is in I2C bus control mode. < KM122100> 2015/10 - 15- [AKD4497-SA] 3. [Sequence]: Sequence Dialog Box Click the [Sequence] button in the main window for Sequence dialog box. Register sequence may be set and executed. Figure 10. [Sequence] Window ~ Sequence Setting ~ Set register sequence according to the following process. 1. Select a command Use [Select] pull-down box to choose commands. Corresponding input boxes will be valid. <Combo Box> * No_use: Not using this address * Register: Register write * Reg(Mask): Register write (Masked) * Interval: Take an interval * Stop: Pause the sequence * End: End the sequence < KM122100> 2015/10 - 16- [AKD4497-SA] 2. Input Sequence [Address]: Data Address [Data]: Write Data [Mask]: Mask This value "ANDed" with the write data becomes the input data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written. Upper 4bit is hold to current setting. [Interval]: Interval Time Valid boxes for each process command are shown below. No_use : None Register : [Address], [Data], [Interval] Reg(Mask) : [Address], [Data], [Mask], [Interval] Interval : [Interval] Stop : None End : None ~ Control Buttons ~ Functions of Control Buttons are shown below. [Start] button [Help] button [Save] button [Open] button [Close] button : Execute the sequence. : Open a help window. : Save sequence settings as a file. The file name is "*.aks". : Open a sequence setting file "*.aks". : Close the dialog box and finishes the process. Stop Sequence When "Stop" command is selected in the sequence, the process is paused at this step. It is resumed by clicking the [Start] button. The process starts from the step shown in [Start Step] box. This step number returns to "1" when the sequence is executed until the end. Input arbitrary step number to the [Start Step] box to start the process from the middle of sequence. The process sequence can be restarted from the beginning by writing "1" to the [Start Step] box and click the [Start] button during the process. < KM122100> 2015/10 - 17- [AKD4497-SA] 4. [Sequence(File)]: Sequence(File) Dialog Click the [Sequence(File)] button to open sequence setting file dialog box shown below. Files saved in the "Sequence setting dialog" can be applied in this dialog. Figure 11. [Sequence (File)] Window [Open (left)] button: Select a sequence setting file (*.aks) [Start ] button: Execute the sequence by the setting of selected file. [Start All] button: Execute sequence with all selected setting files. Selected files are executed in descending order. [Help] button: Open help window. [Save] button: Save register setting file assignment. File name is "*.mas". [Open (right)] button : Open saved sequence setting file assignment "*. mas". [Close] button: Close dialog box and finish process. ~ Operating Suggestions ~ 1. Files saved by [Save] button and opened by [Open] button on the right of the dialog "*.mas" should be stored in the same folder. 2. When "Stop" command is selected in the sequence, the process is paused at this step and a message shown below pops up. The sequence is resumed by clicking "OK" button. Figure 12. Sequence Pause Window < KM122100> 2015/10 - 18- [AKD4497-SA] 6. Measurement Results [Measurement condition] Measurement unit MCLK BICK fs Bit Power Supply Pass Interface Temperature Operational Amplifiers Control Soft Register : Audio Precision APX 555 Audio Analyzer : 256fs (44.1 kHz), 256fs (96 kHz), 128fs (192 kHz) : 64fs : 44.1kHz, 96kHz, 192kHz : 24bit : AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V : DIR AK4497 Cannon Connector : Internal DIR (44.1 kHz, 96 kHz, 192 kHz) : Room Temperature : OPA1611, OPA1612 : HLOAD="1", SC2="1" fs=44.1kHz Parameter Input signal S/(N+D) 1kHz, 0dB DR 1kHz, -60dB S/N "0" data Parameter Input signal S/(N+D) DR S/N 1kHz, 0dB 1kHz, -60dB "0" data Measurement filter 20kHz LPF A-weighted 20kHz LPF A-weighted Lch 116.9 dB 124.2 dB 126.5 dB 124.1 dB 126.5 dB Results / / / / / / Rch 116.6 dB 124.1 dB 126.3 dB 124.1 dB 126.4 dB Lch 114.1 dB 121.5 dB 121.6 dB Results / / / / Rch 115.1 dB 121.5 dB 121.5 dB Lch 115.3 dB 121.5 dB 121.5 dB Results / / / / Rch 114.6 dB 121.3 dB 121.6 dB fs=96kHz Measurement filter 40kHz LPF 40kHz LPF fs=192kHz Parameter Input signal S/(N+D) DR S/N 1kHz, 0dB 1kHz, -60dB "0" data Measurement filter 40kHz LPF 40kHz LPF < KM122100> 2015/10 - 19- [AKD4497-SA] Capacitance between the VREFH pin and the VREFL pin Distortion (THD+N) can be improved by increasing the capacitance of a capacitor between the VREFH pin and the VREFL pin. Applicable capacitors are C108 and C111 in the circuit schematic. C=100uF C=10uF C=470uF Figure 13. THD+N vs. Input Frequency Comparison by Capacitance < KM122100> 2015/10 - 20- [AKD4497-SA] [Plots] fs = 44.1 kHz AK4497 THD+N vs. Input Level AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 14. THD+N vs. Input Level AK4497 THD+N vs. Input Frequency AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 15. THD+N vs. Input Frequency < KM122100> 2015/10 - 21- [AKD4497-SA] fs = 44.1 kHz AK4497 Linearity AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 16. Linearity AK4497 Frequency Response AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 17. Frequency Response < KM122100> 2015/10 - 22- [AKD4497-SA] fs = 44.1 kHz AK4497 Crosstalk AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 18. Crosstalk AK4497 FFT (0dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 19. FFT (0dBFS Input) < KM122100> 2015/10 - 23- [AKD4497-SA] fs = 44.1 kHz AK4497 FFT ( -60dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 20. FFT (-60dBFS Input) AK4497 FFT ( No Signal Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz Figure 21. FFT (No Signal Input) < KM122100> 2015/10 - 24- [AKD4497-SA] fs = 96 kHz AK4497 THD+N vs. Input Level AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 22. THD+N vs. Input Level AK4497 THD+N vs. Input Frequency AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 23. THD+N vs. Input Frequency < KM122100> 2015/10 - 25- [AKD4497-SA] fs = 96 kHz AK4497 Linearity AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 24. Linearity AK4497 Frequency Response AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 25. Frequency Response < KM122100> 2015/10 - 26- [AKD4497-SA] fs = 96 kHz AK4497 Crosstalk AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 26. Crosstalk AK4497 FFT (0dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 27. FFT (0dBFS Input) < KM122100> 2015/10 - 27- [AKD4497-SA] fs = 96 kHz AK4497 FFT (-60dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 28. FFT (-60dBFS Input) AK4497 FFT (No Signal Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz Figure 29. FFT (No Signal Input) < KM122100> 2015/10 - 28- [AKD4497-SA] fs = 192 kHz AK4497 THD+N vs. Input Level AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 30. THD+N vs. Input Level AK4497 THD+N vs. Input Frequency AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 31. THD+N vs. Input Frequency < KM122100> 2015/10 - 29- [AKD4497-SA] fs = 192 kHz AK4497 Lnearity AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 32. Linearity AK4497 Frequency Response AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 33. Frequency Response < KM122100> 2015/10 - 30- [AKD4497-SA] fs = 192 kHz AK4497 Crosstalk AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 34. Crosstalk AK4497 FFT (0dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 35. FFT (0dBFS Input) < KM122100> 2015/10 - 31- [AKD4497-SA] fs = 192 kHz AK4497 FFT (-60dBFS Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 36. FFT (-60dBFS Input) AK4497 FFT (No Signal Input) AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz Figure 37. FFT (No Signal Input) < KM122100> 2015/10 - 32- [AKD4497-SA] 7. Revision History Date (y/m/d) 15/10/30 Manual Revision KM122100 Board Revision 0 Reason Page First Edition - < KM122100> Contents - 2015/10 - 33- [AKD4497-SA] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. < KM122100> 2015/10 - 34- AOUTRP AOUTRN (short) (short) R104 R103 VREFLR 28 27 C110 0.1u C 26 VREFHR 25 24 21 20 19 18 ACKS/CAD1-S DEM0/DSDL 17 open 0 open 0 open 0 open 0 open 0 R131 R130 open 0 TVDD *Default Setting GAIN/DSDR=L TDM0/DCLK=L TDM1=L DCHAIN=L INVR=L TESTE=L 12 11 10 9 8 7 R141 R140 R139 R138 R137 R136 R135 R134 R133 R132 H L SSLOW-S SD-S SLOW-S HLOAD/I2C-S PSN-S ACKS/CAD1-S R127 R126 R125 R124 R123 R122 open 0 0 open open 0 B *Default Setting DIF0/DZFL=L DIF1/DZFR=H DIF2/CAD0=L DEM0/DSDL=H TVDD AVSS AVSS SLOW-S SD-S SSLOW-S A Title Size A3 - 35- Date: 5 4 100 100 100 100 100 100 10k 10k 10k 10k 10k 10k 0 open R142 R143 R144 R145 R146 R147 R148 R149 R150 R151 R152 R153 R129 R128 SW100 1 2 3 4 5 6 22 SSLOW SD SLOW HLOAD/I2C-S PSN ACKS/CAD1 23 open 0 open 0 C111 470u(A) CDTI/SDA TVDD C107 0.1u 29 HLOAD/I2C-S PSN-S CCLK/SCL C105 10u(A) 16 HLOAD/I2C 15 PSN 14 DIF2/CAD0 13 DIF1/DZFR 12 SLOW/CDTI/SDA DIF0/DZFL 11 30 100 10 31 R112 open SMUTE/CSN SD/CCLK/SCL 9 8 100 100 R111 R110 GAIN/DSDR 32 + 35 36 37 38 39 34 AOUTRP VDDR VDDR VDDR VSSR VSSR 40 41 VSSL VSSR 33 + 0 ACKS/CAD1 R113 SSLOW R114 WCK R115 CSN R116 SMUTE-L R117 SMUTE-H R118 CCLK/SCL R119 SD R120 CDTI/SDA R121 SLOW LRCK/DINR BICK/BCK SDATA1/DSDL 0 R107 PDN-0 100p C117 AVSS 0 open R106 AVSS A TVDD R105 R108 LDOE AVSS 0 C116 1u(A) LDOE=L 42 43 45 44 VDDL VDDL 46 VDDL TVDD 1 + 47 DVSS DVDD B AOUTLP TDM0/DCLK open 64 C115 0.1u DVDD LDOE + TVDD C114 10u(A) TDM1 CSN AVSS AVSS DCHAIN MCLK TDMO 63 AVSS SSLOW/WCK 62 INVR 7 MCLK VREFHR AVDD 51 61 VREFHR TESTE R109 60 C113 0.1u VREFHR EXTR open C112 10u(A) VREFHL WCK + AVSS VREFHL 6 AVDD U1 AK4497 Plastic VREFHL 100 59 VREFLR LRCK/DINR 58 33k VREFLL SDATA/DINL R100 AVSS VREFLR 5 57 VREFLL LRCK/DINR 56 VREFLR BICK/BCK 55 VCMR VREFLL 3 54 VREFHL VCML SDATA1/DSDL 4 + C C109 0.1u AOUTRN BICK/BCK 53 C108 470u(A) AOUTRN AOUTLN PDN 52 C103 0.1u AOUTLN 2 51 C106 0.1u VREFLL 1 D VSSR C101 10u(A) C102 0.1u PDN + 50 VSSL C100 10u(A) R101 48 AOUTLP 49 AVSS + R102 D C104 10u(A) VDDR AVSS 2 AOUTRP VDDL VSSL AOUTLP (short) 3 VSSL AOUTLN (short) 4 + 5 3 2 AKD4497-SA Document Number Rev AK4497 64LQFP Wednesday, October 28, 2015 Sheet 1 0 1 of 5 A B C 1 D K MCLK-R1 R200 A 10k 1 H 3 L 1 3 5 9 11 13 14 7 SW200 PDN C200 2 0.1u AVSS U200 1A 2A 3A 4A 5A 6A VCC GND C201 0.1u BICK/BCK-R1 LRCK/DINR-R1 WCK-R1 SDATA1/DSDL-R1 2 4 6 8 10 12 1Y 2Y 3Y 4Y 5Y 6Y 1 VCC -> TVDD VCC-R1 D200 E PDN-0-R1 PDN-0-R1 R213 0 R219 0 2 3 4 5 6 7 8 9 1 19 AVSS A1 A2 A3 A4 A5 A6 A7 A8 OE1 OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 VCC GND 18 17 16 15 14 13 12 11 R214 51 MCLK R215 R216 R217 R218 51 51 51 51 BICK/BCK LRCK/DINR WCK SDATA1/DSDL PDN-0 20 10 TVDD C202 0.1u 74VCX541 AVSS 74HC14 U201 AVSS AVSS 2 2 VCC-R1 MCLK-DIR DIR R201 0 EXT R227 R209 MCLK 51 open TVDD VCC -> TVDD 100k MCLK-R1 C203 0.1u R202 DIR 0 PCA9306DP1 EXT 10k 10k 10k 10k BICK-DIR R203 R210 BICK 51 open BICK/BCK-R1 8 7 SDTO-DIR DIR R205 0 EXT R220 R221 R222 R223 R204 R211 SDTO SDATA1/DSDL-R1 51 open R224 R225 R206 LRCK-DIR DIR EXT 470 5 CDTI/SDA EN GND VREF2 VREF1 SCL2 SCL1 SDA2 SDA1 AVSS 1 R229 R230 C204 2 0.1u 10k 3 CCLK/SCL 4 CDTI/SDA R212 LRCK R208 LRCK/DINR-R1 51 open PORT200 MCLK BICK SDTO LRCK WCK 1 2 3 4 5 CDTI/SDA EXT AVSS AVSS PORT201 9 CSN CSN-10PIN 7 CCLK/SCLCCLK/SCL-10PIN 5 CDTI/SDACDTI/SDA-10PIN 3 1 0.1u PCA9306DP1 7 WCK-R1 4 C205 8 10 8 6 4 2 R226 470 CSN 3 TVDD 100k 10 9 8 7 6 10k CCLK/SCL R228 R207 0 CCLK/SCL 6 CSN SCL/CCLK SDA/CDTI 3 470 U202 6 5 U203 EN VREF2 GND VREF1 SCL2 SCL1 SDA2 SDA1 AVSS 1 R231 R232 C206 2 3 0.1u 10k 10k CSN CSN 4 uP-I/F 4 5 5 Title Size A3 - 36A B C Date: D AKD4497-SA Document Number Rev Digital Signal for AK4497 Wednesday, October 28, 2015 Sheet E 2 of 0 5 5 4 VCC-R1 R302 R303 C303 AVSS 1 AVSS Change: DIF2-0=HLH -> HLL 4 3 SW300 2 VCC-R1 R306 open R307 0 R315 0 37 INT1 38 AVDD 41 VSS3 42 RX0 43 NC 45 44 RX1 VSS4 RX3 75 H 0.1u 0.47u R301 VCC-R1 VCC-R1 10k R316 C305 0.1u D 10u C304 COAX 0 TEST1 1 C302 E OPT 48 2 3 4 5 J300 RX-COAX open 39 R300 51 + AVSS 46 E + IPS0/RX4 INT0 NC OCKS0/CSN/CAD0 DIF0/RX5 OCKS1/CCLK/SCL 36 R314 4 TEST2 CM1/CDTI/SDA XTL0 MCKO2 XTL1 BICK OCKS1-R 33 R313 0 R312 0 VCC-R1 32 AVSS 31 PDN-0 30 29 AVSS C 28 27 AVSS 26 BICK-DIR 25 SDTO-DIR BICK-DIR LRCK SDTO-DIR 24 MCKO1 23 VSS2 DVDD 22 14 13 SDTO 21 VIN/GP0 VOUT/GP7 DAUX TVDD 12 P/SN 20 11 XTO UOUT/GP6 10 IPS1/IIC 19 9 AVSS XTI COUT/GP5 8 AVSS PDN DIF2/RX7 18 7 BOUT/GP4 open 17 0 R311 U300 VSS1 TX1/GP3 47k 47k R305 R304 R310 CM0/CDTO/CAD1 16 6 OCKS0-R OCKS1-R DIF1/RX6 TX0/GP2 5 15 0 NC/GP1 open R309 OCKS0-R 34 1 2 OCKS1 OCKS0 R308 0 35 D 3 L C 1 C301 10u R 0.1u 2 1 GND OUT 2 47uH 40 C300 RX2 3 VCC 2 VCOM 1 L300 RX-OPT 47 PORT300 3 LRCK-DIR B C306 C308 MCLK-DIR MCLK-DIR + 0.1u + 0.1u B LRCK-DIR C307 10u C309 10u VCC-R1 AVSS A A Title AKD4497-SA Size A3 - 375 4 3 2 Document Number Rev 0 <AK4118A-DIR> Date: Wednesday, October 28, 2015 Sheet 1 3 of 5 A B C D E C401 27n 8 R800 22 R403 20k + 2 1 - OPA1612 1 4 C800 56n C428 1n R424 620 4 C400 10u R429 620 U400A 3 3 C407 27n C406 10u R409 20k 2 6 7 - OPA1612 6 OPA1611 R428 620 R430 short J402 LOUT R431 open 7 100 2 C430 1n AVSS AVSS AVSS AVSS 1 1 + 100 U400B 5 R811 R801 22 8 R407 22 3 AVSS R425 620 C431 10u U402 2 MVDD 4 AOUTLN + R406 short 2 R810 Lch 3 + J400 R404 220 2 - R405 100 AVSS + + R401 22 AOUTLP C801 56n + C432 0.1u R411 100 AVSS R410 220 C433 C434 100u 0.1u + R400 short 1 AVSS C435 100u R460 J404 Short -15V AVSS AVSS C444 470u 3 + AVSS 3 C413 27n AVSS MVDD 8 7 6 - OPA1612 AVSS R421 20k C803 56n R435 620 U401A 3 + 1 2 - OPA1612 AVSS 5 2 3 1 100 R813 8 R803 22 4 2 R422 220 R438 620 AVSS 4 + C418 10u AVSS 2 C439 10u U403 6 OPA1611 7 C419 27n 3 R434 620 4 3 100 Rch R812 4 C436 1n J401 R416 220 AOUTRN C443 100u AVSS R439 620 R417 100 R419 22 C441 C442 100u 0.1u C438 1n R440 short + C802 56n AVSS R418 short + C440 0.1u 1 R415 20k + 4 C412 10u U401B 5 + + R802 22 - R413 22 + R412 short AOUTRP J403 ROUT R441 open AVSS AVSS AVSS R423 100 5 AVSS Title AVSS Size A3 - 38A B C Date: D AKD4497-SA Document Number External LPF Thursday, October 29, 2015 Rev 0 Sheet E 4 of 5 A B C Q500 BCP 56 MVDD R500 270 + + 200 C501 0.1u R503 3.9k C503 0.1u + (short) R506 C505 47u (short) (short) R531 U500 R502 510 2 3 + + C500 470u C502 1u D501 4 (short) NC NC -IN V+ +IN V- OUT NC AVSS AVSS VREFHR 5V J500 REG(+15V) VREFLL VREFLR AVSS AVSS AVSS MVDD + AVSS 7 1 J501 8 C530 470u 6 Q501 SB1188 CSC 5 AD817A/AD AVSS AVSS R550 AVSS + AVSS VREFHL R530 D500 1 E R505 R501 1 D C504 47u AVSS DVSS-LAYER4 (dummy short) R551 R504 3.6k DVSS-LAYER1 (dummy short) AVSS 2 2 Q502 BCP 56 MVDD R507 R512 R508 + 200 C507 0.1u C509 0.1u + C511 47u (short) R513 (short) VDDL VDDR 5V D502 U501 1 R509 510 2 3 3 + + C506 470u C508 1u D503 4 T500 NC NC -IN V+ +IN OUT V- NC 8 7 + 6 Q503 SB1188 CSC 5 AD817A/AD + AVSS AVSS AVSS AVSS AVSS C510 47u AVSS R511 3.6k 270 + + 200 C513 0.1u R517 3.9k C515 0.1u 1.8V OUT C518 C519 47u 0.1u C520 0.1u AVSS + C521 47u R521 (short) AVDD R523 (short) DVDD R524 (short) TVDD 3 AVSS AVSS R519 R515 4 LT1963AEST-1.8 IN AVSS Q504 BCP 56 MVDD R514 3.3V VCC-R GND 270 + R510 3.9k + C517 47u (short) R520 (short) VCC-R VCC-R1 VCC-R -> Regulator(3.3V->1.8V) 3.3V VCC-R1 -> AK4118A, DigitalSignal 4 D504 U502 1 R516 510 2 3 + + C512 470u C514 0.01u D505 4 NC NC -IN V+ +IN OUT V- NC 8 7 6 Q505 SB1188 CSC 5 AD817A/AD + C516 47u R518 10k 5 5 AVSS AVSS AVSS AVSS AVSS AVSS AVSS Title Size A3 - 39A B C Date: D AKD4497-SA Document Number Rev Puwer Supply Unit Thursday, October 29, 2015 Sheet E 0 5 of 5