[AKD4497-SA]
< KM122100> 2015/10
1. General Description
The AKD4497-SA is an evaluation board for the AK4497 (Premium 32-bit 2ch DAC) that supports
Network-Audios, USB-DAC, Car-Audio Systems. It integrates differential output low pass filters, allowing
quick evaluation with digital audio interface.
■Ordering Guide
AKD4497-SA -- Evaluation Board for the AK4497
(A USB I/F board for IBM-AT compatible computers and control software are
included in this package.)
2. Function
10-pin Header for Serial Control
Low Pass Filters (LPF) for Pre-amplifier Outputs
Digital Audio Interface (AK4118A)
COAX In
AK4
497
2nd Order LPF
Rch
Lch
DIR
Opt In
AK4118A
Figure 1. AKD4497-SA Block Diagram (Note 1)
Note 1. Circuit schematics are attached at the end of this document.
AK4497 Evaluation Board Rev.0
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3. Board Appearance
■Appearance Diagram
J500
SW100
SW200
U1
J400
J300
PORT200
J403
J402
J401
J501
J404
SW300
PORT201
PORT300
Filter Block1-1
Filter Block2-1
Filter Block1-2
Filter Block2-2
Regulator
Block4
Regulator
Block3
Regulator
Block1
Regulator
Block2
U300
Bottom Side
Figure 2. AKD4497-SA Outline View
■Description
(1) Connectors for Power Supply and GND ( J500 / +15V, J404 / -15V, J501 / GND )
Connectors for power supply and the ground
Refer to the “Power Supply Connections” for details.
(2) SPDIF Input Connectors (J300 / BNC Connector, PORT300 / Optical Connector)
Input a SPDIF signal to the AK4118A.
Set the R303 resistance to short when using the J300 (BNC Connector) jack.
Set the R302 resistance to short when using the PORT300 (Optical Connector).
(3) Analog Differential Output Terminals (J400 / J401, XLR Connector)
Differential Analog Output Connector
(4) Analog Output Terminals (J402 / J403, BNC Connector)
Single-ended Analog Output Connector
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(5) EXT PORT (PORT200)
10-pin Header for External Interfacing
External digital audio devices are interfaced to this port.
Set the R202, R204, R206 and R208 resistances to short when using the PORT200 (EXT).
Pin I/O Function pin I/O Function
1 I MCLK 10 P GND
2 I BICK 9 P GND
3 I SDTO 8 P GND
4 I LRCK 7 P GND
5 I WCK 6 P GND
Table 1. PORT200 (EXT) Pin Assignments
(6) AK4118A (U300)
The AK4118A is a digital audio transceiver.
It is used when evaluating sound quality of the AK4497 by SPDIF signals.
(7) µP-IF PORT (PORT201)
10-pin Header for the USB I/F board
Connect the USB I/F board for IBM-AT compatible computers to this port for a connection to a USB port of
a PC. Refer to the “Serial Control Mode” for details
(8) Dip Switches (SW100 / SW300)
Setting Switches for the AK4497 and the AK4118A.
Upside is “H” (ON) and Downside is “L” (OFF).
Refer to “■Resistance and DIP Switch Settings” for details.
(9) SW200 ( Toggle switch )
Toggle type-switch PDN for AK4497 and the AK4118A.
“H” : PDN = High
“L” : PDN = Low
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4. Operation Sequence
Operation sequence
1). Power Supply Connections
2). Evaluation Mode
3). ■Resistance and DIP Switch Settings
4). Power-up
■Power Supply Connections
Name Color Voltage Content Note Default
Setting
J500
(REG(+15V))
Red +10 to +15V MVDD (AK4497),
Op-Amp
This jack is always needed. +15V
J404
(REG(-15V))
Blue -10 to -15V Op-Amp This jack is always needed. -15V
J501
(AVSS)
Black 0V Ground This jack is always needed. 0V
Table 2. Power Supply Connections
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■Evaluation Mode
(1) Evaluation with a DIR (COAX) < Default >
The J300 (COAX) jack is used in this mode. The DIR (AK4118A) generates MCLK, BICK, LRCK and
SDATA from the input data of the J300 (COAX) connector.
Set the R303 resistance to short, and set the R201 (MCLK), R203 (BICK), R207 (LRCK) and R205
(SDTO) resistances to short.
Resistance Settings with DIR:
COAX / OPT : R303 = short (COAX)
MCLK : R201 = short (DIR)
BICK : R203 = short (DIR)
LRCK : R207 = short (DIR)
SDTO : R205 = short (DIR)
(2) Evaluation with a DIR (OPTICAL)
The PORT300 (OPTICAL) is used in this mode. The DIR (AK4118A) generates MCLK, BICK, LRCK
and SDATA from the input data of the PORT300 (OPTICAL) connector.
Set the R302 resistance to shot, and set the R201 (MCLK), R203 (BICK), R207 (LRCK) and R205
(SDTO) jumper pins to “DIR”.
Resistance Settings with DIR:
COAX / OPT : R302 = short (OPT)
MCLK : R201 = short (DIR)
BICK : R203 = short (DIR)
LRCK : R207 = short (DIR)
SDTO : R205 = short (DIR)
(3) In the case that all interface clocks including the master clock are input externally. (PORT200)
Input all interface clocks including the master clock to the PORT200 (DSP).
Set R202 (MCLK), R204 (BICK), R208 (LRCK) and R206 (SDTO) resistances to short.
Resistance Settings with External Clocks:
COAX / OPT : R303 = short (COAX) <default>
MCLK : R202 = short (EXT)
BICK : R204 = short (EXT)
LRCK : R208 = short (EXT)
SDTO : R206 = short (EXT)
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■Resistance and DIP Switch Settings
(1) Resistance Settings
[R201 / R202 (MCLK)]: MCLK pin input select
R201 short: MCLK signal is supplied from the DIR (AK4118A). < Default >
R202 short: MCLK signal is supplied from the PORT200.
[R203 / R204 (BICK)]: BICK pin input select
R203 short: BICK signal is supplied from the DIR (AK4118A). < Default >
R204 short: BICK signal is supplied from the PORT200.
[R205 / R206 (SDTO)]: SDATA pin input select
R205 short: SDATA signal is supplied from the DIR (AK4118A). < Default >
R206 short: SDATA signal is supplied from the PORT200.
[R207 / R208 (LRCK)]: LRCK pin input select
R207 short: LRCK signal is supplied from the DIR (AK4118A). < Default >
R208 short: LRCK signal is supplied from the PORT200.
[R303 / R302 (COAX / OPT)]: SPDIF signal for AK4118A
R303 short: SPDIF signal is supplied from the J300 (COAX) connector. < Default >
R302 short: SPDIF signal is supplied from the PORT300.
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(2) DIP Switch Setting
Upside is ON (“H”), and Downside is OFF (“L”).
[SW300]: Setting of the AK4118A
No. Name ON (“H”) OFF (“L”) Default
1 OCKS1 Master Clock setting for AK4118A
Refer to Table 5.
L
2 OCKS0 L
Table 3. SW300 Setting
[SW100]: Setting of the AK4497
No. Name ON (“H”) OFF (“L”) Default
1 SSLOW Digital Filter Setting Refer to Table 6.
( In Pararell Control Mode)
L
2 SD H
3 SLOW L
4HLOAD
/I2C
Heavy Load Mode Normal Mode
L
( In Pararell Control Mode)
I2C-Bus
Control Mode
3-wire
Serial Control Mode
5 PSN PSN pin= “H”
(Pararell Control Mode)
PSN pin= “L”
Serial Control Mode) L
6ACKS
/CAD1
Auto Setting Mode Manual Setting Mode
L( In Pararell Control Mode)
CAD1 pin= “H” CAD1 pin= “L”
Table 4. SW100 Setting
Mode OCKS1 OCKS0 MCKO1 fs (max)
0 L L 256fs 96 kHz < Default >
1 L H 256fs 96 kHz
2 H L 512fs 48 kHz
3 H H 128fs 192 kHz
Table 5. Master Clock Setting
SSLOW SD SLOW Mode
L L L Sharp roll-off filter
L L H Slow roll-off filter
L H L Short delay sharp roll-off filter < Default >
L H H Short delay slow roll-off filter
H L L Super Slow roll-off filter
H L H Reserved
H H L Low dispersion Shot Delay filter /
Programable FIR filter
H H H
Table 6. Digital Filter Setting
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■Power-up
Upside is ON (“H”), and Downside is OFF (“L”).
[SW200] (PDN): DAC / DIR Reset control. It must be set to “H” during operation.
After power-up, the AKD4497-SA must be reset once.
To reset the AKD4497-SA, set the SW200 toggle switch to “L” and power down the
AK4497 and the AK4118A. Then, release the power-down by setting back the SW200 to
“H”.
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■Serial Control Mode (PSN pin = “L”)
When using this evaluation board in serial control mode, settings of the CAD1 pin and the CAD2 pin on the
board must match the Chip Address settings of the control software.
(1) 3-wire Serial Control Mode: (I2C pin= “L”)
(2) I2C Bus Control Mode: (I2C pin= “H”)
The AKD4497-SA should be connected to a PC (IBM-AT compatible) via a USB control box
(AKDUSBIF-B) included in this package. The USB control box is connected to a PC with a USB cable and
the AKD4497-SA with a 10-pin flat cable. (Note 2,Note 3)
Note 2. The AKD4497-SA accepts only one AKDUSBIF-B at one time. It does not operate if two or more
AKDUSBIF-Bs are connected.
Note 3. Connect the 10pin Flat Cable as the red line of the cable is connected to the 1 pin of the 10pin Header
of the board.
PC
USB Cable
-
B
USB
Connector
Evaluation Board
AKDXXXX
-YY
10pin
Connector
Device
AKXXXX
10pin Flat Cable
Set Red line to No.1 pin side.
Figure 3. AKDUSBIF-B Connection
Figure 4. AKDUSBIF-B
AKDUSBIF
-
B
Evaluation Board
PC
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5. Control Software Manual
■Evaluation Board and Control Software Manual
1.Set up the evaluation board as needed, according to the previous terms.
2.Connect the evaluation board to a PC with USB cable.
3.USB control is recognized as HID (Human Interface Device) on PC. When it is not recognized properly, please
reconnect the evaluation board to PC.
4.Insert the CD-ROM labeled “AKD4497-SA Evaluation Kit” into the CD-ROM drive.
5.Access the CD-ROM drive and double-click the icon “AKD4497-SA.exe” to open the control program.
6.Begin evaluation by following the procedure below.
[Supported OS]
Windows XP / Vista / 7 (32bit) (XP compatible mode is recommended for Vista / 7)
64bit OS is not supported.
Figure 5. Control Program Window
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■Operation Overview
Register map is controlled by this control software.
Frequently used buttons, such as the register initializing button “Write Default”, are located outside of the
switching tab window. Refer to the “■Dialog Box” section for details of each dialog box setting.
1.[Port Reset]: Reset connection to PC
Click this button after the control software starts up and the evaluation board is connected to
the PC via USB cable.
2.[Write Default]: Register Initialization
Use this button to initialize the registers when the device is reset by a hardware reset.
3.[All Write]: Execute write command for all registers displayed.
4.[All Read]: Execute read command for all registers displayed. (Note 2)
5.[Save]: Save current register settings to a file.
6.[Load]: Execute data write from a saved file.
7.[All Reg Write]: [All Reg Write] dialog box pops up.
8.[Data R/W]: [Data R/W] dialog box pops up.
9.[Sequence]: [Sequence] dialog box pops up.
10.[Sequence(File)]: [Sequence(File)] dialog box pops up.
Note 2. The [All Read] button is only valid when the interface mode for register control is in I2C bus control
mode.
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■Tab Functions
1. [REG] Tab: Register Map
This tab is for register read and write.
Each bit on the register map is a push-button switch.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray)
Grayed out registers are Read-Only registers. They cannot be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 6. REG Window
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[Write] button: Data Write Dialog
Select the [Write] button located on the right of the each corresponding address when changing two or more bits
on the same address simultaneously.
Click the [Write] button for the register pop-up dialog box shown below.
When the checkbox next to the register is checked, the data will become “1”. When the checkbox is not
checked, the data will become “0”. Click [OK] to write the set values to the registers, or click [Cancel] to cancel
this setting.
Figure 7. Register Set Window
[Read] button: Data Read (Only in I2C-bus Control Mode)
Click the [Read] button located on the right of the each corresponding address to execute a register read.
The current register value will be displayed in the register window as well as in the upper right hand DEBUG
window.
Button Down indicates “1” and the bit name is shown in red (when read only the bit name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read only the bit name is shown in gray)
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■Dialog Box
1. [All Reg Write]: All Register Write dialog box
Click [All Reg Write] button in the main window to open register setting file window shown below.
Register setting files saved by [SAVE] button may be applied.
Figure 8. [All Reg Write] Window
[Open (left)]: Select a register setting file (*.akr).
[Write]: Execute register write with selected setting file.
[Write All]: Execute register write with all selected setting files.
Selected files are executed in descending order.
[Help]: Open help window.
[Save]: Save register setting file assignment. File name is “*.mar”.
[Open (right)]: Open saved register setting file assignment “*. mar”.
[Close]: Close dialog box and finish process.
~ Operating Suggestions ~
1. Files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
2. When register settings are changed by [Save] button in the main window, re-read the file to reflect new
register settings.
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2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data is written to the specified address.
Figure 9. [Data R/W] Window
[Address] Box: Input data write address in hexadecimal numbers.
[Data] Box: Input write data in hexadecimal numbers.
[Mask] Box: Input mask data in hexadecimal numbers.
This value “ANDed” with the write data becomes the input data.
[Write]: Write data generated from Data and Mask value is written to the address specified in “Address” box.
(Note 3)
[Read]: Read data from the address specified in “Address” box. (Note 4)
[Close]: Close dialog box and finish process.
Data write will not be executed unless [Write] is clicked.
Note 3. The register map will be updated after executing the [Write] command.
Note 4. The [Read] button is only valid when the interface mode for register control is in I2C bus control mode.
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3. [Sequence]: Sequence Dialog Box
Click the [Sequence] button in the main window for Sequence dialog box.
Register sequence may be set and executed.
Figure 10. [Sequence] Window
~ Sequence Setting ~
Set register sequence according to the following process.
1. Select a command
Use [Select] pull-down box to choose commands.
Corresponding input boxes will be valid.
<Combo Box>
• No_use: Not using this address
• Register: Register write
• Reg(Mask): Register write (Masked)
• Interval: Take an interval
• Stop: Pause the sequence
• End: End the sequence
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2. Input Sequence
[Address]: Data Address
[Data]: Write Data
[Mask]: Mask
This value “ANDed” with the write data becomes the input data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[Interval]: Interval Time
Valid boxes for each process command are shown below.
・No_use : None
・Register : [Address], [Data], [Interval]
・Reg(Mask) : [Address], [Data], [Mask], [Interval]
・Interval : [Interval]
・Stop : None
・End : None
~ Control Buttons ~
Functions of Control Buttons are shown below.
[Start] button : Execute the sequence.
[Help] button : Open a help window.
[Save] button : Save sequence settings as a file. The file name is “*.aks”.
[Open] button : Open a sequence setting file “*.aks”.
[Close] button : Close the dialog box and finishes the process.
Stop Sequence
When “Stop” command is selected in the sequence, the process is paused at this step. It is resumed by
clicking the [Start] button. The process starts from the step shown in [Start Step] box. This step number
returns to “1” when the sequence is executed until the end. Input arbitrary step number to the [Start Step]
box to start the process from the middle of sequence.
The process sequence can be restarted from the beginning by writing “1” to the [Start Step] box and
click the [Start] button during the process.
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4. [Sequence(File)]: Sequence(File) Dialog
Click the [Sequence(File)] button to open sequence setting file dialog box shown below.
Files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 11. [Sequence (File)] Window
[Open (left)] button: Select a sequence setting file (*.aks)
[Start ] button: Execute the sequence by the setting of selected file.
[Start All] button: Execute sequence with all selected setting files.
Selected files are executed in descending order.
[Help] button: Open help window.
[Save] button: Save register setting file assignment. File name is “*.mas”.
[Open (right)] button : Open saved sequence setting file assignment “*. mas”.
[Close] button: Close dialog box and finish process.
~ Operating Suggestions ~
1. Files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be
stored in the same folder.
2. When “Stop” command is selected in the sequence, the process is paused at this step and a message shown
below pops up. The sequence is resumed by clicking “OK” button.
Figure 12. Sequence Pause Window
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6. Measurement Results
[Measurement condition]
Measurement unit : Audio Precision APX 555 Audio Analyzer
MCLK : 256fs (44.1 kHz), 256fs (96 kHz), 128fs (192 kHz)
BICK : 64fs
fs : 44.1kHz, 96kHz, 192kHz
Bit : 24bit
Power Supply : AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V
Pass : DIR →AK4497 →Cannon Connector
Interface : Internal DIR (44.1 kHz, 96 kHz, 192 kHz)
Temperature : Room Temperature
Operational Amplifiers : OPA1611, OPA1612
Control Soft Register : HLOAD=”1”, SC2=”1”
fs=44.1kHz
Parameter Input signal Measurement filter Results
Lch / Rch
S/(N+D) 1kHz, 0dB 20kHz LPF 116.9 dB / 116.6 dB
DR 1kHz, -60dB 124.2 dB / 124.1 dB
A-weighted 126.5 dB / 126.3 dB
S/N “0” data 20kHz LPF 124.1 dB / 124.1 dB
A-weighted 126.5 dB / 126.4 dB
fs=96kHz
Parameter Input signal Measurement filter Results
Lch / Rch
S/(N+D) 1kHz, 0dB 40kHz LPF 114.1 dB / 115.1 dB
DR 1kHz, -60dB 121.5 dB / 121.5 dB
S/N “0” data 40kHz LPF 121.6 dB / 121.5 dB
fs=192kHz
Parameter Input signal Measurement filter Results
Lch / Rch
S/(N+D) 1kHz, 0dB 40kHz LPF 115.3 dB / 114.6 dB
DR 1kHz, -60dB 121.5 dB / 121.3 dB
S/N “0” data 40kHz LPF 121.5 dB / 121.6 dB
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■Capacitance between the VREFH pin and the VREFL pin
Distortion (THD+N) can be improved by increasing the capacitance of a capacitor between the VREFH pin and
the VREFL pin. Applicable capacitors are C108 and C111 in the circuit schematic.
Figure 13. THD+N vs. Input Frequency Comparison by Capacitance
C=470
uF
C=10uF
C=100uF
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[Plots]
fs = 44.1 kHz
AK4497 THD+N vs. Input Level
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz
Figure 14. THD+N vs. Input Level
AK4497 THD+N vs. Input Frequency
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz
Figure 15. THD+N vs. Input Frequency
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fs = 44.1 kHz
AK4497 Linearity
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz
Figure 16. Linearity
AK4497 Frequency Response
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz
Figure 17. Frequency Response
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fs = 44.1 kHz
AK4497 Crosstalk
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz
Figure 18. Crosstalk
AK4497 FFT (0dBFS Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz
Figure 19. FFT (0dBFS Input)
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fs = 44.1 kHz
AK4497 FFT ( -60dBFS Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz
Figure 20. FFT (-60dBFS Input)
AK4497 FFT ( No Signal Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz
Figure 21. FFT (No Signal Input)
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fs = 96 kHz
AK4497 THD+N vs. Input Level
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
Figure 22. THD+N vs. Input Level
AK4497 THD+N vs. Input Frequency
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
Figure 23. THD+N vs. Input Frequency
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fs = 96 kHz
AK4497 Linearity
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
Figure 24. Linearity
AK4497 Frequency Response
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
Figure 25. Frequency Response
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fs = 96 kHz
AK4497 Crosstalk
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
Figure 26. Crosstalk
AK4497 FFT (0dBFS Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
Figure 27. FFT (0dBFS Input)
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fs = 96 kHz
AK4497 FFT (-60dBFS Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
Figure 28. FFT (-60dBFS Input)
AK4497 FFT (No Signal Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
Figure 29. FFT (No Signal Input)
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fs = 192 kHz
AK4497 THD+N vs. Input Level
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
Figure 30. THD+N vs. Input Level
AK4497 THD+N vs. Input Frequency
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
Figure 31. THD+N vs. Input Frequency
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fs = 192 kHz
AK4497 Lnearity
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
Figure 32. Linearity
AK4497 Frequency Response
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
Figure 33. Frequency Response
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fs = 192 kHz
AK4497 Crosstalk
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
Figure 34. Crosstalk
AK4497 FFT (0dBFS Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
Figure 35. FFT (0dBFS Input)
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[AKD4497-SA]
< KM122100> 2015/10
fs = 192 kHz
AK4497 FFT (-60dBFS Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
Figure 36. FFT (-60dBFS Input)
AK4497 FFT (No Signal Input)
AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
Figure 37. FFT (No Signal Input)
- 32-
[AKD4497-SA]
< KM122100> 2015/10
7. Revision History
Date
(y/m/d)
Manual
Revision
Board
Revision
Reason Page Contents
15/10/30 KM122100 0 First
Edition
- -
- 33-
[AKD4497-SA]
< KM122100> 2015/10
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this
document. You are fully responsible for use of such information contained in this document in your product
design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR
THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT
DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices
related to electric power, and equipment used in finance-related fields. Do not use Product for the above use
unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
- 34-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CSN
SMUTE-L
CCLK/SCL
SD
CDTI/SDA
SLOW
SSLOW
SSLOW
SD
SLOW
HLOAD/I2C-S
PSN
ACKS/CAD1
VSSL VSSR
WCK
H
L
SMUTE-H
*Default Setting
DIF0/DZFL=L
DIF1/DZFR=H
DIF2/CAD0=L
DEM0/DSDL=H
*Default Setting
GAIN/DSDR=L
TDM0/DCLK=L
TDM1=L
DCHAIN=L
INVR=L
TESTE=L
LDOE=L
SDATA1/DSDL
PDN
HLOAD/I2C-S
LRCK/DINR
BICK/BCK
PSN-S
SSLOW-S
SD-S
SLOW-S
HLOAD/I2C-S
PSN-S
ACKS/CAD1-S
SD-S
SLOW-S
LDOE
ACKS/CAD1-S
SSLOW-S
AVSS AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
VREFHR
VREFLR
VREFHL
VREFLL
AVDD
MCLK
AOUTLP
AOUTLN
VDDL VDDR
AOUTRN
AOUTRP
CDTI/SDA
CCLK/SCL
CSN
LRCK/DINR
SDATA1/DSDL
BICK/BCK
PDN-0
DVDD
TVDD
WCK
TVDD
TVDD
TVDD
TVDD
Title
Size Document Number Rev
Date: Sheet of
AK4497 64LQFP 0
AKD4497-SA
A3
1 5Wednesday, October 28, 2015
Title
Size Document Number Rev
Date: Sheet of
AK4497 64LQFP 0
AKD4497-SA
A3
1 5Wednesday, October 28, 2015
Title
Size Document Number Rev
Date: Sheet of
AK4497 64LQFP 0
AKD4497-SA
A3
1 5Wednesday, October 28, 2015
R114 open
C115
0.1u
R125 0
+
C111
470u(A)
R128 open
R150 10k
C113
0.1u
+
C116
1u(A)
R105 0
U1
AK4497 Plastic
LDOE
1
PDN
2
BICK/BCK
3
SDATA/DINL
4
LRCK/DINR
5
SSLOW/WCK
6
TDMO
7
SMUTE/CSN
8
SD/CCLK/SCL
9
SLOW/CDTI/SDA
10
DIF0/DZFL
11
DIF1/DZFR
12
DIF2/CAD0
13
PSN
14
HLOAD/I2C
15
VSSR 38
VSSR 39
GAIN/DSDR 17
ACKS/CAD1 18
TDM0/DCLK 19
TDM1 20
INVR 22
TESTE 23
VREFHR 24
VREFHR 25
VREFHR 26
VREFLR 27
VREFLR 28
VREFLR 29
VCMR 30
AOUTRN 31
AOUTRN 32
AOUTRP 33
AOUTRP 34
VDDR 37
VDDR 36
VDDR 35
DEM0/DSDL
16
DCHAIN 21
VSSR 40
VSSL 41
VSSL 42
VSSL 43
VDDL 44
AOUTLP 48
AOUTLP 47
VDDL 46
VDDL 45
AOUTLN
49
AOUTLN
50
VCML
51
VREFLL
52
VREFLL
53
VREFLL
54
VREFHL
55
VREFHL
56
VREFHL
57
EXTR
58
AVDD
59
AVSS
60
MCLK
61
DVDD
62
DVSS
63
TVDD
64
R147 100
+
C104
10u(A)
R116 open
R131 open
R141 open
R113 0
+
C108
470u(A)
+
C100 10u(A)
R101 (short)C117 100p
R130 0
R120 0
R143 100
C106
0.1u
R123 open
R108 100
R140 0
R118 0
R126 0
R111 100
+
C114
10u(A)
R151 10k
C107
0.1u
R121 open
R152 10k
R146 100
R119 open
R133 open
R110 100
+
C105
10u(A)
R145 100
R132 0
R153 10k
R102 (short)
C102 0.1u
R112 100
R148 10k
R137 open
C109
0.1u
R142 100
SW100
1
2
3
4
5
6
12
11
10
9
8
7
R107 0
R117 open
+
C101 10u(A)
R124 open
R135 open
R103 (short)
R109 51
R136 0
C103 0.1u
R144 100
R139 open
R134 0
R122 0
R100 33k
R129 0
C110
0.1u
R138 0
R149 10k
R115 0
R104 (short)
R127 open
R106 open
+
C112
10u(A)
- 35-
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
HL
LRCK
MCLK
SDTO
BICK
DIR
DIR
DIR
EXT
EXT
EXT
EXT
DIR
CDTI/SDA
CCLK/SCL
CSNCSN
CCLK/SCL
CDTI/SDA
CSN
SCL/CCLK
SDA/CDTI
VCC -> TVDD
VCC -> TVDD
MCLK
BICK
SDTO
LRCK
WCK
CDTI/SDA-10PIN
CCLK/SCL-10PIN
CSN-10PIN
CCLK/SCL
CDTI/SDA
CSN
AVSS AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
MCLK-DIR
BICK-DIR
SDTO-DIR
LRCK-DIR
VCC-R1
PDN-0-R1
MCLK-R1
BICK/BCK-R1
SDATA1/DSDL-R1
LRCK/DINR-R1
VCC-R1
TVDD
CCLK/SCL
CDTI/SDA
TVDD
CSN
MCLK
MCLK-R1
TVDD
BICK/BCK-R1
LRCK/DINR-R1
SDATA1/DSDL-R1
BICK/BCK
LRCK/DINR
SDATA1/DSDL
PDN-0-R1 PDN-0
WCK-R1
WCK-R1 WCK
Title
Size Document Number Rev
Date: Sheet of
Digital Signal for AK4497 0
AKD4497-SA
A3
2 5Wednesday, October 28, 2015
Title
Size Document Number Rev
Date: Sheet of
Digital Signal for AK4497 0
AKD4497-SA
A3
2 5Wednesday, October 28, 2015
Title
Size Document Number Rev
Date: Sheet of
Digital Signal for AK4497 0
AKD4497-SA
A3
2 5Wednesday, October 28, 2015
R206
open
R210
51
C200
0.1u
R211
51
R201
0
R228
100k
R207
0
R225
470
R202
open
U202PCA9306DP1
GND 1
VREF1 2
SCL1 3
SDA1 4
EN
8
VREF2
7
SCL2
6
SDA2
5
R215
51
R208
open
C201
0.1u
PORT201
uP-I/F
1
3
5
7
910
8
6
4
2
R224
470
C203
0.1u
PORT200
EXT
1
2
3
4
5 6
7
8
9
10
C206
0.1u
R212
51
R227
100k
R209
51
R219
0
R231
10k
D200
KA
C204
0.1u
U201
74VCX541
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
OE1
1
OE2
19
Y1 18
Y2 17
Y3 16
Y4 15
Y5 14
Y6 13
Y7 12
Y8 11
VCC 20
GND 10
R222
10k
R226
470
SW200
PDN
2
1
3
C202
0.1u
R221
10k
R229
10k
R203
0
R214
51
R216
51
U200
74HC14
GND
7
1A
1
3A
5
5A
11 5Y 10
3Y 6
1Y 2
2Y 4
4Y 8
6Y 12
6A
13
4A
9
2A
3
VCC
14
R230
10k
R200
10k
R204
open
R213
0
R223
10k
U203PCA9306DP1
GND 1
VREF1 2
SCL1 3
SDA1 4
EN
8
VREF2
7
SCL2
6
SDA2
5
R218
51
R232
10k
R205
0
R217
51
R220
10k
C205
0.1u
- 36-
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
OCKS0
H
L
OCKS1
OPT
COAX
Change:
DIF2-0=HLH -> HLL
BICK-DIR
MCLK-DIR
SDTO-DIR
LRCK-DIR
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
OCKS0-R
OCKS0-R
SDTO-DIR
OCKS1-R
LRCK-DIR
MCLK-DIR
OCKS1-R
PDN-0
BICK-DIR
VCC-R1
VCC-R1
VCC-R1
VCC-R1
VCC-R1
VCC-R1
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIR> 0
AKD4497-SA
A3
3 5
Wednesday, October 28, 2015
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIR> 0
AKD4497-SA
A3
3 5
Wednesday, October 28, 2015
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIR> 0
AKD4497-SA
A3
3 5
Wednesday, October 28, 2015
R301
75
R313
0
C306
0.1u
+
C309
10u
R303
0
C304 0.1u
R314
0
R306 open
+
C303 10u
L300
47uH
1 2
SW300
1
2
4
3
R305
47k
+
C301
10u
R307 0
PORT300
RX-OPT
OUT 1
VCC 3
GND 2
U300
IPS0/RX4
1
NC
2
DIF0/RX5
3
TEST2
4
DIF1/RX6
5
VSS1
6
DIF2/RX7
7
IPS1/IIC
8
P/SN
9
XTL0
10
XTL1
11
TVDD
13
NC/GP1
14
TX0/GP2
15
TX1/GP3
16
BOUT/GP4
17
COUT/GP5
18
UOUT/GP6
19
VOUT/GP7
20
DVDD
21
VSS2
22
MCKO1
23
BICK 26
MCKO2 27
DAUX 28
XTO 29
XTI 30
PDN 31
CM0/CDTO/CAD1 32
CM1/CDTI/SDA 33
OCKS1/CCLK/SCL 34
OCKS0/CSN/CAD0 35
INT0 36
AVDD 38
R39
VCOM 40
VSS3 41
RX0 42
NC 43
RX1 44
TEST1 45
RX2 46
VSS4 47
RX3 48
VIN/GP0
12
LRCK
24
SDTO 25
INT1 37
C302
0.1u
C308
0.1u
J300
RX-COAX
12
3
4
5
R315
0
R316
10k
R308 open
+
C307
10u
R309 0
R310 0
R311 open
C305
0.47u
R304
47k
C300
0.1u
R302
open
R300
51
R312
0
- 37-
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Lch
Rch
-15V
AVSS
AVSS AVSS
AVSS
AVSSAVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AOUTLP
AOUTLN
AOUTRP
AOUTRN
MVDD
MVDD
Title
Size Document Number Rev
Date: Sheet of
External LPF 0
AKD4497-SA
A3
4 5Thursday, October 29, 2015
Title
Size Document Number Rev
Date: Sheet of
External LPF 0
AKD4497-SA
A3
4 5Thursday, October 29, 2015
Title
Size Document Number Rev
Date: Sheet of
External LPF 0
AKD4497-SA
A3
4 5Thursday, October 29, 2015
R811
100
C407
27n
+
C431
10u
R434
620
R418
short
C419
27n
R810
100
+
C444
470u
R411
100
J402
LOUT
+
-
U400B
OPA1612
5
6
7
84
R410
220
+
-
U403
OPA1611
3
2
6
7 4
C803
56n
R417
100
R421
20k
R415
20k
R428
620
+
C433
100u
+
C441
100u
R404
220
R800
22
R425
620
R406
short
R405
100
R460
Short
J401
22
3
3
1
1
R412
short
R813
100
R440
short
+
-
U402
OPA1611
3
2
6
7 4
R439
620
R401
22
C401
27n
C428
1n
R802
22
C413
27n
R422
220
R416
220
+
C443
100u
C801
56n
J404
R441
open
R435
620
+
C406
10u
R419
22
C436
1n
C442
0.1u
R812
100
C434
0.1u
+
C418
10u
R403
20k
R429
620
C440
0.1u
R424
620
+
-
U401B
OPA1612
5
6
7
84
C430
1n
R413
22
+
C400
10u
R803
22
+
-
U401A
OPA1612
3
2
1
84
+
C435
100u
C800
56n
+
C439
10u
R431
open
+
C412
10u
R400
short
R438
620
C802
56n
R423
100
+
-
U400A
OPA1612
3
2
1
84
C432
0.1u
R430
short
R407
22
J400
22
3
3
1
1
R801
22
C438
1n
R409
20k
J403
ROUT
- 38-
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
AVSS
REG(+15V)
LT1963AEST-1.8
1.8V
5V
5V
3.3V
VCC-R1 -> AK4118A, DigitalSignal
VCC-R -> Regulator(3.3V->1.8V)
3.3V
AVSS
DVSS-LAYER1
DVSS-LAYER4
AVSSAVSS AVSSAVSSAVSSAVSS AVSS
AVSS
AVSS
AVSSAVSS AVSS
AVSS AVSSAVSSAVSS AVSSAVSSAVSS
AVSS AVSSAVSSAVSS AVSSAVSSAVSS
AVSS
VREFHL
MVDD
VCC-R
AVDD
DVDD
TVDD
VREFHR
MVDD
MVDD
VDDR
VDDL
MVDD
VCC-R1
VCC-R
VREFLR
VREFLL
Title
Size Document Number Rev
Date: Sheet of
Puwer Supply Unit 0
AKD4497-SA
A3
5 5Thursday, October 29, 2015
Title
Size Document Number Rev
Date: Sheet of
Puwer Supply Unit 0
AKD4497-SA
A3
5 5Thursday, October 29, 2015
Title
Size Document Number Rev
Date: Sheet of
Puwer Supply Unit 0
AKD4497-SA
A3
5 5Thursday, October 29, 2015
Q502
BCP 56
D505
R500
270
+
C509
0.1u
D503 R524 (short)
R531
(short)
R501
200
R506
(short)
C520
0.1u
J500
D500
Q501
SB1188 CSC
R515
200
R523 (short)
R509
510
+
C508
1u
+
C515
0.1u
T500
IN OUT
GND
+
C530
470u
J501
R517
3.9k
R514
270
R519
(short)
+
C516
47u
R503
3.9k
R505
(short)
+
C505
47u
R504
3.6k
R502
510
R518
10k
+
C517
47u
+
C507
0.1u
R512
(short)
+
C514
0.01u
R510
3.9k
R507
270
U500
AD817A/AD
NC
1
-IN
2
+IN
3
V-
4
NC 8
V+ 7
OUT 6
NC 5
+
C510
47u
+
C506
470u
+
C512
470u
U501
AD817A/AD
NC
1
-IN
2
+IN
3
V-
4
NC 8
V+ 7
OUT 6
NC 5
R530
(short)
R516
510
R511
3.6k
R521 (short)
+
C518
47u
D502
D501
+
C521
47u
C519
0.1u
+
C513
0.1u
+
C503
0.1u
R551
(dummy short)
Q503
SB1188 CSC
+
C501
0.1u
Q505
SB1188 CSC
U502
AD817A/AD
NC
1
-IN
2
+IN
3
V-
4
NC 8
V+ 7
OUT 6
NC 5
+
C500
470u
+
C502
1u
Q500
BCP 56
Q504
BCP 56
R513
(short)
+
C511
47u
+
C504
47u
D504
R508
200
R520
(short)
R550
(dummy short)
- 39-