January 2011 Doc ID 18211 Rev 2 1/29
29
ALTAIR04-900
Off-line all-primary-sensing switching regulator
Features
■Primary side constant voltage operations with
no optocoupler
■Adjustable and main-independent maximum
output current for safe operations during
overload/short circuit conditions
■900 V avalanche rugged internal power section
■Quasi-resonant valley switching operation
■Low standby consumption
■Overcurrent protection against transformer
saturation and secondary diode short circuit
■SO16 package
Applications
■SMPS for energy metering
■Auxiliary power supplies for 3-phases input
industrial systems
■AC-DC adapters
Description
ALTAIR04-900 is a high-voltage all-primary-
sensing switcher intended for operating directly
from the rectified mains with minimum external
parts. It combines a high-performance low-
voltage PWM controller chip and a 900 V
avalanche-rugged power section in the same
package.
SO16N
Figure 1. Block diagram
3.3 V
ZCD/F
B
IFF
STA RT ER
SOURC
E
TUR
N
-O
N
LOGI
C
+Vi
n
+V out
Is ta r
t
-u p
Internal supply bu
s
Vref
In te r n .
suppl
y
bu
s
DRAIN
BLANKING
TIME
LE
B
Vc
c
Ir e f
2.5
V
R
S
Q
COMP
-
+
-
+
+
-
S/H
DE M AG
LOGIC
GND
S
R
Q
IR EF
R
P ROT EC TION &
FE EDFORWAR D
LO G I C
Pr o
t
IFF
Vc
-
+
1 V
S
R
Q
UV L O
UV LO
Pr o
t
R
FF
SU PP L
Y
& UV LO
Rfb
Rz cd
Rsens
e
Rcomp
Ccom p
Cr e
f
3.3 V
ZCD /F
B
IFF
STA RT ERSTA RT ER
SOURC
E
TUR
N
-O
N
LOGI
C
+Vi
n
+V out
Is ta r
t
-u p
Internal supply bu
s
Vref
In te r n .
suppl
y
bu
s
DRAIN
BLANKING
TIME
BLANKING
TIME
LE
B
LE
B
Vc
c
Ir e f
2.5
V
R
S
Q
COMP
-
+
-
+
-
+
+
-
+
-
S/HS/H
DE M AG
LOGIC
DE M AG
LOGIC
GND
S
R
Q
S
R
Q
IR EF
R
P ROT EC TION &
FE EDFORWAR D
LO G I C
P ROT EC TION &
FE EDFORWAR D
LO G I C
Pr o
t
IFF
Vc
-
+
-
+
1 V
S
R
Q
S
R
Q
UV L O
UV LO
Pr o
t
R
FF
SU PP L
Y
& UV LO
Rfb
Rz cd
Rsens
e
Rcomp
Ccom p
Cr e
f
www.st.com
Contents ALTAIR04-900
2/29 Doc ID 18211 Rev 2
Contents
1 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Zero current detection and triggering block . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6 Voltage feedforward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.7 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 18
5.8 Soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.9 Hiccup mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.10 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Test board: evaluation data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Test board: main waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ALTAIR04-900 Device description
Doc ID 18211 Rev 2 3/29
1 Device description
The device combines two silicon in the same package: a low voltage PWM controller and a
900 V avalanche rugged power section.
The controller is a current-mode specifically designed for off-line quasi-resonant flyback
converters.
The device is capable of providing constant output voltage using all primary sensing
feedback. This eliminates the need for the optocoupler, the secondary voltage reference, as
well as the current sensor, still maintaining quite accurate regulation. Also, it is possible to
set the maximum deliverable output current, thus increasing the end-product's safety and
reliability during fault events.
Quasi-resonant operation is guaranteed by means of a transformer demagnetization
sensing input that turns on the power section. The same input serves also the output
voltage monitor, to perform CV regulation, and the input voltage monitor, to achieve mains-
independent maximum deliverable output current (line voltage feedforward).
The maximum switching frequency is top-limited below 166 kHz, so that at medium-light
load a special function automatically lowers the operating frequency still maintaining the
valley switching operation. At very light load, the device enters a controlled burst-mode
operation that, along with the built-in high-voltage start-up circuit and the low operating
current, helps minimize the standby power.
Although an auxiliary winding is required in the transformer to correctly perform CV/CC
regulation, the chip is able to power itself directly from the rectified mains. This is useful
especially during CC regulation, where the flyback voltage generated by the winding drops
below UVLO threshold.
However, if ultra-low no-load input consumption is required to comply with the most stringent
energy-saving recommendations, then the device needs to be powered via the auxiliary
winding.
In addition to these functions that optimize power handling under different operating
conditions, the device offers protection features that considerably increase end-product's
safety and reliability: auxiliary winding disconnection - or brownout - detection and shorted
secondary rectifier - or transformer's saturation - detection.
All of them are auto restart mode.
Pin connection ALTAIR04-900
4/29 Doc ID 18211 Rev 2
2 Pin connection
Figure 2. Pin connection (top view)
Note: The copper area for heat dissipation has to be designed under the drain pins
N.A.
N.A.
SOURCE DRAIN
SOURCE
GND
IREF
ZCD/FB
COMP
Vcc
DRAIN
DRAIN
DRAIN
N.A.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N.C.
N.A.
N.A.
SOURCE DRAIN
SOURCE
GND
IREF
ZCD/FB
COMP
Vcc
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
N.A.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N.C.
N.A.
Table 1. Pin functions
N. Name Function
1, 2 SOURCE
Power section source and input to the PWM comparator. The current flowing in the MOSFET
is sensed through a resistor connected between the pin and GND. The resulting voltage is
compared with an internal reference (0.75V max.) to determine MOSFET’s turn-off. The pin
is equipped with 250 ns blanking time after the gate-drive output goes high for improved
noise immunity. If a second comparison level located at 1V is exceeded the IC is stopped and
restarted after Vcc has dropped below 5V.
3Vcc
Supply voltage of the device. An electrolytic capacitor, connected between this pin and
ground, is initially charged by the internal high-voltage start-up generator; when the device is
running the same generator keeps it charged in case the voltage supplied by the auxiliary
winding is not sufficient. This feature is disabled in case a protection is tripped. Sometimes a
small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for
the signal part of the IC.
4GND
Ground. Current return for both the signal part of the IC and the gate drive. All of the ground
connections of the bias components should be tied to a trace going to this pin and kept
separate from any pulsed current return.
5IREF
CC regulation loop reference voltage. An external capacitor has to be connected between
this pin and GND. An internal circuit develops a voltage on this capacitor that is used as the
reference for the MOSFET’s peak drain current during CC regulation. The voltage is
automatically adjusted to keep the average output current constant.
ALTAIR04-900 Pin connection
Doc ID 18211 Rev 2 5/29
6 ZCD/FB
Transformer’s demagnetization sensing for quasi-resonant operation. Input/output voltage
monitor. A negative-going edge triggers MOSFET’s turn-on. The current sourced by the pin
during ON-time is monitored to get an image of the input voltage to the converter, in order to
compensate the internal delay of the current sensing circuit and achieve a CC regulation
independent of the mains voltage. If this current does not exceed 50µA, either a floating pin
or an abnormally low input voltage is assumed, the device is stopped and restarted after Vcc
has dropped below 5V. Still, the pin voltage is sampled-and-held right at the end of
transformer’s demagnetization to get an accurate image of the output voltage to be fed to the
inverting input of the internal, transconductance-type, error amplifier, whose non-inverting
input is referenced to 2.5V. Please note that the maximum IZCD/FB sunk/sourced current has
to not exceed ±2 mA (AMR) in all the Vin range conditions. No capacitor is allowed between
the pin and the auxiliary transformer.
7COMP
Output of the internal transconductance error amplifier. The compensation network is placed
between this pin and GND to achieve stability and good dynamic performance of the voltage
control loop.
8-11 N.A Not available. These pins must be left not connected
12 N.C Not internally connected. Provision for clearance on the PCB to meet safety requirements.
13 to 16 DRAIN
Drain connection of the internal power section. The internal high-voltage start-up generator
sinks current from this pin as well. Pins connected to the internal metal frame to facilitate
heat dissipation.
Table 1. Pin functions (continued)
N. Name Function
Maximum ratings ALTAIR04-900
6/29 Doc ID 18211 Rev 2
3 Maximum ratings
3.1 Absolute maximum ratings
3.2 Thermal data
Table 2. Absolute maximum ratings
Symbol Pin Parameter Value Unit
VDS 1,2, 13-16 Drain-to-source (ground) voltage -1 to 900 V
ID1,2, 13-16 Drain current 0.7 A
Eav 1,2, 13-16 Single pulse avalanche energy
(Tj = 25°C, ID = 0.7A) 25 mJ
Vcc 3 Supply voltage (Icc < 25mA) Self limiting V
IZCD/FB 6 Zero current detector current ±2 mA
Vcomp 8 Analog input -0.3 to 3.6 V
Ptot Power dissipation @TA = 50°C 0.9 W
TjJunction temperature range -25 to 150 °C
Tstg Storage temperature -55 to 150 °C
Table 3. Thermal data
Symbol Parameter Max. value Unit
Rth j-pin Thermal resistance, junction-to-pin 10 °C/W
Rth j-amb Thermal resistance, junction-to-ambient 110
ALTAIR04-900 Electrical characteristics
Doc ID 18211 Rev 2 7/29
4 Electrical characteristics
(TJ = -25 to 125 °C, Vcc = 14 V; unless otherwise specified)
Table 4. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Power section
V(BR)DSS Drain-source breakdown ID< 100 µA; Tj = 25 °C 900 V
IDSS Off state drain current VDS = 850 V; Tj = 125 °C
(See Figure 4 and note) 80 µA
RDS(on) Drain-source ON-state resistance Id=250 mA; Tj = 25 °C 16 19 W
Id=250 mA; Tj = 125 °C 38
Coss Effective (energy-related) output capacitance (See Figure 3)
High-voltage start-up generator
VStart Min. Drain start voltage Icharge < 100 µA 40 50 60 V
Icharge Vcc startup charge current
VDRAIN> VStart; Vcc < VccOn
Tj = 25 °C 45.5 7mA
VDRAIN> VStart; Vcc < VccOn +/-10%
VCCrestart Vcc restart voltage (Vcc falling)
(1) 9.5 10.5 11.5 V
After protection tripping 5
Supply voltage
Vcc Operating range After turn-on 11.5 23 V
VccOn Turn-on threshold (1) 12 13 14 V
VccOff Turn-off threshold (1) 91011V
VZZener voltage Icc = 20 mA 23 25 27 V
Supply current
Iccstart-up Start-up current (See Figure 5) 200 300 µA
Iq Quiescent current (See Figure 6)11.4mA
Icc Operating supply current @ 50 kHz (See Figure 7)1.41.7mA
Iq(fault) Fault quiescent current During hiccup and brownout
(See Figure 8)250 350 µA
Start-up timer
TSTART Start timer period 100 125 175 µs
TRESTART Restart timer period during burst mode 400 500 700 µs
Zero current detector
IZCDb Input bias current VZCD = 0.1 to 3 V 0.1 1 µA
VZCDH Upper clamp voltage IZCD = 1 mA 3.0 3.3 3.6 V
Electrical characteristics ALTAIR04-900
8/29 Doc ID 18211 Rev 2
VZCDL Lower clamp voltage IZCD = - 1 mA -90 -60 -30 mV
VZCDA Arming voltage positive-going edge 100 110 120 mV
VZCDT Triggering voltage negative-going edge 50 60 70 mV
IZCDON Min. source current during MOSFET ON-time -25 -50 -75 µA
TBLANK Trigger blanking time after MOSFET’s turn-off
VCOMP ≥ 1.3V 6µs
VCOMP = 0.9V 30
Line feedforward
RFF Equivalent feedforward resistor IZCD = 1mA 45 Ω
Transconductance error amplifier
VREF Voltage reference
Tj = 25°C (1) 2.46 2.5 2.54
V
Tj = -25 to 125°C and
Vcc=12V to 23V (1) 2.42 2.58
gm Transconductance ΔICOMP = ±10 µA
VCOMP = 1.65 V 1.3 2.2 3.2 mS
Gv Voltage gain Open loop 73 dB
GB Gain-bandwidth product 500 KHz
ICOMP
Source current VZCD = 2.3V, VCOMP = 1.65V 70 100 µA
Sink current VZCD = 2.7V, VCOMP = 1.65V 400 750 µA
VCOMPH Upper COMP voltage VZCD = 2.3 V 2.7 V
VCOMPL Lower COMP voltage VZCD = 2.7 V 0.7 V
VCOMPBM Burst-mode threshold 1 V
Hys Burst-mode hysteresis 65 mV
Current reference
VIREFx Maximum value VCOMP = VCOMPL (1) 1.5 1.6 1.7 V
GICurrent loop gain VCOMP = VCOMPH 0.5 0.6 0.7
VCREF Current reference voltage 0.38 0.4 0.42 V
Current sense
tLEB Leading-edge blanking 200 250 300 ns
td(H-L) Delay-to-output 300 ns
VCSx Max. clamp value dVcs/dt = 200 mV/µs (1) 0.7 0.75 0.8 V
VCSdis Hiccup-mode OCP level (1) 0.92 1 1.08 V
1. Parameters tracking each other
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
ALTAIR04-900 Electrical characteristics
Doc ID 18211 Rev 2 9/29
Figure 3. COSS Output capacitance variation
Figure 4. Off state drain and source current test circuit
Note: The measured IDSS is the sum between the current across the start-up resistor and the
effective MOSFET’s off state drain current
Figure 5. Start-up current test circuit
0 25 50 75 100 125 150
0
100
200
300
400
500
COSS (pF)
VDS (V)
A
Iq(f ault) AIdss
850 V
15V
2. 5V
COMP SOURCE
DRAINVDD
+
-
CURRENT
CONTROL
IREF GND
FB/ZCD
1 1.8 V
A
Ic cstart-up
2. 5V
COMP SOURCE
DRAINVDD
+
-
CURRENT
CONTROL
IR EF GND
FB/ZCD
Electrical characteristics ALTAIR04-900
10/29 Doc ID 18211 Rev 2
Figure 6. Quiescent current test circuit
Figure 7. Operating supply current test circuit
Note: The circuit across the ZCD pin is used for switch-on synchronization
Figure 8. Quiescent current during fault test circuit
14 VA
Iq_meas
0. 2V
3V
33k
0.8V 10k
2.5 V
COMP SOURCE
DRAINVDD
+
-
CURRENT
CONTROL
IREF GND
FB/ZCD
2.8V
1.5k
2W
AIcc 15 V
10
10 k10 k
-5V
50 kH z
27k
220 k
5.6
15 0V
2. 5V
COMP SOURCE
DRAINVDD
+
-
CURRENT
CONTROL
IREF GND
FB/ZCD
14V
A
Iq(fault)
2. 5V
COMP SOURCE
DRAINVDD
+
-
CURRENT
CONTROL
IR EF GND
FB/ZCD
ALTAIR04-900 Application information
Doc ID 18211 Rev 2 11/29
5 Application information
The device is an all-primary sensing switching regulator, based on quasi-resonant flyback
topology.
Depending on converter’s load condition, the device is able to work in different modes (see
Figure 9):
1. QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET's
turn-on to the transformer’s demagnetization by detecting the resulting negative-going
edge of the voltage across any winding of the transformer. Then the system works
close to the boundary between discontinuous (DCM) and continuous conduction
(CCM) of the transformer. As a result, the switching frequency is different for different
line/load conditions (see the hyperbolic-like portion of the curves in Figure 9). Minimum
turn-on losses, low EMI emission and safe behavior in short circuit are the main
benefits of this kind of operation.
2. Valley-skipping mode at medium/ light load. Depending on voltage on COMP pin, the
device defines the maximum operating frequency of the converter. As the load is
reduced MOSFET’s turn-on does not any more occur on the first valley but on the
second one, the third one and so on. In this way the switching frequency is no longer
increased (piecewise linear portion in Figure 9).
3. Burst-mode with no or very light load. When the load is extremely light or disconnected,
the converter enters a controlled on/off operation with constant peak current.
Decreasing the load results in frequency reduction, which can go down even to few
hundred hertz, thus minimizing all frequency-related losses and making it easier to
comply with energy saving regulations or recommendations. Being the peak current
very low, no issue of audible noise arises.
Figure 9. Multi-mode operation of ALTAIR04-900
0
fsw
Pinmax
Input voltage
Pin
fosc
Burst-mode
Valley-skipping
mode
Quasi-resonant mode
0
fsw
Pinmax
Input voltage
Pin
fosc
Burst-mode
Valley-skipping
mode
Quasi-resonant mode
0
fsw
Pinmax
Input voltage
Pin
fosc
Burst-mode
Valley-skipping
mode
Quasi-resonant mode
Application information ALTAIR04-900
12/29 Doc ID 18211 Rev 2
5.1 Power section and gate driver
The power section guarantees safe avalanche operation within the specified energy rating
as well as high dv/dt capability. The Power MOSFET has a V(BR)DSS of 900 V min. and a
typical RDS(on) of 16 Ω.
The gate driver is designed to supply a controlled gate current during both turn-on and turn-
off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the power MOSFET cannot be turned on
accidentally.
5.2 High voltage startup generator
Figure 10 shows the internal schematic of the high-voltage start-up generator (HV
generator). The HV current generator is supplied through the DRAIN pin and it is enabled
only if the input bulk capacitor voltage is higher than Vstart threshold, 50 VDC typically.
When the HV current generator is ON, the Icharge current (5.5 mA typical value) is delivered
to the capacitor on the VCC pin.
With reference to the timing diagram of Figure 10, when power is applied to the circuit and
the voltage on the input bulk capacitor is high enough, the HV generator is sufficiently
biased to start operating, thus it draws about 5.5 mA (typical) from the bulk capacitor. Most
of this current charges the bypass capacitor connected between the Vcc pin and ground and
make its voltage rise linearly.
As the Vcc voltage reaches the start-up threshold (13 V typ.) the chip starts operating, the
internal power MOSFET is enabled to switch and the HV generator is cut off by the Vcc_OK
signal asserted high. The IC is powered by the energy stored in the Vcc capacitor.
The chip is able to power itself directly from the rectified mains: when the voltage on the VCC
pin falls below Vccrestart (10.5V typ.), during each MOSFET’s off-time the HV current
generator is turned on and charges the supply capacitor until it reaches the VCCOn
threshold.
In this way, the self-supply circuit develops a voltage high enough to sustain the operation of
the device. This feature is useful especially during CC regulation, when the flyback voltage
generated by the auxiliary winding alone may not be able to keep Vcc above VCCrestart.
At converter power-down the system loses regulation as soon as the input voltage falls
below VStart. This prevents converter’s restart attempts and ensures monotonic output
voltage decay at system power-down.
ALTAIR04-900 Application information
Doc ID 18211 Rev 2 13/29
Figure 10. Timing diagram: normal power-up and power-down sequences
5.3 Zero current detection and triggering block
The zero current detection (ZCD) and triggering blocks switch on the power MOSFET if a
negative-going edge falling below 50 mV is applied to the ZCD/FB pin. To do so, the
triggering block must be previously armed by a positive-going edge exceeding 100 mV.
This feature is used to detect transformer demagnetization for QR operation, where the
signal for the ZCD input is obtained from the transformer’s auxiliary winding used also to
supply the IC.
Figure 11. ZCD block, triggering block
The triggering block is blanked after MOSFET’s turn-off to prevent any negative-going edge
that follows leakage inductance demagnetization from triggering the ZCD circuit
erroneously.
This blanking time is dependent on the voltage on COMP pin: it is TBLANK = 30 µs for VCOMP
= 0.9 V, and decreases almost linearly down to TBLANK = 6 µs for VCOMP = 1.3 V
Vcc
DRAIN
VccON
Vccresta rt
t
tt
t
Vin
VSta rt
Icha rg e
5.5 mA
t
t
Power-on Power-off
Normal op era tion
CV mode CC mode
Normal operation
Vcc
DRAIN
VccON
Vccresta rt
t
tt
t
Vin
VSta rt
Icha rg e
5.5 mA
t
t
Power-on Power-off
Normal op era tion
CV mode CC mode
Normal operation
60 m V
ZCD
CLAMP
B LAN KI N G
TI ME
TU R N - O N
LOGI C
STAR TER
S
R
Q
LEB
+
-
Aux
Rf b
Rzcd
To D riv er
From CC /CV Block
From OCP
ZCD/ FB
110mV
Application information ALTAIR04-900
14/29 Doc ID 18211 Rev 2
The voltage on the pin is both top and bottom limited by a double clamp, as illustrated in the
internal diagram of the ZCD block of Figure 11. The upper clamp is typically at 3.3 V, while
the lower clamp is located at -60mV. The interface between the pin and the auxiliary winding
is a resistor divider. Its resistance ratio as well as the individual resistance values has to be
properly chosen (see “Section 5.4: Constant voltage operation” and “Section 5.6: Voltage
feedforward block”.
Please note that the maximum IZCD/FB sunk/sourced current has to not exceed ±2 mA
(AMR) in all the Vin range conditions. No capacitor is allowed between ZCD pin and the
auxiliary transformer.
The switching frequency is top-limited below 166 kHz, as the converter’s operating
frequency tends to increase excessively at light load and high input voltage.
A Starter block is also used to start-up the system, that is, to turn on the MOSFET during
converter power-up, when no or a too small signal is available on the ZCD pin.
The starter frequency is 2 kHz if COMP pin below burst mode threshold, i.e. 1 V, while it
becomes 8 kHz if this voltage exceed this value.
After the first few cycles initiated by the starter, as the voltage developed across the auxiliary
winding becomes large enough to arm the ZCD circuit, MOSFET’s turn-on starts to be
locked to transformer demagnetization, hence setting up QR operation.
The starter is activated also when the IC is in CC regulation and the output voltage is not
high enough to allow the ZCD triggering.
If the demagnetization completes – hence a negative-going edge appears on the ZCD pin –
after a time exceeding time TBLANK from the previous turn-on, the MOSFET is turned on
again, with some delay to ensure minimum voltage at turn-on. If, instead, the negative-going
edge appears before TBLANK has elapsed, it is ignored and only the first negative-going
edge after TBLANK turns-on the MOSFET. In this way one or more drain ringing cycles is
skipped (“valley-skipping mode”, Figure 12) and the switching frequency is prevented from
exceeding 1/TBLANK.
Figure 12. Drain ringing cycle skipping as the load is progressively reduced
Note that when the system operates in valley skipping-mode, uneven switching cycles may
be observed under some line/load conditions, due to the fact that the OFF-time of the
MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time
needed for cycle-by-cycle energy balance may fall in between. Thus one or more longer
switching cycles is compensated by one or more shorter cycles and vice versa. However,
this mechanism is absolutely normal and there is no appreciable effect on the performance
of the converter or on its output voltage.
Pin = Pin'
( limit co ndi ti on) Pin = P in '' < Pin' Pin = Pin''' < Pin''
t
V
DS
T
FW
T
osc
T
V
T
ON
t
VDS
T
osc
t
VDS
T
osc
ALTAIR04-900 Application information
Doc ID 18211 Rev 2 15/29
5.4 Constant voltage operation
The IC is specifically designed to work in primary regulation and the output voltage is
sensed through a voltage partition of the auxiliary winding, just before the auxiliary rectifier
diode.
Figure 13 shows the internal schematic of the constant voltage mode and the external
connections.
Figure 13. Voltage control principle: internal schematic
Due to the parasitic wires resistance, the auxiliary voltage is representative of the output just
when the secondary current becomes zero. For this purpose, the signal on ZCD/FB pin is
sampled-and-held at the end of transformer’s demagnetization to get an accurate image of
the output voltage and it is compared with the error amplifier internal reference.
The COMP pin is used for the frequency compensation: usually, an RC network, which
stabilizes the overall voltage control loop, is connected between this pin and ground.
The output voltage can be defined according the formula:
Where NSEC and NAUX are the secondary and auxiliary turn’s number respectively.
The RZCD value can be defined depending on the application parameters (see “Section 5.6:
Voltage feedforward block”).
2. 5V
Rzcd
From Rsense
Aux
+
-
EA
R
To PWM Logic
S/ H
Rf b
DEMAG
LOGI C
+
-
CV
C
COMP
ZCD/FB
(1)
RFB
VREF
NAUX
NSEC
-------------- VOUT VREF
–⋅
------------------------------------------------------ RZCD
⋅=
Application information ALTAIR04-900
16/29 Doc ID 18211 Rev 2
5.5 Constant current operation
Figure 14 presents the principle used for controlling the average output current of the
flyback converter.
The output voltage of the auxiliary winding is used by the demagnetization block to generate
the control signal for the mosfet switch Q1. A resistor R in series with it absorbs a current
VC/R, where VC is the voltage developed across the capacitor Cref.
The flip-flop’s output is high as long as the transformer delivers current on secondary side.
This is shown in Figure 15.
The capacitor Cref has to be chosen so that its voltage VC can be considered as a constant.
Since it is charged and discharge by currents in the range of some ten µA (ICREF is typically
20 µA) at the switching frequency rate, a capacitance value in the range 4.7-10 nF is suited
for switching frequencies in the ten kHz.
The average output current can be expressed as:
where NPRI is the primary turn's number.
This formula shows that the average output current does not depend anymore on the input
or the output voltage, neither on transformer inductance values. The external parameters
defining the output current are the transformer ratio n and the sense resistor RSENSE.
Current loop gain GI and current reference voltage VCREF are internally defined.
Figure 14. Current control principle
(2)
I
OUT NPRI
NSEC
----------- ---
GIVCREF
⋅
2R
SENSE
⋅()
------------- ------------- -------
⋅=
.
IREF
Rzcd
Rfb
Aux
Q1
Iref
R
Gi
DEMAG
LOGI C
To PWM Logic
From Rsense
ZCD/ FB
+
-
CC
C
S
R
Q
ALTAIR04-900 Application information
Doc ID 18211 Rev 2 17/29
Figure 15. Constant current operation: Switching cycle waveforms
5.6 Voltage feedforward block
The current control structure uses the voltage VC to define the output current, according to
(2). Actually, the CC comparator is affected by an internal propagation delay Td, which
switches off the MOSFET with a peak current than higher the foreseen value.
This current overshoot is equal to:
where Lp is the primary inductance and it introduces an error on the calculated CC setpoint,
depending on the input voltage.
The device implements a line feedforward function, which solves the issue by introducing an
input voltage dependent offset on the current sense signal, in order to adjust the cycle-by-
cycle current limitation.
The internal schematic is shown in Figure 16.
t
t
t
t
IP
Is
Q
IC
T
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V
IC
CREF −=
CREF
I
(3)
IN d
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P
VT
ΔIL
⋅
=
Application information ALTAIR04-900
18/29 Doc ID 18211 Rev 2
Figure 16. Feedforward compensation: internal schematic
The RZCD resistor can be calculated as follows:
In this case the peak drain current does not depend on input voltage anymore.
One more consideration concerns the RZCD value: during MOSFET’s ON-time, the current
sourced by the ZCD/FB pin, IZCD, is compared with an internal reference current IZCDON (-50
µA typical).
If IZCD < IZCDON, the brownout function is activated and the IC is shut-down.
This feature is especially important when the auxiliary winding is accidentally disconnected
and considerably increases the end-product’s safety and reliability.
5.7 Burst-mode operation at no load or very light load
When the voltage at the COMP pin falls 65 mV below a threshold fixed internally at a value,
VCOMPBM, the IC is disabled with the MOSFET kept in OFF state and its consumption
reduced at a lower value to minimize Vcc capacitor discharge.
In this condition the converter operates in burst-mode (one pulse train every TSTART=500
µs), with minimum energy transfer.
As a result of the energy delivery stop, the output voltage decreases: after 500 µs the
controller switches-on the MOSFET again and the sampled voltage on the ZCD pin is
compared with the internal reference. If the voltage on the EA output, as a result of the
comparison, exceeds the VCOMPL threshold, the device restarts switching, otherwise it stays
OFF for another 500 µs period.
In this way the converter works in burst-mode with a nearly constant peak current defined by
the internal disable level. Then a load decrease causes a frequency reduction, which can go
down even to few hundred hertz, thus minimizing all frequency-related losses and making it
easier to comply with energy saving regulations. This kind of operation, shown in the timing
.
CC
Block
Aux
R zcd
Rfb
IFF
Rsense
Rff
+
-
CC
Feedforward
Logic
PWM
LOGI C
ZCD/ FB
DRAIN
SOURCE
(4)
AUX P FF
ZCD
PRI d SENSE
NLR
RNTR
⋅
=⋅
⋅
ALTAIR04-900 Application information
Doc ID 18211 Rev 2 19/29
diagrams of Figure 17 along with the others previously described, is noise-free since the
peak current is low
Figure 17. Load-dependent operating modes: timing diagrams
5.8 Soft-start and starter block
The soft start feature is automatically implemented by the constant current block, as the
primary peak current is limited from the voltage on the CREF capacitor.
During start-up, as the output voltage is zero, the IC starts in CC mode with no high peak
current operations. In this way the voltage on the output capacitor increases slowly and the
soft-start feature is ensured.
Actually the CREF value is not important to define the soft-start time, as its duration
depends on others circuit parameters, like transformer ratio, sense resistor, output
capacitors and load. The user can define the best appropriate value by experiments.
CO M P
I
DS
65 mV
hyster.
Normal-modeBurst-modeNormal-mode
T
STA R T
T
START
T
START
T
ST AR T
V
COMPL
Application information ALTAIR04-900
20/29 Doc ID 18211 Rev 2
5.9 Hiccup mode OCP
The device is also protected against short circuit of the secondary rectifier, short circuit on
the secondary winding or a hard-saturated flyback transformer. A comparator monitors
continuously the voltage on the RSENSE and activates a protection circuitry if this voltage
exceeds 1 V.
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the
first time the comparator is tripped the protection circuit enters a “warning state”. If in the
subsequent switching cycle the comparator is not tripped, a temporary disturbance is
assumed and the protection logic will be reset in its idle state; if the comparator is tripped
again a real malfunction is assumed and the device is stopped.
This condition is latched as long as the device is supplied. While it is disabled, however, no
energy is coming from the self-supply circuit; hence the voltage on the VCC capacitor decays
and cross the UVLO threshold after some time, which clears the latch. The internal start-up
generator is still off, then the VCC voltage still needs to go below its restart voltage before the
VCC capacitor is charged again and the device restarted. Ultimately, this results in a low-
frequency intermittent operation (Hiccup-mode operation), with very low stress on the power
circuit. This special condition is illustrated in the timing diagram of Figure 18.
Figure 18. Hiccup-mode OCP: timing diagram
VDS
Vc cON
Vc cOF F
Vccrest
Secondary diode is shorted here
t
t
t
VSOURCE
1 V
Two switching cycles
VCC
Vcsdis
ALTAIR04-900 Application information
Doc ID 18211 Rev 2 21/29
5.10 Layout recommendations
A proper printed circuit board layout is essential for correct operation of any switch-mode
converter and this is true for the ALTAIR04-900 as well. Careful component placing, correct
traces routing, appropriate traces widths and compliance with isolation distances are the
major issues. In particular:
●The compensation network should be connected as close as possible to the COMP
pin, maintaining the trace for the GND as short as possible
●Signal Ground should be routed separately from power ground, as well from the sense
resistor trace.
Figure 19. Suggested routing for converter
A
C IN
OU
T
GND
COMP SOU RCE
DRAI N
VD
D
IREFGN
D
FB/ZC
D
A
LTAIR04-90
0
A
C IN
Typical application ALTAIR04-900
22/29 Doc ID 18211 Rev 2
6 Typical application
Figure 20. Test board schematic: 4.5 W (9 V - 500 mA) wide range mains adapter
Figure 21. Electrical schematic for 440 Vac input voltage option thanks to the 900 V
rated power section of Altair04-900
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ALTAIR04-900 Typical application
Doc ID 18211 Rev 2 23/29
6.1 Test board: evaluation data
Figure 22. No-load consumption Figure 23. Efficiency at full load
100 150 200 250 300 350 400
0
20
40
60
80
100
Input Power [mW]
DC Input Voltage [V] 50 100 150 200 250 300
50
60
70
80
90
10 0
Eff iciency [%]
AC Inp u t Vol tage [ VAC]
Figure 24. VI Curve @ 110 VAC Figure 25. VI Curve @ 264 VAC
0 100 200 300 400 500
6
7
8
9
10
11
12
Output Voltage [V]
Output Current [mA]
0 100 200 300 400 500
6
7
8
9
10
11
12
Output Voltage [V]
Output Current [mA]
Typical application ALTAIR04-900
24/29 Doc ID 18211 Rev 2
6.2 Test board: main waveforms
Figure 26. 110 VAC, No-load Figure 27. 264 VAC, No-load
M: 400 s/div
M: 400 s/div
Figure 28. 110 VAC, Full load Figure 29. 234 VAC, Full load
M: 400 s/div
M: 400 s/div
ALTAIR04-900 Package mechanical data
Doc ID 18211 Rev 2 25/29
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 5. SO16N mechanical data
Dim.
Mm inch
Min Typ Max Min Typ Max
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45° (typ.)
D (1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F(1) 3.8 4.0 0.150 0.157
G 4.60 5.30 0.181 0.208
L 0.4 1.27 0.150 0.050
M 0.62 0.024
S 8 °(max.)
Package mechanical data ALTAIR04-900
26/29 Doc ID 18211 Rev 2
Figure 30. Package dimensions
ALTAIR04-900 Order codes
Doc ID 18211 Rev 2 27/29
8 Order codes
Table 6. Ordering information
Order code Package Packaging
ALTAIR04-900 SO16N Tu b e
ALTAIR04-900TR Tape and reel
ALTAIR04-900
Doc ID 18211 Rev 2 29/29
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