2:1, Single-Ended Multiplexer ICS83052I DATA SHEET GENERAL DESCRIPTION FEATURES The ICS83052I is a low skew, 2:1, Single-ended Multiplexer. The ICS83052I has two selectable single-ended clock inputs and one single-ended clock output. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage trans-lation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. The device operates up to 250MHz and is packaged in an 8 TSSOP. * 2:1 single-ended multiplexer * Q nominal output impedance: 15 (VDDO = 3.3V) * Maximum output frequency: 250MHz * Propagation delay: 2.7ns (maximum), (VDD = VDDO = 3.3V) * Input skew: 160ps (maximum), (VDD = VDDO = 3.3V) * Part-to-part skew: 490ps (maximum), (VDD = VDDO = 3.3V) * Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz): 0.18ps (typical), (VDD = VDDO = 3.3V) * Operating supply modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V * -40C to 85C ambient operating temperature * Available in standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT VDDO GND CLK1 VDD CLK0 Q CLK1 1 2 3 4 8 7 6 5 Q SEL0 CLK0 OE ICS83052I 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View SEL0 OE ICS83052I REVISION B DECEMBER 8, 2011 1 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDO Power Type Description Output supply pin. 2 GND Power 3, 6 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Power supply ground. 4 VDD Power 5 OE Input 7 SEL0 Input 8 Q Output Positive supply pin. Output enable. When LOW, outputs are in HIGH impedance state. Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Clock select input. See Table 3. Control Input Function Table. Pulldown LVCMOS / LVTTL interface levels. Single-ended clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Test Conditions Minimum Typical Maximum Units Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Power Dissipation Capacitance (per output) VDDO = 3.465V 18 pF CPD VDDO = 2.625V 19 pF VDDO = 1.89V 19 pF 15 ROUT Output Impedance TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs SEL0 0 1 Input Selected to Q CLK0 CLK1 ICS83052I REVISION B DECEMBER 8, 2011 2 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA Storage Temperature, TSTG NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 4.6V 101.7C/W (0 mps) -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5%, 2.5V5% OR 1.8V5%,TA = -40C TO 85C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V 1.71 1.8 1.89 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 2.5V5% OR 1.8V5%, TA = -40C TO 85C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V 2.375 2.5 2.625 V 1.71 1.8 VDDO Output Supply Voltage 1.89 V IDD Power Supply Current 36 mA IDDO Output Supply Current 5 mA ICS83052I REVISION B DECEMBER 8, 2011 3 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40C TO 85C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage IIH Input High Current IIL Input Low Current VOH VOL CLK0, CLK1, SEL0 OE CLK0, CLK1, SEL0 OE Output HighVoltage Output Low Voltage Test Conditions Minimum Maximum Units VDD = 3.3V 5% 2 Typical VDD + 0.3 V VDD = 2.5V 5% 1.7 VDD + 0.3 V VDD = 3.3V 5% -0.3 0.8 V VDD = 2.5V 5% -0.3 0.7 V VDD = 3.3V or 2.5V 5% 150 A VDD = 3.3V or 2.5V 5% 5 A VDD = 3.3V or 2.5V 5% -5 A VDD = 3.3V or 2.5V 5% -150 A VDDO = 3.3V 5%; NOTE 1 2.6 V VDDO = 2.5V 5%; NOTE 1 1.8 V VDDO = 1.8V 5%; NOTE 1 VDD - 0.3 V VDDO = 3.3V 5%; NOTE 1 0.5 V VDDO = 2.5V 5%; NOTE 1 0.45 V VDDO = 1.8V 5%; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL tsk(i) tR / tF Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle tsk(pp) tjit Test Conditions 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Minimum Typical Maximum Units 250 MHz 2.0 2.4 2.7 ns 2.0 2.5 2.9 ns 36 160 ps 490 ps 0.18 ps 200 700 ps 45 55 % 45 dB MUXISOLATION MUX Isolation NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS83052I REVISION B DECEMBER 8, 2011 4 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL tsk(i) tR / tF Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle tsk(pp) tjit Test Conditions Minimum Typical Units 250 MHz 2.3 2.6 2.9 ns 2.3 2.6 2.9 ns 106 ps 350 ps 23 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Maximum 0.14 ps 300 700 ps 46 54 % 45 dB MUXISOLATION MUX Isolation NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL tsk(i) tR / tF Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle tsk(pp) tjit Test Conditions 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Minimum Typical Maximum Units 250 MHz 2.3 3.1 3.9 ns 2.3 3.1 3.9 ns 19 66 ps 350 ps 0.16 ps 350 850 ps 46 54 % 45 dB MUXISOLATION MUX Isolation NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS83052I REVISION B DECEMBER 8, 2011 5 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL tsk(i) tR / tF Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle tsk(pp) tjit Test Conditions Minimum Typical Units 250 MHz 2.2 2.7 3.2 ns 2.2 2.7 3.2 ns 123 ps 400 ps 28 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Maximum 0.22 ps 300 700 ps 45 55 % MUXISOLATION MUX Isolation 45 dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL tsk(i) tR / tF Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle tsk(pp) tjit Test Conditions 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Minimum Typical Maximum Units 250 MHz 2.1 3.1 4.1 ns 2.1 3.1 4.2 ns 19 73 ps 350 ps 0.19 ps 350 850 ps 45 55 % 45 dB MUXISOLATION MUX Isolation NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS83052I REVISION B DECEMBER 8, 2011 6 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz 0 -10 Additive Phase Jitter (Random) -20 at 155.52MHz (12kHz - 20MHz) = 0.18ps (typical) -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of ICS83052I REVISION B DECEMBER 8, 2011 the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 7 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 1.65V5% 1.25V5% SCOPE VDD, VDDO SCOPE VDD, VDDO Qx Qx LVCMOS LVCMOS GND GND -1.25V5% -1.65V5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.45% 2.05V5% 0.9V5% 1.25V5% SCOPE VDD VDDO SCOPE VDD VDDO Qx Qx GND GND LVCMOS LVCMOS -0.9V5% -1.25V5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 1.6V5% 0.9V5% Part 1 SCOPE VDD VDDO Qx V DDO 2 Qx Part 2 GND LVCMOS Qy V DDO 2 tsk(pp) -0.9V5% 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT ICS83052I REVISION B DECEMBER 8, 2011 PART-TO-PART SKEW 8 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER VDD VDD 2 2 CLK0, CLK1 VDDO Q VDDO 2 tpLH 80% 80% Clock Outputs 2 tpHL PROPAGATION DELAY 20% 20% tR tF OUTPUT RISE/FALL TIME CLKx V DDO 2 Q Q t PW tPD1 t odc = PERIOD t PW x 100% t PERIOD CLKy Q tPD2 tsk(i) = tPD2 - tPD1 INPUT SKEW ICS83052I REVISION B DECEMBER 8, 2011 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 9 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER APPLICATIONS INFORMATION RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. ICS83052I REVISION B DECEMBER 8, 2011 10 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS830521I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS830521I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation * Power (core) * Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2 MAX = VDD_MAX * (IDD+ IDDo ) = 3.4565V * (40mA + 5mA) = 155.93mW Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465 / [2 * (50 + 15)] = 26.7mA * Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW Dynamic Power Dissipation at 250MHz * Power (250MHz) = CPD * frequency * (VDD)2 = 18pF * 250MHz * (3.465V)2 = 54.0mW Total Power Dissipation * Total Power = Power (core)MAX + Power (ROUT) Total Power + Power (250MHz) = 155.93mW + 10.7mW + 54.0mW =220.6mW ICS83052I REVISION B DECEMBER 8, 2011 11 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER 2. Junction Temperature Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction, TJ, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 101.7C/W per Table 6. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.221W * 101.7C/W = 107.4C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS83052I REVISION B DECEMBER 8, 2011 JA BY Velocity 0 101.7C/W 12 1 2.5 90.5C/W 89.8C/W (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for ICS83052I is: 967 ICS83052I REVISION B DECEMBER 8, 2011 13 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet PACKAGE OUTLINE - G SUFFIX 2:1, SINGLE ENDED MULTIPLEXER FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS83052I REVISION B DECEMBER 8, 2011 14 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 83052AGI 052AI 8 lead TSSOP tube -40C to 85C 8 lead TSSOP 2500 tape & reel -40C to 85C 83052AGIT 052AI 83052AGILF 52AIL 8 lead "Lead-Free" TSSOP tube -40C to 85C 83052AGILFT 52AIL 8 lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS83052I REVISION B DECEMBER 8, 2011 15 (c)2011 Integrated Device Technology, Inc. ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER REVISION HISTORY SHEET Re v B Table 4A, 4B T8 T8 Page 3 12 12 De s cription of Change Power Supply Tables - corrected VDDO min/max. Ordering Information Table - added lead- free marking. Ordering Information Table - corrected lead- free marking. B T4B B T5A, 5B, 5C, 5D, 5E, 3 All, 4, 5, 6 11, 12 17 2.5V Power Supply Table - corrected units for IDD & IDDO. Updated Header and Footer. Added Note to Tables.Updated Contact Information. Added Power Considerations section. Updated Contact Information. B ICS83052I REVISION B DECEMBER 8, 2011 Date 8/7/06 3/16/07 6/25/08 12/8/11 16 (c)2011 Integrated Device Technology, Inc. We've Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 (c) 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA