ICS83052AGILFT - INTEGRATED DEVICE TECHNOLOGY

2:1, Single-Ended Multiplexer ICS83052I

DATA SHEET

ICS83052I REVISION B DECEMBER 8, 2011 1©201 1 Integrated Device Technology , Inc.

GENERAL DESCRIPTION

The ICS83052I is a low skew, 2:1, Single-ended Multiplexer. The

ICS83052I has two selectable single-ended clock inputs and one

single-ended clock output. The output has a VDDO pin which may

be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in

voltage trans-lation applications. An output enable pin places the

output in a high impedance state which may be useful for testing

or debug. The device operates up to 250MHz and is packaged in

an 8 TSSOP.

BLOCK DIAGRAM PIN ASSIGNMENT

FEATURES

• 2:1 single-ended multiplexer

• Q nominal output impedance: 15Ω (VDDO = 3.3V)

• Maximum output frequency: 250MHz

• Propagation delay: 2.7ns (maximum), (VDD = VDDO = 3.3V)

• Input skew: 160ps (maximum), (VDD = VDDO = 3.3V)

• Part-to-part skew: 490ps (maximum), (VDD = VDDO = 3.3V)

• Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz):

0.18ps (typical), (VDD = VDDO = 3.3V)

• Operating supply modes:

VDD/VDDO

3.3V/3.3V

3.3V/2.5V

3.3V/1.8V

2.5V/2.5V

2.5V/1.8V

• -40°C to 85°C ambient operating temperature

• Available in standard (RoHS 5) and lead-free (RoHS 6)

packages

CLK0

CLK1

SEL0

ICS83052I

8-Lead TSSOP

4.40mm x 3.0mm x 0.925mm

package body

G Package

Top View

VDDO

GND

CLK1

VDD

SEL0

CLK0

ICS83052I REVISION B DECEMBER 8, 2011 2©201 1 Integrated Device Technology , Inc.

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

TABLE 3. CONTROL INPUT FUNCTION TABLE

rebmuNemaNepyTnoitpircseD

ODD

rewoP.nipylppustuptuO

2DNGrewoP.dnuorgylppusrewoP

6,30KLC,1KLCtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.stupnik

colcdedne-elgniS

rewoP.nipylppusevitisoP

5EOtupnIpulluP .etatsecnadepmiHGIHnierastuptuo,WOLnehW.elbanetuptuO

.slevelecafretni

LTTVL/SOMCVL.evitcaerastuptuo,HGIHnehW

70LEStupnInwodlluP eeS.tupnitceleskcolC .elbaTnoitcnuFtupnIlortnoC.3

elbaT

.slevelecafretniLTTVL/SOMCVL

8QtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcdedne-elgniS

:ETON pullu

Pdna nwodlluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

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ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15kΩ

ecnaticapaCnoitapissiDrewoP

)tuptuorep(

ODD

V564.3=81Fp

ODD

V526.2=91Fp

ODD

V98.1=91Fp

TUO

ecnadepmItuptuO 51 Ω

stupnIlortnoC QotdetceleStupnI

0LES

00KLC

11KLC

ICS83052I REVISION B DECEMBER 8, 2011 3©201 1 Integrated Device Technology , Inc.

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5 V

Outputs, V

O-0.5V to VDDO + 0.5V

Package Thermal Impedance, θJA 101.7°C/W (0 mps)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional op-

eration of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5%, 2.5V±5% OR 1.8V±5%,TA = -40°C TO 85°C

TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 2.5V±5% OR 1.8V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ODD

egatloVylppuStuptuO

531.33.3564.3V

573.25.2526.2V

17.18.198.1V

tnerruCylppuSrewoP 04Am

ODD

tnerruCylppuStuptuO 5Am

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 573.25.2526.2V

ODD

egatloVylppuStuptuO 573.25.2526.2V

17.18.198.1V

tnerruCylppuSrewoP 63Am

ODD

tnerruCylppuStuptuO 5Am

ICS83052I REVISION B DECEMBER 8, 2011 4©201 1 Integrated Device Technology , Inc.

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C

TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI V

%5±V3.3=2V

3.0+V

%5±V5.2=7.1V

3.0+V

egatloVwoLtupnI V

%5±V3.3=3.0-8.0V

%5±V5.2=3.0-7.0V

tnerruChgiHtupnI

,1KLC,0KLC

0LES V

%5±V5.2roV3.3=051Aμ

EOV

%5±V5.2roV3.3=5Aμ

tnerruCwoLtupnI

,1KLC,0KLC

0LES V

%5±V5.2roV3.3=5-Aμ

EOV

%5±V5.2roV3.3=051-Aμ

hgiHtuptuOegatloV

ODD

1ETON;%5±V3.3=6.2V

ODD

1ETON;%5±V5.2=8.1V

ODD

1ETON;%5±V8.1=V

3.0-V

egatloVwoLtuptuO

ODD

1ETON;%5±V3.3=5.0V

ODD

1ETON;%5±V5.2=54.0V

ODD

1ETON;%5±V8.1=53.0V

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ICS83052I REVISION B DECEMBER 8, 2011 5©201 1 Integrated Device Technology , Inc.

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C

TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C

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ICS83052I REVISION B DECEMBER 8, 2011 6©201 1 Integrated Device Technology , Inc.

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C

TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C

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1ETON 2.27.22.3sn

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t)pp(ks 4,2ETON;wekStraP-ot-traP 004sp

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ICS83052I REVISION B DECEMBER 8, 2011 7©201 1 Integrated Device Technology , Inc.

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

ADDITIVE PHASE JITTER

Additive Phase Jitter (Random)

at 155.52MHz (12kHz - 20MHz)

= 0.18ps (typical)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

The spectral purity in a band at a specific offset from the

fundamental compared to the power of the fundamental is called

the dBc Phase Noise. This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise power

present in a 1Hz band at a specified offset from the fundamental

frequency to the power value of the fundamental. This ratio is

expressed in decibels (dBm) or a ratio of the power in the 1Hz

As with most timing specifications, phase noise measurements

has issues relating to the limitations of the equipment. Often

the noise floor of the equipment is higher than the noise floor of

band to the power in the fundamental. When the required offset

is specified, the phase noise is called a dBc value, which simply

means dBm at a specified offset from the fundamental. By

investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

the device. This is illustrated above. The device meets the noise

floor of what is shown, but can actually be lower. The phase

noise is dependant on the input source and measurement

equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB P HASE NOISE dBc /HZ

1k 10k 100k 1M 10M 100M

ICS83052I REVISION B DECEMBER 8, 2011 8©201 1 Integrated Device Technology , Inc.

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

PARAMETER MEASUREMENT INFORMATION

SCOPE

LVCMOS

GND

3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

2.4±5%

VDDO

-0.9V±5%

VDD

0.9V±5%

SCOPE

LVCMOS

GND

2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

2.05V±5%

VDDO

-1.25V±5%

VDD

1.25V±5%

3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

LVCMOS

GND

1.65V±5%

-1.65V±5%

3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW

SCOPE

LVCMOS

GND

1.25V±5%

-1.25V±5%

SCOPE

LVCMOS

GND

1.6V±5%

VDDO

-0.9V±5%

VDD

0.9V±5%

VDD,

VDDO

VDD,

VDDO

tsk(pp)

DDO

Part 1

Part 2

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

Clock

Outputs

20%

80% 80%

20%

PERIOD

odc =

DDO

x 100%

tPW

DDO

CLK0, CLK1

INPUT SKEW

OUTPUT RISE/FALL TIMEPROPAGATION DELAY

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

PD1

PD2

tsk(i) = ⏐t

PD2

– t

PD1

⏐

CLKx

CLKy

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

INPUTS:

CLK INPUT:

For applications not requiring the use of the test clock, it can be

left floating. Though not required, but for additional protection, a

1kΩ resistor can be tied from the CLK input to ground.

CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT PINS

APPLICATIONS INFORMATION

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS830521I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS830521I is the sum of the core power plus the analog power plus the power

dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

Core and LVDS Output Power Dissipation

•Power (core)MAX = VDD_MAX * (IDD+ IDDo ) = 3.4565V * (40mA + 5mA) = 155.93mW

•Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDD/2

Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465 / [2 * (50Ω + 15Ω)] = 26.7mA

•Power Dissipation on the ROUT per LVCMOS output

Power (ROUT) = ROUT * (IOUT)2 = 15Ω * (26.7mA)2 = 10.7mW

Dynamic Power Dissip ation at 250MHz

•Power (250MHz) = CPD * frequency * (VDD)2 = 18pF * 250MHz * (3.465V)2 = 54.0mW

Total Power Dissip ation

•T ot al Power

= Power (core)MAX + Power (ROUT) Total Power + Power (250MHz)

= 155.93mW + 10.7mW + 54.0mW

=220.6mW

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

2. Junction T emperature

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of

the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction, TJ, to

125°C ensures that the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used.

Assuming no air flow and a multi-layer board, the appropriate value is 101.7°C/W per Table 6.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.221W * 101.7°C/W = 107.4°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air

flow, and the type of board (multi-layer).

TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP

θθ

yticoleVYB

dnoceSrepsreteM 015.2

sdraoBtseTdradnatSCEDEJ,BCPreyaL-itluMW/C°7.101W/C°5.09W/C°8.98

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS83052I is: 967

ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

TABLE 7. PACKAGE DIMENSIONS

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

Reference Document: JEDEC Publication 95, MO-153

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1A50.051.0

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1E03.405.4

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ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and

industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

TABLE 8. ORDERING INFORMATION

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ICS83052I Data Sheet 2:1, SINGLE ENDED MULTIPLEXER

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B8T21.gnikrameerf-daeldetcerroc-elbaTnoitam

rofnIgniredrO 70/61/3

BB4T3 Irofstinudetcerroc-elbaTylppuSrewoPV5.2

ODD

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11/8/21

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