1 of 20
FEATURES
Real-Time Clock (RTC) Keeps Track of
Hundredths of Seconds, Minutes, Hours,
Days, Date of the Month, Months, and Years
32K x 8 NV SRAM Directly Replaces
Volatile Static RAM or EEPROM
Embedded Lithium Energy Cell Maintains
Calendar Operation and Retains RAM Data
Watch Function is Transparent to RAM
Operation
Automatic Leap Year Compensation Valid
Up to 2100
Full 10% Operating Range
Over 10 Years of Data Retention in the
Absence of Power
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
DIP Module Only
Standard 28-Pin JEDEC Pinout
PowerCap Module Board Only
– Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
– Replaceable Battery (PowerCap)
– Pin-for-Pin Compatible with DS1248P
and DS1251P
Underwriters Laboratories (UL) Recognized
PIN CONFIGURATIONS
EDIP Module
(740 mils)
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
14
13
28
27
26
25
24
23
22
21
20
19
18
17
15
16
A14/RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
N.C.
N.C.
WE
CE
DQ7
DQ6
DQ4
DQ3
DQ1
DQ0
N.C.
33
32
31
29
27
25
24
22
20
18
A12
A11
A9
A8
A6
A5
A2
A4
A0
V
CC
28
A1
RST
N.C.
OE
DQ5
DQ2
GND
A14
30
26
23
19
A13
A10
A7
A3
34
N.C.
X1
GND
V
BAT
X2
PowerCap Module
(Uses DS9034PCX+ PowerCap)
TOP VIEW
DS1244P
DS1244
DS1244/DS1244P
256K NV SRAM
with Phantom Clock
www.maxim-ic.com
19-6077; Rev 11/11
DS1244/DS1244P
2 of 20
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
VOLTAGE
(V)
DS1244W-120+
0°C to +70°C
28 EDIP (0.740a)
3.3
DS1244W-120IND+
-40°C to +85°C
28 EDIP (0.740a)
3.3
DS1244WP-120+
0°C to +70°C
34 PowerCap*
3.3
DS1244WP-120IND+
-40°C to +85°C
34 PowerCap*
3.3
DS1244Y-70+
0°C to +70°C
28 EDIP (0.740a)
5.0
DS1244YP-70+
0°C to +70°C
34 PowerCap*
5.0
+Denotes a lead(Pb)-free/RoHS-compliant device.
*DS9034PCX+ or DS9034I-PCX+ (PowerCap) required. (Must be ordered separately.)
DS1244/DS1244P
3 of 20
PIN DESCRIPTION
PIN
NAME FUNCTION
EDIP
PowerCap
1 1 A14/RST
Address Input/Active-Low Reset Input. This pin has an internal
pullup resistor connected to VCC. A14 address on the EDIP
package.
1
32
A14
Address Inputs
2
30
A12
3
25
A7
4
24
A6
5
23
A5
6
22
A4
7
21
A3
8
20
A2
9
19
A1
10
18
A0
21
28
A10
23
29
A11
24
27
A9
25
26
A8
26
31
A13
11
16
DQ0
Data In/Data Out
12
15
DQ1
13
14
DQ2
15
13
DQ3
16
12
DQ4
17
11
DQ5
18
10
DQ6
19
9
DQ7
20
8
CE
Active-Low Chip-Enable Input
22
7
OE
Active-Low Output-Enable Input
27
6
WE
Active-Low Write-Enable Input
—
2, 3, 4, 33,
34
N.C. No Connection
28
5
VCC
Power-Supply Input
14
17
GND
Ground
DS1244/DS1244P
4 of 20
DESCRIPTION
The DS1244 256K NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM)
(organized as 32K words by 8 bits) with a built-in real-time clock. The DS1244 has a self-contained
lithium energy source and control circuitry, which constantly monitors VCC for an out-of-tolerance
condition. When such a condition occurs, the lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent garbled data in both the memory and real-time
clock.
The phantom clock provides timekeeping information for hundredths of seconds, seconds, minutes, hours,
days, date, months, and years. The date at the end of the month is automatically adjusted for months with
fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or
12-hour format with an AM/PM indicator.
PACKAGES
The DS1244 is available in two packages: 28-pin encapsulated DIP and 34-pin PowerCap module. The
28-pin DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The
34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on
top of the DS1244P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and
PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap
is DS9034PCX.
RAM READ MODE
The DS1244 executes a read cycle whenever
WE
(write enable) is inactive (high) and
CE
(chip enable)
is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the
32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within tACC
(access time) after the last address input signal is stable, providing that
CE
and
OE
(output enable)
access times and states are also satisfied. If
OE
and
CE
access times are not satisfied, then data access
must be measured from the later occurring signal (
CE
or
OE
) and the limiting parameter is either tCO for
CE
or tOE for
OE
, rather than address access.
RAM WRITE MODE
The DS1244 is in the write mode whenever the
WE
and
CE
signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of
CE
or
WE
will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs
must be kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery
time (tWR ) before another cycle can be initiated. The
OE
control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output bus has been enabled (
CE
and
OE
active) then
WE
will disable the outputs in tODW from its falling edge.
DS1244/DS1244P
5 of 20
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC fall as below the VPF, access to the device is inhibited. If VPF is less than VBAT, the device
power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF. If VPF is greater
than VBAT, the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below
VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
All control, data, and address signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of the chip enable, output enable, and write enable. Initially, a read cycle to any memory location using
the
CE
and
OE
control of the phantom clock starts the pattern recognition sequence by moving a pointer
to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
CE
and
WE
control of the SmartWatch. These 64 write cycles are used only to gain access to the
phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for
a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either
receive or transmit data on DQ0, depending on the level of the
OE
pin or the
WE
pin. Cycles to other
locations outside the memory block can be interleaved with
CE
cycles without interrupting the pattern
recognition sequence or data transfer sequence to the phantom clock.
DS1244/DS1244P
6 of 20
PHANTOM CLOCK REGISTER INFORMATION
The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary coded decimal (BCD) format. Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
Figure 1. PHANTOM CLOCK REGISTER DEFINITION
NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING
ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN 1 IN
1019. THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB.
DS1244/DS1244P
7 of 20
Figure 2. PHANTOM CLOCK REGISTER DEFINITION
AM/PM/12/24 MODE
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the 20-hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
RESET
and oscillator functions. Bit 4 controls the
RESET
(pin 1). When the
RESET
bit is set to logic 1, the
RESET
input pin is ignored. When the
RESET
bit is set to logic 0, a low input on the
RESET
pin will cause the phantom clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
DS1244/DS1244P
8 of 20
BATTERY LONGEVITY
The DS1244 has a lithium power source that is designed to provide energy for clock activity and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1244 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running
in the absence of VCC power. Each DS1244 is shipped from Maxim with its lithium energy source
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF , the
lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1244 will
be much longer than 10 years since no lithium battery energy is consumed when VCC is present.
See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm.
CLOCK ACCURACY (DIP MODULE)
The DS1244 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The clock is
calibrated at the factory by Maxim using special calibration nonvolatile tuning elements and does not
require additional calibration. For this reason, methods of field clock calibration are not available and not
necessary.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1244P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C.
DS1244/DS1244P
9 of 20
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground (5V product) ………………………..-0.3V to +6.0V
(3.3V product) ……………………..-0.3V to +4.6V
Storage Temperature Range
EDIP ………………………………………………………….……………………-40ºC to +85ºC
PowerCap …………………………………………………………………………-55ºC to +125ºC
Lead Temperature (soldering, 10 seconds) ……………………………………………………… +260ºC
Note: EDIP is wave or hand-soldered only.
Soldering Temperature (reflow, PowerCap) …………………………………………………… +260ºC
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect
reliability.
OPERATING RANGE
RANGE
TEMP RANGE
(NONCONDENSING)
VCC
Commercial
0°C to +70°C
3.3V ±10% or 5V ±10%
Industrial
-40°C to +85°C
3.3V ±10% or 5V ±10%
RECOMMENDED OPERATING CONDITIONS Over the operating range
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Logic 1
VCC = 5V ±10%
VIH
2.2 VCC + 0.3
V 11
VCC = 3.3V ±10% 2.0 VCC + 0.3
Input Logic 0
VCC = 5V ±15%
VIL
-0.3 0.8
V 11
VCC = 3.3V ±10% -0.3 0.6
DC ELECTRICAL CHARACTERISTICS Over the operating range (5V)
0BPARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current
IIL
-1.0
+1.0
µA
12
I/O Leakage Current
CE
≥
VIH ≤ VCC
IIO -1.0 +1.0 µA
Output Current at 2.4V IOH -1.0 mA
Output Current at 0.4V IOL 2.0 mA
Standby Current
CE
= 2.2V ICCS1 5 10 mA
Standby Current
CE
= VCC - 0.5V ICCS2 3.0 5.0 mA
Operating Current tCYC = 70ns ICC01 85 mA
Write Protection Voltage
V
PF
4.25
4.37
4.50
V
11
Battery Switchover Voltage VSO VBAT 7BV 11
DS1244/DS1244P
10 of 20
DC ELECTRICAL CHARACTERISTICS Over the operating range (3.3V)
1B
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Leakage Current
IIL
-1.0
+1.0
µA
12
I/O Leakage Current
CE
≥ VIH ≤ VCC
IIO -1.0 +1.0 µA
Output Current at 2.4V
IOH
-1.0
mA
Output Current at 0.4V
IOL
2.0
mA
Standby Current
CE
= 2.2V
I
CCS1
5 7 mA
Standby Current
CE
= VCC - 0.5V
ICCS2 2.0 3.0 mA
Operating Current tCYC = 70ns
ICC01
50
mA
Write Protection Voltage
VPF
2.80
2.86
2.97
V
11
Battery Switchover Voltage
VSO VBAT or VPF 8BV 11
CAPACITANCE (TA = +25°C)
2B
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
10
pF
Input/Output Capacitance
CI/O
5
10
pF
MEMORY AC ELECTRICAL CHARACTERISTICS Over the operating range (5V)
PARAMETER SYMBOL 9B
DS1244Y-70
3BUNITS 4BNOTES
10B
MIN
11B
MAX
Read Cycle Time
tRC
70
ns
Access Time
tACC
70
ns
OE
to Output Valid
t
OE
35
ns
CE
to Output Valid
t
CO
70
ns
OE
or
CE
to Output Active
t
COE
5
ns
5
Output High-Z from Deselection
tOD
25
ns
5
Output Hold from Address Change
tOH
5
ns
Write Cycle Time
tWC
70
ns
Write Pulse Width
tWP
50
ns
3
Address Setup Time
tAW
0
ns
Write Recovery Time
tWR
0
ns
Output High-Z from
WE
t
ODW
25
ns
5
Output Active from
WE
t
OEW
5
ns
5
Data Setup Time
tDS
30
ns
4
Data Hold Time from
WE
t
DH
5
ns
4
DS1244/DS1244P
11 of 20
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
Over the operating range (5V)
12B
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Read Cycle Time
tRC
65
ns
CE
Access Time
t
CO
55
ns
OE
Access Time
t
OE
55
ns
CE
to Output Low-Z
t
COE
5
ns
OE
to Output Low-Z
t
OEE
5
ns
CE
to Output High-Z
t
OD
25
ns
5
OE
to Output High-Z
t
ODO
25
ns
5
Read Recovery
tRR
10
ns
Write Cycle Time
tWC
65
ns
Write Pulse Width
tWP
55
ns
3
Write Recovery
tWR
10
ns
10
Data Setup Time
tDS
30
ns
4
Data Hold Time
tDH
0
ns
4
CE
Pulse Width
t
CW
60
ns
RESET
Pulse Width
t
RST
65
ns
POWER-DOWN/POWER-UP TIMING Over the operating range (5V)
13B
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE
at VIH before Power-Down
t
PD
0
µs
V
CC
Slew from V
PF(max)
to
VPF(min)(
CE
at VPF)
t
F
300
µs
VCC Slew from VPF(min) to VSO
tFB
10
µs
V
CC
Slew from V
PF(max)
to
VPF(min)(
CE
at VPF)
t
R
0
µs
CE
at VIH after Power-Up
t
REC
1.5
2.5
ms
(TA = +25°C)
5BPARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time
tDR 10 years 9
Warning: Under no circumstances are negative undershoots of any amplitude allowed when device
is in battery-backup mode.
DS1244/DS1244P
12 of 20
MEMORY AC ELECTRICAL CHARACTERISTICS
Over the operating range (3.3V)
PARAMETER SYMBOL
DS1244W-120
UNITS NOTES
MIN
14B
MAX
Read Cycle Time
tRC
120
ns
Access Time
tACC
120
ns
OE
to Output Valid
t
OE
60
ns
CE
to Output Valid
t
CO
120
ns
OE
or
CE
to Output Active
t
COE
5
ns
5
Output High-Z from Deselection
tOD
40
ns
5
Output Hold from Address Change
tOH
5
ns
Write Cycle Time
tWC
120
ns
Write Pulse Width
tWP
90
ns
3
Address Setup Time
tAW
0
ns
Write Recovery Time
tWR
20
ns
10
Output High-Z from
WE
t
ODW
40
ns
5
Output Active from
WE
t
OEW
5
ns
5
Data Setup Time
tDS
50
ns
4
Data Hold Time from
WE
t
DH
20
ns
4
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
Over the operating range (3.3V)
15B
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Read Cycle Time
tRC
120
ns
CE
Access Time
t
CO
100
ns
OE
Access Time
t
OE
100
ns
CE
to Output Low-Z
t
COE
5
ns
OE
to Output Low-Z
t
OEE
5
ns
CE
to Output High-Z
t
OD
40
ns
5
OE
to Output High-Z
t
ODO
40
ns
5
Read Recovery
tRR
20
ns
Write Cycle Time
tWC
120
ns
Write Pulse Width
tWP
100
ns
3
Write Recovery
tWR
20
ns
10
Data Setup Time
tDS
45
ns
4
Data Hold Time
tDH
0
ns
4
CE
Pulse Width
t
CW
105
ns
RESET
Pulse Width
t
RST
120
ns
DS1244/DS1244P
13 of 20
POWER-DOWN/POWER-UP TIMING Over the operating range (3.3V)
16B
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE
at VIH before Power-Down
t
PD
0
µs
V
CC
Slew from V
PF(MAX)
to
VPF(MIN)(
CE
at VIH)
t
F
300
µs
V
CC
Slew from V
PF(MAX)
to
VPF(MIN)(
CE
at VIH)
t
R
0
µs
CE
at VIH after Power-Up
t
REC
1.5
2.5
ms
(TA = +25°C)
6BPARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time
t
DR
10
years
9
Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when
device is in battery-backup mode.
DS1244/DS1244P
14 of 20
MEMORY READ CYCLE (Note 1)
MEMORY WRITE CYCLE 1 (Notes 2, 6, and 7)
DS1244/DS1244P
15 of 20
MEMORY WRITE CYCLE 2 (Notes 2 and 8)
RESET FOR PHANTOM CLOCK
READ CYCLE TO PHANTOM CLOCK
DS1244/DS1244P
16 of 20
WRITE CYCLE TO PHANTOM CLOCK
DS1244/DS1244P
17 of 20
POWER-DOWN/POWER-UP CONDITION, 5V
POWER-DOWN/POWER-UP CONDITION, 3.3V
DS1244/DS1244P
18 of 20
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1)
WE
is high for a read cycle.
2)
OE
= VIH or VIL. If
OE
= VIH during write cycle, the output buffers remain in a high-impedance
state.
3) tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4) tDH, tDS are measured from the earlier of
CE
or
WE
going high.
5) These parameters are sampled with a 50pF load and are not 100% tested.
6) If the
CE
low transition occurs simultaneously with or later than the
WE
low transition in Write
Cycle 1, the output buffers remain in a high-impedance state during this period.
7) If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in a high-impedance state during this period.
8) If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high-impedance state during this period.
9) The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator
running.
10) tWR is a function of the latter occurring edge of
WE
or
CE
.
11) Voltages are referenced to ground.
12)
RST
(Pin 1) has an internal pullup resistor.
13) RTC modules can be successfully processed through conventional wave-soldering techniques as long
as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-
solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not
used.
In addition, for the PowerCap:
1) Maxim recommends that PowerCap module bases experience one pass through solder reflow oriented
with the label side up (“live-bug”).
2) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than three
seconds.
– To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part,
apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove
solder.
DS1244/DS1244P
19 of 20
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-“ in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
32 EDIP MDT28+4 21-0245
34 PWRCP PC2+4 21-0246
DS1244/DS1244P
20 of 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
11/11
Updated the Features, Ordering Information, and Absolute Maximum
Ratings sections
1, 2, 9