54AC/74AC175 # 54ACT/74ACT175 Quad D Flip-Flop General Description Features The 'AC/'ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. Y Y Y Y Y Y Y Y Logic Symbols ICC reduced by 50% Edge-triggered D-type inputs Buffered positive edge-triggered clock Asynchronous common reset True and complement output Outputs source/sink 24 mA 'ACT175 has TTL-compatible inputs Standard Military Drawing (SMD) 'AC175: 5962-89552 'ACT175: 5962-89693 Connection Diagrams Pin Assignment for DIP, Flatpak and SOIC TL/F/9936 - 1 IEEE/IEC TL/F/9936 - 3 Pin Assignment for LCC TL/F/9936 - 2 TL/F/9936 - 4 Pin Names D0 - D3 CP MR Q0 - Q3 Q0 - Q3 Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs FACTTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9936 RRD-B30M75/Printed in U. S. A. 54AC/74AC175 # 54ACT/74ACT175 Quad D Flip-Flop March 1993 Functional Description Truth Table The 'AC/'ACT175 consists of four edge-triggered D flipflops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-toHIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The 'AC/'ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Inputs @ Outputs tn, MR e H @ tn a 1 Dn Qn Qn L H L H H L H e HIGH Voltage Level L e LOW Voltage Level tn e Bit Time before Clock Pulse tn a 1 e Bit Time after Clock Pulse Logic Diagram TL/F/9936 - 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0.5V VI e VCC a 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e b0.5V VO e VCC a 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP PDIP Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) b 0.5V to a 7.0V b 20 mA a 20 mA 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC Output Voltage (VO) Operating Temperature (TA) 74AC/ACT 54AC/ACT b 0.5V to VCC a 0.5V b 20 mA a 20 mA b 40 C to a 85 C b 55 C to a 125 C Minimum Input Edge Rate (DV/Dt) 'AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (DV/Dt) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V b 0.5V to VCC a 0.5V g 50 mA g 50 mA b 65 C to a 150 C 125 mV/ns 125 mV/ns 175 C 140 C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT TM circuits outside databook specifications. DC Characteristics for 'AC Family Devices Symbol Parameter VCC (V) 74AC 54AC 74AC TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Typ VIH VIL VOH IIN Conditions Guaranteed Limits Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT e 0.1V or VCC b 0.1V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT e 0.1V or VCC b 0.1V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.4 3.7 4.7 2.46 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 3.0 4.5 5.5 0.36 0.36 0.36 0.50 0.50 0.50 0.44 0.44 0.44 V 5.5 g 0.1 g 1.0 g 1.0 mA 3.0 4.5 5.5 VOL Units Maximum Low Level Output Voltage Maximum Input Leakage Current 3.0 4.5 5.5 0.002 0.001 0.001 *All outputs loaded; thresholds on input associated with output under test. 3 IOUT e b50 mA *VIN e VIL or VIH b 12 mA b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH 12 mA IOL 24 mA 24 mA VI e VCC, GND DC Characteristics for 'AC Family Devices (Continued) Symbol Parameter VCC (V) 74AC 54AC 74AC TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Typ Minimum Dynamic Output Current IOLD IOHD ICC Maximum Quiescent Supply Current Units Conditions Guaranteed Limits 5.5 50 75 mA VOLD e 1.65V Max 5.5 b 50 b 75 mA VOHD e 3.85V Min 80.0 40.0 mA VIN e VCC or GND 5.5 4.0 Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ ICC for 54AC 3.0V are guaranteed to be less than or equal to the respective limit @ 25 C is identical to 74AC @ @ 5.5V VCC. 25 C. DC Characteristics for 'ACT Family Devices 74ACT 54ACT 74ACT TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Parameter VCC (V) VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 V VOUT e 0.1V or VCC b 0.1V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOUT e 0.1V or VCC b 0.1V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 4.4 5.4 V 3.86 4.86 3.70 4.70 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 V 4.5 5.5 0.36 0.36 0.50 0.50 0.44 0.44 V g 0.1 g 1.0 g 1.0 mA VI e VCC, GND 1.6 1.5 mA VI e VCC b 2.1V 5.5 50 75 mA VOLD e 1.65V Max 5.5 b 50 b 75 mA VOHD e 3.85V Min 80.0 40.0 mA VIN e VCC or GND Symbol Typ 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 IIN Maximum Input Leakage Current 5.5 ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic Output Current IOHD ICC Maximum Quiescent Supply Current 0.001 0.001 4.0 *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. Note: ICC for 54ACT @ 25 C is identical to 74ACT @ Conditions Guaranteed Limits 0.6 5.5 Units 25 C. 4 IOUT e b50 mA *VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH 24 mA IOL 24 mA AC Electrical Characteristics Symbol Parameter VCC* (V) 74AC 54AC 74AC TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Max Min Max Min Typ fmax Maximum Clock Frequency 3.3 5.0 149 187 214 244 tPLH Propagation Delay CP to Qn or Qn 3.3 5.0 2.0 1.5 9.5 7.0 12.0 9.0 1.0 1.5 14.5 10.5 2.0 1.0 13.5 9.5 ns tPHL Propagation Delay CP to Qn or Qn 3.3 5.0 2.5 1.5 8.5 6.0 13.0 9.5 1.0 1.5 15.0 11.5 2.0 1.5 14.5 10.5 ns tPLH Propagation Delay MR to Qn 3.3 5.0 3.0 2.0 7.5 5.5 12.5 9.0 1.0 1.5 15.0 11.0 2.5 1.5 13.5 10.0 ns tPHL Propagation Delay MR to Qn 3.3 5.0 3.0 2.0 8.5 6.0 11.0 8.5 1.0 1.5 13.5 10.5 2.5 1.5 12.5 9.0 ns 95 95 Min Units Max 139 187 MHz *Voltage Range 3.3 is 3.3V g 0.3V Voltage Range 5.0 is 5.0V g 0.5V AC Operating Requirements 74AC 54AC 74AC TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Parameter VCC* (V) ts Setup Time, HIGH or LOW Dn to CP 3.3 5.0 2.0 1.0 4.5 3.0 5.0 3.5 4.5 3.0 ns th Hold Time, HIGH or LOW Dn to CP 3.3 5.0 1.0 1.0 1.0 1.0 2.0 2.5 1.0 1.0 ns tw CP Pulse Width HIGH or LOW 3.3 5.0 2.5 2.0 4.5 3.5 6.0 5.0 4.5 3.5 ns tw MR Pulse Width, LOW 3.3 5.0 2.5 2.0 4.5 3.5 5.5 5.0 5.0 3.5 ns trec Recovery Time MR to CP 3.3 5.0 b 2.0 b 1.0 0 0 1.5 1.5 0 0 ns Symbol Typ Units Guaranteed Minimum *Voltage Range 3.3 is 3.3V g 0.3V Voltage Range 5.0 is 5.0V g 0.5V 5 AC Electrical Characteristics Symbol VCC* (V) Parameter 74ACT 54ACT 74ACT TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Min Typ 5.0 175 236 Propagation Delay CP to Qn or Qn 5.0 2.0 6.0 10.0 1.5 11.5 1.5 11.0 ns tPHL Propagation Delay CP to Qn or Qn 5.0 2.0 7.0 11.0 1.5 12.5 1.5 12.0 ns tPLH Propagation Delay MR to Qn 5.0 2.0 6.0 9.5 1.5 11.5 1.5 10.5 ns tPHL Propagation Delay MR to Qn 5.0 2.0 5.5 9.5 1.5 11.0 1.5 10.5 ns fmax Maximum Clock Frequency tPLH Max Min Max 95 Min Units Max 145 MHz *Voltage Range 5.0 is 5.0V g 0.5V AC Operating Requirements Symbol Parameter VCC* (V) 74ACT 54ACT 74ACT TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Typ Units Guaranteed Minimum ts (H) ts (L) Setup Time Dn to CP 5.0 3.0 3.0 2.0 2.5 3.5 3.5 2.0 2.5 ns th Hold Time, HIGH or LOW Dn to CP 5.0 0 1.0 1.5 1.0 ns tw CP Pulse Width HIGH or LOW 5.0 4.0 3.0 5.0 3.5 ns tw MR Pulse Width, LOW 5.0 4.0 3.0 5.0 4.0 ns trec Recovery Time, MR to CP 5.0 0 0 1.5 0 ns *Voltage Range 5.0 is 5.0V g 0.5V Capacitance Parameter Typ Units Conditions CIN Symbol Input Capacitance 4.5 pF VCC e OPEN CPD Power Dissipation Capacitance 45.0 pF VCC e 5.0V 6 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74ACT 175 P Temperature Range Family 74AC e Commercial 54AC e Military 74ACT e Commercial TTL-Compatible 54ACT e Military TTL-Compatible C QR Special Variations X e Devices shipped in 13x reels QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing shipped in tubes Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) Temperature Range C e Commercial (b40 C to a 85 C) M e Military (b55 C to a 125 C) Physical Dimensions inches (millimeters) 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 7 Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 16-Lead Small Outline Integrated Circuit (S) NS Package Number M16A 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead Plastic Dual-In-Line Package (P) NS Package Number N16E 9 54AC/74AC175 # 54ACT/74ACT175 Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductores Do Brazil Ltda. Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.