NAU8223 Datasheet Rev 1.3 Page 1 of 23 July, 2012
NAU8223
3.1W Stereo Filter-Free Class-D Audio Amplifier
1 Description
The NAU8223 is a stereo high efficiency filter-free Class-D audio amplifier, which is capable of driving a 4Ω load with
up to 3.1W output power. This device provides chip enable pin with extremely low standby current and fast start-up time
of 3.4ms. It has five selectable gain settings (i.e. 0dB, 6dB, 12dB, 18dB and 24dB), which can be controlled by a single
gain pin.
The NAU8223 is ideal for the portable applications of battery drive, as it has advanced features like 87dB PSRR, 91%
efficiency, ultra low quiescent current (i.e. 2.1mA at 3.7V for 2 channels) and superior EMI performance. It has the
ability to configure the inputs in either single-ended or differential mode.
NAU8223 is available in Miniature QFN-20 package and TSSOP-20 package.
Key Features
Low Quiescent Current:
• 2.1mA at 3.7V for 2 channels
• 3.2mA at 5V for 2 channels
5 Selectable Gain Settings:
• 0dB / 6dB / 12dB / 18dB / 24dB
Powerful Stereo Class-D Amplifier:
• 2ch x 3.1W (4Ω @ 5V, 10% THD+N)
• 2ch x 1.26W (4Ω @ 3.7V, 1% THD+N)
• 2ch x 1.76W (8Ω @ 5V, 10% THD+N)
• 2ch x 0.76W (8Ω @ 3.7V, 1% THD+N)
Low Output Noise: 20 µV
RMS
@0dB gain
87dB PSRR @217Hz
Low Current Shutdown Mode
Click-and Pop Suppression
Applications
Notebooks / Tablet PCs
Personal Media Players / Portable TVs
MP3 Players
Portable Game Players
Digital Camcorders
Figure 1: NAU8223Block Diagram
NAU8223Datasheet Rev 1.4 Page 2 of 23 August, 2013
2 Pinout
2.1 NAU8223 QFN 20 (TOP VIEW)
NAU8223Datasheet Rev 1.4 Page 3 of 23 August, 2013
2.2 TSSOP 20 (TOP VIEW)
Part Number Dimension Package Package Material
NAU8223YG 4mm x 4mm QFN-20 Pb-Free
NAU8223WG 4.4mm x 6.5mm TSSOP-20 Pb-Free
NAU8223Datasheet Rev 1.4 Page 4 of 23 August, 2013
3 Pin Descriptions
QFN TSSOP Name Type Functionality
1 9 OUTRP Analog Output Right Channel Positive BTL Output
2 10 VDD Supply Power Supply
3 11 NC NC No Connect
4 12 EN Digital Input Chip Enable (High = Enable; Low = PD)
5 13 INR Analog Input Right Channel Negative Input
6 14 IPR Analog Input Right Channel Positive Input
7 15 GS Analog Input 5 Selectable Gain Setting (0dB / 6dB / 12dB / 18dB / 24dB)
8 16 VDD Supply Power Supply
9 17 VSS Supply Ground
10 18 IPL Analog Input Left Channel Positive Input
11 19 INL Analog Input Left Channel Negative Input
12 20 NC NC No Connect
13 1 NC NC No Connect
14 2 VDD Supply Power Supply
15 3 OUTLP Analog Output Left Channel Positive BTL Output
16 4 VSS Supply Ground
17 5 OUTLN Analog Output Left Channel Negative BTL Output
18 6 VDD Supply Power Supply
19 7 OUTRN Analog Output Right Channel Negative BTL Output
20 8 VSS Supply Ground
21 - Ex-Pad Analog Input Thermal Tab (must be connected to VSS, QFN-20 package, only)
Notes
1. Pins designated as NC (Not Internally Connected) should be left as no-connection
Table 1: NAU8223 Pin description
NAU8223Datasheet Rev 1.4 Page 5 of 23 August, 2013
4 Electrical Characteristics
Conditions: EN = VDD = 5V, VSS = 0V, Av = 12dB Z
L
= ∞, Bandwidth = 20Hz to 22kHz, T
A
= 25
o
C
Parameter Symbol Comments/Conditions Min Typ Max Units
Power Delivered
Output Power
(per channel) P
out
Z
L
= 4Ω + 33µH
THD + N = 10%
VDD = 5.0V 3.1
W
VDD = 3.7V 1.57
Z
L
= 4Ω + 33µH
THD + N = 1%
VDD = 5.0V 2.46
VDD = 3.7V 1.26
Z
L
= 8Ω + 68µH
THD + N = 10%
VDD = 5.0V 1.76
VDD = 3.7V 0.95
Z
L
= 8Ω + 68µH
THD + N = 1%
VDD = 5.0V 1.41
VDD = 3.7V 0.76
Parameter Symbol Comments/Conditions Min Typ Max Units
Chip Enable (EN)
Voltage Enable High V
EN_H
VDD = 2.5V to 5.5V 1.4 V
Voltage Enable Low V
EN_L
VDD = 2.5V to 5.5V 0.4 V
Input Leakage Current -1 +1 µA
Thermal and Current Protection
Thermal Shutdown Temperature
130
o
C
Thermal Shutdown Hysteresis
15
o
C
Short circuit Threshold I
LIMIT
2.1 A
Gain Setting
Voltage Gain A
V
Tie GS to VSS 24
dB
GS Connect VSS through
100k ± 5%
18
Tie GS pin to VDD 12
GS Connect VDD
through 100k ± 5%
6
Floating Node 0
Differential Input Resistance R
IN
A
V
= 24dB 35
kΩ
A
V
= 18dB 70
A
V
= 12dB 140
A
V
= 6dB 280
A
V
= 0dB 558
NAU8223Datasheet Rev 1.4 Page 6 of 23 August, 2013
Electrical Characteristics (continued)
Conditions: EN = VDD = 5V, VSS = 0V, Av = 12dB, Z
L
= ∞, Bandwidth = 20Hz to 22kHz, T
A
= 25
o
C
Parameter Symbol Comments/Conditions Min Typ Max Units
Normal Operation
Quiescent Current Consumption I
QUI
VDD = 3.7V 2.1 mA
VDD = 5V 3.17 mA
Shut Down Current I
OFF
EN = 0 0.1 µA
Oscillator Frequency f
OSC
300 kHz
Efficiency η 91 %
Start Up Time T
start
3.4 msec
Output Offset Voltage V
OS
±1 ±4 mV
Common Mode Rejection Ratio CMRR f
IN
= 1kHz 80 dB
Click-and-Pop Suppression Into Shutdown (Z
L
=8Ω)
A Weighted
-72 dBV
Power Supply Rejection Ratio
DC
PSRR
VDD = 2.5V to 5.5V 98 dB
AC
PSRR*
V
RIPPLE
=
0.2Vpp@217Hz**
V
RIPPLE
= 0.2Vpp@1KHz
V
RIPPLE
=
0.2Vpp@10KHz
87
74
54
dB
Channel Crosstalk f
IN
= 1kHz,
Z
L
= 8Ω + 68µH
-101 dB
*
Measured with 0.1uF capacitor on V
DD
and Battery supply ** Measured with 2.2uF input capacitor.
Parameter Symbol Comments/Conditions Min Typ Max Units
Noise Performance
Av = 0dB (A-weighted) 20
µV
RMS
Av = 6dB (A-weighted) 21
Av = 12dB (A-weighted) 27
Av = 18dB (A-weighted) 36
Av = 24dB (A-weighted) 52
The following setup is used to measure the above parameters
NAU8223Datasheet Rev 1.4 Page 7 of 23 August, 2013
Absolute Maximum Ratings
Condition Min Max Units
Analog supply -0.50 +5.50 V
Industrial operating temperature -40 +85 °C
Storage temperature range -65 +150 °C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may
adversely influence product reliability and result in failures not covered by warranty.
Operating Conditions
Condition Symbol Min Typical Max Units
Analog supply range VDD 2.50 3.7 5.50 V
Ground VSS 0 V
NAU8223Datasheet Rev 1.4 Page 8 of 23 August, 2013
6 Special Feature Description
The NAU8223 offers excellent quantity performance as high efficiency, high output power and low quiescent current. It
also provides the following special features.
6.1 Gain Setting
The NAU8223 has a GS pin, which can control five selectable gain settings (i.e. 0dB / 6dB / 12dB / 18dB / 24dB).
GS Pin Configuration Internal Gain (dB)
GS tie to VSS 24
GS connect to VSS through
100kΩ ± 5% resistor
18
GS tie to VDD 12
GS connect to VDD through
100kΩ ± 5% resistor
6
Floating (open node) 0
6.2 Device Protection
The NAU8223 includes device protection for three operating scenarios. They are
1. Thermal Overload
2. Short circuit
3. Supply under voltage
6.2.1 Thermal Overload Protection
When the device internal junction temperature reaches 130°C, the NAU8223 will disable the output drivers. When the
device cools down and a safe operating temperature of 115°C has been reached for at least about 47mSec, the output
drivers will be enabled again.
6.2.2 Short Circuit Protection
If a short circuit is detected on any of the pull-up or pull-down devices on the output drivers for at least 14uSec, the
output drivers will be disabled for 47mSec. The output drivers will then be enabled again and check for the short circuit.
If the short circuit is still present, the output drivers are disabled after 14uSec. This cycle will continue until the short
circuit is removed. The short circuit threshold is set at 2.1A.
6.2.3 Supply under Voltage Protection
If the supply voltage drops under 2.1V, the output drivers will be disabled while the NAU8223 control circuitry still
operates. This will avoid the battery supply to drag down too low before the host processor can safely shut down the
devices on the system. If the supply drops further below 1.0v the internal power on reset activated and puts the entire
device in power down state.
NAU8223Datasheet Rev 1.4 Page 9 of 23 August, 2013
6.3 Power up and Power down Control
When the supply voltage ramps up, the internal power on reset circuit gets triggered. At this time all internal circuits will
be set to power down state. The device can be enabled by setting the EN pin high. Upon setting the EN pin high, the
device will go through an internal power up sequence in order to minimize ‘pops’ on the speaker output. The complete
power up sequence will take about 3.4mSec. The device will power down in about 30uSec, when the EN pin is set low.
It is important to keep the input signal at zero amplitude or enable the mute condition in order to minimize the ‘pops’
when the EN pin is toggled.
.
NAU8223Datasheet Rev 1.4 Page 10 of 23 August, 2013
7 Typical Operating Characteristics
Conditions: EN = V
DD
= 5V, VSS = 0V, Av = 12dB, Z
L
= ∞, Bandwidth = 20Hz to 22kHz, T
A
= 25
o
C, unless otherwise
noted
0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 4
Efficiency(%)
Output Power(W)
Efficiency Vs Output Power
(VDD = 5.0V)
ZL=4Ω+33uH
ZL=8Ω+68uH
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2
Efficiency(%)
Output Power(W)
Efficiency Vs Output Power
(VDD = 3.7V)
ZL=4Ω+ 33uH
ZL=8Ω +68uH
0.001
0.01
0.1
1
20 200 2000 20000
THD+N(%)
Frequency(Hz)
THD+N vs Frequency
(VDD = 3.7V, ZL= 8Ω + 68uH)
Pout 0.2W
Pout 0.4W
0.001
0.01
0.1
1
20 200 2000 20000
THD+N(%)
Frequency(Hz)
THD+N vs Frequency
(VDD = 4.2V, ZL= 8Ω + 68uH)
Pout 0.2W
Pout 0.6W
NAU8223Datasheet Rev 1.4 Page 11 of 23 August, 2013
0.001
0.01
0.1
1
20 200 2000 20000
THD+N(%)
Frequency(Hz)
THD+N vs Frequency
(VDD = 5V, ZL= 8Ω + 68uH)
Pout 0.2W
Pout 1.2W
0.001
0.01
0.1
1
10
100
0 0.5 1 1.5
THD+N (%)
Pout (W)
THD+N vs Pout
(VDD = 3.7V, ZL = 8Ω + 68uH)
f 100Hz
f 1kHz
f 6kHz
0.001
0.01
0.1
1
10
100
0 0.5 1 1.5 2
THD+N (%)
Pout (W)
THD+N vs Pout
(VDD = 4.2V, ZL= 8Ω + 68uH)
f 100Hz
f 1kHz
f 6kHz
0.001
0.01
0.1
1
10
100
0 1 2 3
THD+N (%)
Pout (W)
THD+N vs Pout
(VDD = 5V, ZL=8Ω + 68uH)
f 100Hz
f 1kHz
f 6kHz
NAU8223Datasheet Rev 1.4 Page 12 of 23 August, 2013
0.001
0.01
0.1
1
20 200 2000 20000
THD+N(%)
Frequency(Hz)
THD+N vs Frequency
(VDD = 3.7V, ZL= 4Ω + 33uH)
Pout 0.2W
Pout 0.8W
0.001
0.01
0.1
1
20 200 2000 20000
THD+N(%)
Frequency(Hz)
THD+N vs Frequency
(VDD = 4.2V, ZL= 4Ω + 33uH)
Pout 0.2W
Pout 1W
0.001
0.01
0.1
1
20 200 2000 20000
THD+N(%)
Frequency (Hz)
THD+N vs Frequency
(VDD = 5V, ZL= 4Ω + 33uH)
Pout 1.5W
Pout 2W
0.001
0.01
0.1
1
10
100
0 1 2 3
THD+N (%)
Pout (W)
THD+N vs Pout
(VDD = 3.7V, ZL= 4Ω + 33uH)
f = 100Hz
f = 1kHz
f = 6kHz
NAU8223Datasheet Rev 1.4 Page 13 of 23 August, 2013
0.001
0.01
0.1
1
10
100
0 1 2 3
THD+N (%)
Pout (W)
THD+N vs Pout
(VDD = 4.2V, ZL= 4Ω + 33uH)
f = 100Hz
f = 1kHz
f = 6kHz
0.001
0.01
0.1
1
10
100
01234
THD+N (%)
Pout (W)
THD+N vs Pout
(VDD = 5V, ZL= 4Ω + 33uH)
f = 100Hz
f = 1kHz
f = 6kHz
-10
-5
0
5
10
15
20
25
30
20 200 2000 20000
Gain (dB)
Frequency (Hz)
Gain vs Frequency
Gain 0dB
Gain 6dB
Gain 12dB
Gain 18dB
Gain 24dB
-120
-100
-80
-60
-40
-20
0
20 200 2000 20000
Level (dB)
Frequency (Hz)
Crosstalk vs Frequency
Left to Right
Right to Left
NAU8223Datasheet Rev 1.4 Page 14 of 23 August, 2013
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
2.5 3.5 4.5 5.5 6.5
PSRR (dB)
Supply Voltage (V)
AC PSRR vs Supply Voltage
PSRR @Gain 0dB, 1KHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
20 200 2000 20000
PSRR (dB)
Frequency (Hz)
AC PSRR vs Frequency
PSRR @ Gain 0dB
NAU8223Datasheet Rev 1.4 Page 15 of 23 August, 2013
0
0.5
1
1.5
2
2.5
3
3.5
2.5 3.5 4.5 5.5
Supply Current(mA)
Supply Voltage (V)
SupplyVoltage vs SupplyCurrent
NAU8223Datasheet Rev 1.4 Page 16 of 23 August, 2013
8 Application Information
8.1 Application diagram
VSS
OUTLP
VDD
IPL
VDD
EN
VSS
VDD
NC
GS
VDD
VSS
NC
INR
IPR
OUTLN
NC
OUTRN
OUTRP
2
3
4
5
6
7
8
1
10
15
14
13
12
11
16
9
20
19
18
17
INL
NAU8223
Stereo Class D
QFN 20-Pin
P.S. GS Pin – The 100kΩ resistors are optional. GS can be floating for internal gain setting = 0dB. Please refer Section
2.1 (Gain Setting) for the detailed explanation.
NAU8223Datasheet Rev 1.4 Page 17 of 23 August, 2013
8.2 Component selection
Coupling Capacitors
An ac coupling capacitor (Cin) is used to block the dc content from the input source. The input resistance of the amplifier
(Rin) together with the Cin will act as a high pass filter. So depending on the required cut off frequency the Cin can be
calculated by using the following formula
Where is the desired cut off frequency of the High pass filter.
Input
Output
Cin
Rin(Input Resistance)
Amplifier
Bypass Capacitors
Bypass capacitors are required to remove the ac ripple on the VDD pins. The value of these capacitors depends on the
length of the VDD trace. In most cases, 10uF and 0.1uF are enough to get the good performance.
8.3 Layout considerations
The NAU8223 QFN package uses an exposed pad on the bottom side of the package to dissipate excess power from the
output drivers. This pad must be soldered carefully to the PCB for proper operation of the NAU8223. This pad is
internally connected to Vss. A typical layout is shown below.
NAU8223Datasheet Rev 1.4 Page 18 of 23 August, 2013
The PCB has to be designed in such a manner that it should have nine vias in 3x3 grid under NAU8223. The vias should
have hole size of 12mil and a spacing of 30mils. The pad size of the vias is 24mils. The vias on the top side of the board
should be connected with a copper pour that has an area of 2mm x 2mm, centered underneath the NAU8223. The nine
vias should connect to copper pour area on the bottom of the PCB. It is preferred to pour the complete bottom side of the
board with Vss.
Also good PCB layout and grounding techniques are essential to get the good audio performance. It is better to use low
resistance traces as these devices are driving low impedance loads. The resistance of the traces has a significant effect on
the output power delivered to the load. In order to dissipate more heat, use wide traces for the power and ground lines.
8.4 Class D without filter
The NAU8223 is designed for use without any filter on the output line. That means the outputs can be directly connected
to the speaker in the simplest configuration. This type of filter less design is suitable for portable applications where the
speaker is very close to the amplifier. In other words, this is preferable in applications where the length of the traces
between the speaker and amplifier is short. The following diagram shows this simple configuration.
NAU8223 outputs connected to speaker without filter circuit
8.5 Class D with filter
In some applications, the shorter trace lengths are not possible because of speaker size limitations and other layout
reasons. In these applications, the long traces will cause EMI issues. There are two types of filter circuits available to
reduce the EMI effects. These are ferrite bead and LC filters.
Ferrite Bead filter
The ferrite bead filters are used to reduce the high frequency emissions. The typical circuit diagram is shown in the
figure.
NAU8223 outputs connected to speaker with Ferrite Bead filter
NAU8223Datasheet Rev 1.4 Page 19 of 23 August, 2013
The characteristic of ferrite bead is such that it offers higher impedance at high frequencies. For better EMI performance
select ferrite bead which offers highest impedance at high frequencies, so that it will attenuate the signals at higher
frequencies. Usually the ferrite beads have low impedance in the audio range, so it will act as a pass through filter in the
audio frequency range.
LC filter
The LC filter is used to suppress the low frequency emissions. The following diagram shows the NAU8223 outputs
connected to the speaker with LC filter circuit. R
L
is the resistance of the speaker coil.
NAU8223 outputs connected to speaker with LC filter
Standard Low pass LCR filter
The following are the equations for the critically damped (ζ = 0.707) standard low pass LCR filter
2
√
is the cutoff frequency
0.707 1
2 ∗ √
The L and C values for differential configuration can be calculated by duplicating the single ended configuration values
and substituting R
L
= 2R.
NAU8223Datasheet Rev 1.4 Page 20 of 23 August, 2013
8.6 NAU8223 EMI performance
The NAU8223 includes a spread spectrum oscillator for reduced EMI. The PWM oscillator frequency typically sweeps
in a range of 300 kHz +/- 15 kHz in order to spread the energy of the PWM pulses over a larger frequency band. In
addition, slew rate control on the output drivers allows the application of ‘filter less’ loads, while suppressing EMI at
high frequencies. The below graph shows the EMI performance of NAU8223 with ferrite beads and speaker cable length
of 30cm.
NAU8223Datasheet Rev 1.4 Page 21 of 23 August, 2013
9 Package Dimensions
9.1 QFN20L 4X4 MM^2, Pitch:0.50 MM
TOP VI EW BOTTOM VI EW
11
620
15
10
15
1616
15 11
10
6
51
20
NAU8223Datasheet Rev 1.4 Page 22 of 23 August, 2013
9.2 TSSOP20L 4.4X6.5 MM^2, Pitch:0.65 MM
NAU8223Datasheet Rev 1.4 Page 23 of 23 August, 2013
10 Ordering Information
Nuvoton Part Number Description
Version History
VERSION DATE PAGE DESCRIPTION
Rev1.0 March, 2012 P.8, P.9 Preliminary Revision
Updated typical characteristics
Rev1.1 March, 2012 P.2, P.10 Updated Pin No.
Added application diagrams
Rev1.2 May, 2012 NA Updated Electrical Characteristics
Rev1.3 July, 2012 P.4, P.5,
P.10-P.18
Added Application information section
Added/Modified Typical operating Characteristics
Updated Electrical Characteristics
Rev1.4 August, 2013 P.4, P.5,
P.22,P.23 Added TSSOP20 Package information section
Table 1: Version History
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment
intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could
result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Nuvoton for any damages resulting from such improper use or sales.
Package Type:
Y = 20-Pin QFN Package
N
AU8223 _G
Package Material:
G = Pb-free Package
W = 20-Pin TSSOP Package
