SLCS002D − JUNE 1983 − REVISED AUGUST 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DOperates From a Single 5-V Supply
D0-V to 5.5-V Common-Mode Input Voltage
Range
DSelf-Biased Inputs
DComplementary 3-State Outputs
DEnable Capability
DHysteresis ...5 mV Typ
DResponse Times . . . 25 ns Typ
description/ordering information
The TL712 is a high-speed comparator fabricated with bipolar Schottky process technology. The circuit has
differential analog inputs and complementary 3-state TTL-compatible logic outputs with symmetrical switching
characteristics. When the output enable (OE) is low, both outputs are in the high-impedance state. This device
operates from a single 5-V supply and is useful as a disk memory read-chain data comparator.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP (P) Tube of 50 TL712CP TL712CP
SOIC (D)
Tube of 75 TL712CD
TL712C
0°C to 70°C
SOIC (D) Reel of 2500 TL712CDR TL712C
0°C to 70°CSOP (PS) Reel of 2000 TL712CPSR T712
TSSOP (PW)
Tube of 150 TL712CPW
T712
TSSOP (PW) Reel of 2000 TL712CPWR T712
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
symbol (positive logic)
OE
IN−
IN+
4
2
3
7
6
OUT−
OUT+
Copyright 2003, Texas Instruments Incorporated
! "#
" $ %
"" &'# " ( " !' !"
( !! #
1
2
3
4
8
7
6
5
NC
IN−
IN+
OE
VCC
OUT−
OUT+
GND
D, P, PS, OR PW PACKAGE
(TOP VIEW)
NC−No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLCS002D − JUNE 1983 − REVISED AUGUST 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
EQUIVALENT OF EACH
DIFFERENTIAL INPUT
VCC
Input
4 kΩ
Nom 960 Ω
Nom
960 Ω
Nom
VCC 8.3 kΩ
Nom
OE
VCC
85 Ω
Nom
Output
EQUIVALENT OF EACH ENABLE INPUT TYPICAL OF ALL OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI, any differential input ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output enable voltage 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-level output current, IOL 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 3 and 4): D package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
P package 85°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS package 95°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” secti on of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground.
2. Differential voltage values are at IN+ with respect to IN−.
3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
SLCS002D − JUNE 1983 − REVISED AUGUST 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIC Common-mode input voltage 0 5.5 V
IOH High-level output current −1 mA
IOL Low-level output current 16 mA
TAOperating free-air temperature 0 70 °C
electrical characteristics at VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTThreshold voltage (VT+ and VT−) VICR = 0 to 5 V −100†100 mV
Vhys Hysteresis (VT+ − VT−) 5 mV
VOH High-level output voltage VID = 100 mV, IOH = −1 mA 2.7 3.5 V
VOL Low-level output voltage VID = − 100 mV, IOL = 16 mA 0.4 0.5 V
IOZ Off-state output current VO = 2.4 V −20 µA
IIEnable current VI = 5.5 V 100 µA
IIH High-level enable current VIH = 2.7 V 20 µA
IIL Low-level enable current VIL = 0.4 V −360 µA
riDifferential input resistance 4 kΩ
roOutput resistance 100 Ω
IOS Short-circuit output current −15 −85 mA
ICC Supply current VID = 0, No load 17 20 mA
†The algebraic convention, where the more-negative limit is designated as minimum, is used in this data sheet for input threshold voltage levels
only.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
tPLH Propagation delay time, low-to-high-level output
TTL load,
See Note 5 and Figure 1
25 ns
tPHL Propagation delay time, high-to-low-level output
TTL load,
See Note 5 and Figure 1
25 ns
NOTE 5: The response time specified is for a 100-mV input step with 5-mV overdrive (105 mV total) and is the interval between the input step
function and the instant when the output crosses 2.5 V.
SLCS002D − JUNE 1983 − REVISED AUGUST 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
5 V
Output
2 kΩ
NOTE A: All diodes are 1N4148 or equivalent.
Figure 1. TTL Output Load Circuit
TYPICAL CHARACTERISTICS
5
4
3
2
1
0
Differential
Input Voltage
010203040
t − Time − ns
OUTPUT RESPONSE FOR VARIOUS
INPUT OVERDRIVE VOLTAGES
VO− Output Voltage − V
VCC = 5 V
TTL Load
TA = 25°C
100 mV
50 mV
20 mV 5 mV
100 mV + Overdrive
5152535
Figure 2
Differential
Input Voltage
5
4
3
2
1
0010203040
t − Time − ns
OUTPUT RESPONSE FOR VARIOUS
INPUT OVERDRIVE VOLTAGES
VCC = 5 V
TTL Load
TA = 25°C
100 mV
50 mV
20 mV 5 mV
100 mV + Overdrive
VO− Output Voltage − V
5152535
Figure 3
SLCS002D − JUNE 1983 − REVISED AUGUST 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VO
50 Ω
50 Ω
VIC
4
3
2
1
0
0 40 80 120 140
1.7
1.65
1.6
1.55
1.5
t − Time − ns
COMMON-MODE
PULSE RESPONSE
VO− Output Voltage − V VIC − Common-Mode
Input Voltage
VCC = 5 V
TA = 25°C
20 60 100 160
Figure 4
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TL712CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CDE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL712CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TL712CPSR ACTIVE SO PS 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CPSRE4 ACTIVE SO PS 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CPW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CPWE4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CPWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TL712CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 1
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TL712CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL712CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TL712CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL712CDR SOIC D 8 2500 340.5 338.1 20.6
TL712CPSR SO PS 8 2000 346.0 346.0 33.0
TL712CPWR TSSOP PW 8 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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