HM621100A Series 1048576-word x 1-bit High Speed CMOS Static RAM The Hitachi HM621100A is a high speed 1M Static RAM organized as 1048576-word x 1-bit. It realizes high speed access time (20/25/35 ns) and low power consumption, employing CMOS process technology and high speed circuit designing technology. It is most advantageous for the field where high speed and high density memory is required, such as the cache memory for main frame or 32-bit MPU. The HM621100A, packaged in a 400-mil plastic SOJ is available for high density mounting. Features * Single 5 V supply and high density 28-pin package (DIP and SOJ) * High speed Access time: 20/25/35 ns (max) * Low power dissipation Active mode: 350 mW (typ) Standby mode: 100 W (typ) * Completely static memory required No clock or timing strobe required * Equal access and cycle time * Directly TTL compatible All inputs and outputs Ordering Information Type No. Access time Package --------------------------------------------- HM621100AP-20 20 ns 400-mil --------------------------------- 28-pin HM621100AP-25 25 ns plastic DIP --------------------------------- (DP-28C) HM621100AP-35 35 ns --------------------------------- HM621100ALP-20 20 ns --------------------------------- HM621100ALP-25 25 ns --------------------------------- HM621100ALP-35 35 ns --------------------------------------------- HM621100AJP-20 20 ns 400-mil --------------------------------- 28-pin HM621100AJP-25 25 ns plastic SOJ --------------------------------- (CP-28D) HM621100AJP-35 35 ns --------------------------------- HM621100ALJP-20 20 ns --------------------------------- HM621100ALJP-25 25 ns --------------------------------- HM621100ALJP-35 35 ns --------------------------------------------- 1 HM621100A Series HM621100A Series Pin Arrangement Pin Description A0 1 28 VCC A1 2 27 A19 A2 3 26 A18 A3 4 25 A17 A4 5 24 A16 A5 6 23 A15 NC 7 22 A14 A6 8 21 NC A7 9 20 A13 A8 10 19 A12 A9 11 18 A11 Q 12 17 A10 WE VSS 13 16 D 14 15 CS Pin Name Function --------------------------------------------- A0 - A19 Address --------------------------------------------- D Input --------------------------------------------- Q Output --------------------------------------------- CS Chip select --------------------------------------------- WE Write enable --------------------------------------------- VCC Power supply --------------------------------------------- VSS Ground --------------------------------------------- (Top view) Block Diagram A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC Row decoder Memory array 512 x 2048 VSS Din Column I/O Dout Column decoder CS WE 2 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A0 HM621100A Series HM621100A Series Function Table CS WE Mode VCC current Output pin Ref. cycle ----------------------------------------------------------------------------------------------- H X Not selected ISB, ISB1 High-Z -- ----------------------------------------------------------------------------------------------- L H Read ICC Dout Read cycle ----------------------------------------------------------------------------------------------- L L Write ICC High-Z Write cycle ----------------------------------------------------------------------------------------------- Note: X : H or L Absolute Maximum Ratings Parameter Symbol Value Unit ----------------------------------------------------------------------------------------------- Voltage on any pin relative to VSS Vin -0.5*1 to +7.0 V ----------------------------------------------------------------------------------------------- Power dissipation PT 1.0 W ----------------------------------------------------------------------------------------------- Operating temperature range Topr 0 to +70 C ----------------------------------------------------------------------------------------------- Storage temperature range Tstg -55 to +125 C ----------------------------------------------------------------------------------------------- Storage temperature range under bias Tbias -10 to +85 C ----------------------------------------------------------------------------------------------- Note: 1. Vin min = -2.0 V for pulse width 10 ns. Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit ----------------------------------------------------------------------------------------------- Supply voltage VCC 4.5 5.0 5.5 V --------------------------------------------------------------- VSS 0 0 0 V ----------------------------------------------------------------------------------------------- Input high (logic 1) voltage VIH 2.2 -- 6.0 V ----------------------------------------------------------------------------------------------- Input low (logic 0) voltage VIL -0.5*1 -- 0.8 V ----------------------------------------------------------------------------------------------- Note: 1. VIL min = -2.0 V for pulse width 10 ns. 3 HM621100A Series HM621100A Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM621100A-20 HM621100A-25/35 ----------------- ------------------ Parameter Symbol Min Typ*1 Max Min Typ*1 Max Unit Test conditions ----------------------------------------------------------------------------------------------- Input leakage |ILI| -- -- 2.0 -- -- 2.0 A VCC = max current Vin = VSS to VCC ----------------------------------------------------------------------------------------------- Output leakage |ILO| -- -- 2.0 -- -- 2.0 A CS = VIH current VI/O = VSS to VCC ----------------------------------------------------------------------------------------------- Operating power ICC -- -- 150 -- -- 120 mA CS = VIL, II/O = 0 mA, supply current min cycle ----------------------------------------------------------------------------------------------- Standby power ISB -- -- 60 -- -- 40 mA CS = VIH, min cycle supply current ----------------------------------------------------------------------------------------------- Standby power ISB1*2 -- 0.02 2.0 -- 0.02 2.0 mA CS VCC -0.2 V supply current (1) ---------------------------------------------------- 0 V Vin 0.2 V or ISB1*3 -- -- 100 -- -- 100 A Vin VCC -0.2 V ----------------------------------------------------------------------------------------------- Output low voltage VOL -- -- 0.4 -- -- 0.4 V IOL = 8 mA ----------------------------------------------------------------------------------------------- Output high voltage VOH 2.4 -- -- 2.4 -- -- V IOH = -4 mA ----------------------------------------------------------------------------------------------- Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. P and JP version 3. LP and LJP version Capacitance (Ta = 25C, f = 1 MHz) Parameter Symbol Min Max Unit Test conditions ----------------------------------------------------------------------------------------------- Input capacitance Cin -- 5*2 pF Vin = 0 V ---------- 6*3 ----------------------------------------------------------------------------------------------- Output capacitance Cout -- 8 pF Vout = 0 V ----------------------------------------------------------------------------------------------- Note: 1. This parameter is sampled and not 100% tested. 2. SOJ package 3. DIP package 4 HM621100A Series HM621100A Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.) Test Conditions * Input pulse levels: 0 V to 3.0 V * Input rise and fall times: 4 ns * Input timing reference levels: 1.5 V +5V +5V 480 480 Dout 255 * Output timing reference levels: 1.5 V * Output load: See figures Dout 30 pF *1 Output load (A) Note: 1. Including scope and jig 255 5 pF *1 Output load (B) (For tHZ , tLZ, tWZ and tOW) Read Cycle HM621100A-20 HM621100A-25 HM621100A-35 ------------ ------------ ------------ Parameter Symbol Min Max Min Max Min Max Unit ----------------------------------------------------------------------------------------------- Read cycle time tRC 20 -- 25 -- 35 -- ns ----------------------------------------------------------------------------------------------- Address access time tAA -- 20 -- 25 -- 35 ns ----------------------------------------------------------------------------------------------- Chip select access time tACS -- 20 -- 25 -- 35 ns ----------------------------------------------------------------------------------------------- Chip selection to output in low-Z tLZ*1 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Chip deselection to output in high-Z tHZ*1 0 10 0 12 0 15 ns ----------------------------------------------------------------------------------------------- Output hold from address change tOH 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Chip selection to power up time tPU 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Chip deselection to power down time tPD -- 12 -- 15 -- 25 ns ----------------------------------------------------------------------------------------------- 5 HM621100A Series HM621100A Series Read Timing Waveform (1) *2, *3 tRC Address tAA tOH tOH Dout Valid Data Read Timing Waveform (2) *2, *4 tRC CS tHZ tACS tLZ Dout Valid Data High-Z High-Z tPD tPU VCCsupply Current ICC 50% 50% ISB Notes: 1. Transition is measured 200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. 2. WE is high for read cycle. 3. Device is continuously selected, CS = VIL. 4. Address valid prior to or coincident with CS transition low. 6 HM621100A Series HM621100A Series Write Cycle HM621100A-20 HM621100A-25 HM621100A-35 ------------- ------------- ------------- Parameter Symbol Min Max Min Max Min Max Unit ----------------------------------------------------------------------------------------------- Write cycle time tWC 20 -- 25 -- 35 -- ns ----------------------------------------------------------------------------------------------- Chip selection to end of write tCW 15 -- 17 -- 25 -- ns ----------------------------------------------------------------------------------------------- Address valid to end of write tAW 16 -- 20 -- 30 -- ns ----------------------------------------------------------------------------------------------- Address setup time tAS 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Write pulse width tWP 15 -- 17 -- 25 -- ns ----------------------------------------------------------------------------------------------- Write recovery time tWR 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Write to output in high-Z tWZ*1 0 12 0 15 0 15 ns ----------------------------------------------------------------------------------------------- Data to write time overlap tDW 12 -- 15 -- 20 -- ns ----------------------------------------------------------------------------------------------- Data hold from write time tDH 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Output active from end of write tOW*1 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Write Timing Waveform (1) (WE Controlled) tWC Address tCW CS tAW tAS tWR *3 tWP *2 WE tDW Valid Data Din tWZ Dout tDH tOW tOH *5 High-Z 7 HM621100A Series HM621100A Series Write Timing Waveform (2) (CS Controlled) tWC Address tAW tAS tWR *3 tCW CS tWP *2 WE tDW Din tDH Valid Data High-Z *4 Dout Notes: 1. Transition is measured 200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. 2. A write occurs during the overlap of a low CS and a low WE. 3. tWR is measured from the earlier of CS or WE going high to the end of write cycle. 4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state. 5. Dout is the same phase of write data of this write cycle, if tWR is long enough. 8 HM621100A Series HM621100A Series Low VCC Data Retention Characteristics (Ta = 0 to +70C) This characteristics is guaranteed only for L-version. Parameter Symbol Min Typ Max Unit Test conditions ----------------------------------------------------------------------------------------------- VCC for data retention VDR 2.0 -- -- V CS VCC -0.2 V, ------------------------------------------------------------------------ Vin VCC -0.2 V or Data retention current ICCDR -- 2 50*1 A 0 V Vin 0.2 V ------------------------------------------------------------------------ Chip deselect to data retention time tCDR 0 -- -- ns ------------------------------------------------------------------------ Operation recovery time tR 5 -- -- ms ----------------------------------------------------------------------------------------------- Note: 1. VCC = 3.0 V Low VCC Data Retention Timing Waveform Data retention mode VCC 4.5 V tR tCDR 2.2 V VDR CS VCC-0.2 V CS 0V 9 HM621100A Series 1.3 Ta=25C 1.2 1.1 1.0 0.9 0.8 0.7 4.5 4.75 5.0 5.25 High Level Input Voltage V IH (Normalized) Low Level Input Voltage V IL (Normalized) HM621100A Series 1.3 Ta=25C 1.2 1.1 1.0 0.9 0.8 0.7 4.5 5.5 Ta=25C Vcc=5V 1.2 1.0 0.8 0.6 0.4 1 2 3 4 5 High Level Output Voltage VOH (V) High Level Output Current vs. High Level Output Voltage 10 5.25 5.5 High Level Input Voltage vs. Supply Voltage Low Level Output Current I OL (Normalized) High Level Output Current IOH (Normalized) Low Level Input Voltage vs. Supply Voltage 1.4 5.0 Supply Voltage Vcc (V) Supply Voltage Vcc (V) 1.6 4.75 1.6 Ta=25C Vcc=5V 1.4 1.2 1.0 0.8 0.6 0.4 0 0.2 0.4 0.6 0.8 Low Level Output Voltage VOL (V) Low Level Output Current vs. Low Level Output Voltage HM621100A Series HM621100A Series 10 -4 Standby Current ISB1 (A) 10 -5 10 -6 10 -7 0 20 40 60 Standby Current ISB1 (Normalized) 1.4 Vcc=3V CS=2.8V 1.2 1.0 0.8 0.6 0.4 0.2 80 Ta=25C CS=Vcc-0.2V 2 Ambient Temperature Ta (C) 3 4 Supply Voltage Vcc (V) Standby Current vs. Supply Voltage Standby Current vs. Ambient Temperature 1.6 1.6 Ta=25C Vcc=5.0V 1.4 Supply Current Icc (Normalized) Supply Current Icc (Normalized) 1.4 1.2 1.0 0.8 0.6 0.4 4.5 6 5 4.75 5.0 5.25 Supply Voltage Vcc (V) Supply Current vs. Supply Voltage 5.5 1.2 1.0 0.8 0.6 0.4 0 20 40 60 80 Ambient Temperature Ta (C) Supply Current vs. Ambient Temperature 11 HM621100A Series HM621100A Series 1.8 1.3 1.2 Access Time t AA ,tACS (Normalized) Access Time t AA ,t ACS (Normalized) Ta=25C 1.1 1.0 0.9 0.8 0.7 4.5 4.75 5.0 5.25 1.6 1.4 1.2 1.0 0.8 0.6 5.5 0 50 1.2 1.1 1.0 0.9 0.8 20 40 60 80 Ambient Temperature Ta (C) Access Time vs. Ambient Temperature 12 1.4 Vcc=5.0V Supply Current Icc (Normalized) Access Time tAA ,tACS (Normalized) 1.3 0 150 200 Access Time vs. Load Capacitance Access Time vs. Supply Voltage 0.7 100 Load Capacitance C L (pF) Supply Voltage Vcc (V) 100 50 33 25 T (ns) 20 10 20 30 40 50 1.2 1.0 0.8 0.6 0.4 0.2 0 Frequency f (MHz) Supply Current vs. Frequency