Filterless, High Efficiency,
Mono 3 W Class-D Audio Amplifier
Data Sheet
SSM2375
Rev. A Document Feedback
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FEATURES
Filterless Class-D amplifier with spread-spectrum
Σ-Δ modulation
3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion (THD + N)
93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>100 dB signal-to-noise ratio (SNR)
High PSSR at 217 Hz: 80 dB
Flexible gain adjustment pin: 0 dB to 12 dB in 3 dB steps
Fixed input impedance: 80 kΩ
User-selectable ultralow EMI emissions mode
Single-supply operation from 2.5 V to 5.5 V
20 nA shutdown current
Short-circuit and thermal protection with autorecovery
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
APPLICATIONS
Mobile phones
MP3 players
Portable electronics
GENERAL DESCRIPTION
The SSM2375 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with <1% THD + N driving a 3 Ω load from a 5.0 V supply.
The SSM2375 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modulation
continues to provide high efficiency even at low output power.
The SSM2375 operates with 93% efficiency at 1.4 W into 8 Ω
or with 85% efficiency at 3 W into 3 Ω from a 5.0 V supply and
has an SNR of >100 dB.
Spread-spectrum pulse density modulation (PDM) is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures. The inherent randomized nature of
spread-spectrum PDM eliminates the clock intermodulation
(beating effect) of several amplifiers in close proximity.
The SSM2375 includes an optional modulation select pin
(ultralow EMI emissions mode) that significantly reduces the
radiated emissions at the Class-D outputs, particularly above
100 MHz. In ultralow EMI emissions mode, the SSM2375
can pass FCC Class B radiated emission testing with 50 cm,
unshielded speaker cable without any external filtering.
The device also includes a highly flexible gain select pin that
allows the user to select a gain of 0 dB, 3 dB, 6 dB, 9 dB, or
12 dB. The gain selection feature improves gain matching
between multiple SSM2375 devices within a single application
as compared to using external resistors to set the gain.
The SSM2375 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying
a logic low to the SD pin.
The device also includes pop-and-click suppression circuitry.
This suppression circuitry minimizes voltage glitches at the
output during turn-on and turn-off, reducing audible noise
on activation and deactivation.
Other features that simplify system-level integration of the
SSM2375 include input low-pass filtering to suppress out-of-band
DAC noise interference to the PDM modulator and fixed-input
impedance to simplify component selection across multiple
platform production builds.
The SSM2375 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a halide-free, 9-ball,
1.5 mm × 1.5 mm wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
FET
DRIVER
MODULATOR
(Σ-Δ)
0.1µF
VDD
OUT+
OUT–
BIAS EDGE
IN+
POWER SUPPLY
2.5V TO 5.5V
IN–
INTERNAL
OSCILLATOR EDGE
CONTROL GND
10µF
22nF
22nF
R
GAIN
SHUTDOWN SD
GAIN SELECT
IN–
IN+
SSM2375
EMISSION
CONTROL
GAIN
CONTROL
GAIN
GAIN = 0d B, 3d B, 6d B, 9dB, O R 12dB
09011-001
Figure 1.
SSM2375 Data Sheet
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Typical Application Circuits .......................................................... 12
Theory of Operation ...................................................................... 13
Overview ..................................................................................... 13
Gain Selection ............................................................................. 13
Pop-and-Click Suppression ...................................................... 13
EMI Noise .................................................................................... 13
Output Modulation Description .............................................. 13
Layout .......................................................................................... 14
Input Capacitor Selection .......................................................... 14
Power Supply Decoupling ......................................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Changes to Figure 33 and Figure 34 ............................................. 12
Changes to Gain Selection Section and Table 5 ......................... 13
Updated Outline Dimensions ....................................................... 15
9/10—Revision 0: Initial Version
Data Sheet SSM2375
Rev. A | Page 3 of 16
SPECIFICATIONS
VDD = 5.0 V, TA = 25°C, RL = 8 Ω +33 µH, EDGE = GND, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power PO f = 1 kHz, 20 kHz BW
RL = 8 Ω, THD = 1%, VDD = 5.0 V 1.42 W
RL = 8 Ω, THD = 1%, VDD = 3.6 V 0.72 W
RL = 8 Ω, THD = 1%, VDD = 2.5 V 0.33 W
R
L
= 8 Ω, THD = 10%, V
DD
= 5.0 V
1.77
W
R
L
= 8 Ω, THD = 10%, V
DD
= 3.6 V
0.91
W
RL = 8 Ω, THD = 10%, VDD = 2.5 V 0.42 W
RL = 4 Ω, THD = 1%, VDD = 5.0 V 2.52 W
RL = 4 Ω, THD = 1%, VDD = 3.6 V 1.28 W
RL = 4 Ω, THD = 1%, VDD = 2.5 V 0.56 W
RL = 4 Ω, THD = 10%, VDD = 5.0 V 3.171 W
RL = 4 Ω, THD = 10%, VDD = 3.6 V 1.6 W
RL = 4 Ω, THD = 10%, VDD = 2.5 V 0.72 W
RL = 3 Ω, THD = 1%, VDD = 5.0 V 3.21 W
RL = 3 Ω, THD = 1%, VDD = 3.6 V 1.52 W
RL = 3 Ω, THD = 1%, VDD = 2.5 V 0.68 W
RL = 3 Ω, THD = 10%, VDD = 5.0 V 3.71 W
RL = 3 Ω, THD = 10%, VDD = 3.6 V 1.9 W
RL = 3 Ω, THD = 10%, VDD = 2.5 V 0.85 W
Efficiency η PO = 1.4 W into 8 Ω, VDD = 5.0 V 93 %
Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.01 %
P
O
= 0.5 W into 8 Ω, f = 1 kHz, V
DD
= 3.6 V
0.01
%
Input Common-Mode Voltage
Range
V
CM
1.0
V
DD
− 1
V
Common-Mode Rejection Ratio CMRRGSM VCM = 2.5 V ± 100 mV, f = 217 Hz, output referred 55 dB
Average Switching Frequency fSW 250 kHz
Differential Output Offset Voltage VOOS Gain = 6 dB 0.1 2.0 mV
POWER SUPPLY
Supply Voltage Range VDD Guaranteed from PSRR test 2.5 5.5 V
Power Supply Rejection Ratio PSRR Inputs are ac-grounded, CIN = 0.1 µF
V
RIPPLE
= 100 mV at 217 Hz
80
dB
VRIPPLE = 100 mV at 1 kHz 80 dB
Supply Current ISY VIN = 0 V, no load, VDD = 5.0 V 3.0 mA
VIN = 0 V, no load, VDD = 3.6 V 2.7 mA
VIN = 0 V, no load, VDD = 2.5 V 2.5 mA
VIN = 0 V, RL = 8 Ω + 33 µH, VDD = 5.0 V 3.1 mA
VIN = 0 V, RL = 8 Ω + 33 µH, VDD = 3.6 V 2.8 mA
VIN = 0 V, RL = 8 Ω + 33 µH, VDD = 2.5 V 2.6 mA
Shutdown Current ISD SD = GND 20 nA
GAIN CONTROL
Closed-Loop Gain Gain 0 12 dB
Input Impedance ZIN SD = VDD, fixed input impedance (0 dB to 12 dB) 80 kΩ
SHUTDOWN CONTROL
Input Voltage High VIH 1.35 V
Input Voltage Low VIL 0.35 V
Turn-On Time tWU SD rising edge from GND to VDD 12.5 ms
Turn-Off Time tSD SD falling edge from VDD to GND 5 µs
Output Impedance
Z
OUT
SD
= GND
>100
kΩ
SSM2375 Data Sheet
Rev. A | Page 4 of 16
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
NOISE PERFORMANCE
Output Voltage Noise en VDD = 5.0 V, f = 20 Hz to 20 kHz, inputs are
ac-grounded, gain = 6 dB, A-weighted
30 µV rms
Signal-to-Noise Ratio SNR PO = 1.4 W, RL = 8 Ω 100 dB
1 Although the SSM2375 has good audio quality above 3 W, continuous output power beyond 3 W without a heat sink must be avoided due to device packaging limitations.
Data Sheet SSM2375
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage 6 V
Input Voltage VDD
Common-Mode Input Voltage VDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec)
300°C
ESD Susceptibility 4 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type PCB θJA θJB Unit
9-Ball, 1.5 mm × 1.5 mm WLCSP 1S0P 162 39 °C/W
2S0P
76
21
°C/W
ESD CAUTION
SSM2375 Data Sheet
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
09011-002
A
321
B
C
IN– SD GAIN
IN+ EDGE OUT–
GND VDD OUT+
BALL A1
CORNER
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1A IN− Inverting Input.
1B IN+ Noninverting Input.
1C GND Ground.
2A SD Shutdown Input. Active low digital input.
2B EDGE Edge Rate Control. Active high.
2C VDD Power Supply.
3A GAIN Gain Control Pin.
3B OUT− Inverting Output.
3C OUT+ Noninverting Output.
Data Sheet SSM2375
Rev. A | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
100
10
1
0.1
0.01
0.001
0.0001 10
THD + N ( %)
OUTPUT POW ER (W)
09011-003
0.001 0.01 0.1 1
R
L
= 8Ω + 33µH
GAIN = 6d B
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
Figure 3. THD + N vs. Output Power into 8 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.001
0.0001 10
THD + N ( %)
OUTPUT POW ER (W)
09011-010
0.001 0.01 0.1 1
R
L
= 4Ω + 15µH
GAIN = 6d B
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
Figure 4. THD + N vs. Output Power into 4 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-012
100 1k 10k
V
DD
= 5V
GAIN = 6d B
R
L
= 8Ω + 33µH
1W
0.25W
0.5W
Figure 5. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.001
0.0001 10
THD + N ( %)
OUTPUT POW ER (W)
09011-004
0.001 0.01 0.1 1
R
L
= 8Ω + 33µH
GAIN = 12d B
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
Figure 6. THD + N vs. Output Power into 8 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.001
0.0001 10
THD + N ( %)
OUTPUT POW ER (W)
09011-011
0.001 0.01 0.1 1
R
L
= 4Ω + 15µH
GAIN = 12d B
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
Figure 7. THD + N vs. Output Power into 4 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-013
100 1k 10k
V
DD
= 5V
GAIN = 12d B
R
L
= 8Ω + 33µH
1W
0.5W
0.25W
Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 12 dB
SSM2375 Data Sheet
Rev. A | Page 8 of 16
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-014
100 1k 10k
VDD = 5V
GAIN = 6d B
RL = 4Ω + 15µH
2W
0.5W
1W
Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-016
100 1k 10k
V
DD
= 3.6V
GAIN = 6d B
R
L
=8Ω + 33µH
0.25W
0.125W
0.5W
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-018
100 1k 10k
VDD = 3.6V
GAIN = 6d B
RL = 4Ω + 15µH
0.25W
0.5W
1W
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-015
100 1k 10k
VDD = 5V
GAIN = 12d B
RL = 4Ω + 15µH
2W
0.5W
1W
Figure 12. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-017
100 1k 10k
V
DD
= 3.6V
GAIN = 12d B
R
L
=8Ω + 33µH
0.25W
0.125W
0.5W
Figure 13. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-019
100 1k 10k
VDD = 3.6V
GAIN = 12d B
RL = 4Ω + 15µH
0.25W
0.5W
1W
Figure 14. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 12 dB
Data Sheet SSM2375
Rev. A | Page 9 of 16
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-020
100 1k 10k
VDD = 2.5V
GAIN = 6d B
RL = 8Ω + 33µH
0.0625W
0.125W
0.25W
Figure 15. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 6 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-022
100 1k 10k
V
DD
= 2.5V
GAIN = 6d B
R
L
= 4Ω + 15µH
0.0625W
0.125W
0.25W
Figure 16. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 6 dB
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.22.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
QUIESCE NT CURRENT (mA)
SUPPLY VOLT AGE (V)
09011-024
8Ω + 33µH
4Ω + 15µH
NO LOAD
GAIN = 0d B
Figure 17. Quiescent Current vs. Supply Voltage, Gain = 0 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-021
100 1k 10k
VDD = 2.5V
GAIN = 12d B
RL = 8Ω + 33µH
0.0625W
0.125W
0.25W
Figure 18. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 12 dB
100
10
1
0.1
0.01
0.00110 100k
THD + N ( %)
FRE QUENCY ( Hz )
09011-023
100 1k 10k
V
DD
= 2.5V
GAIN = 12d B
R
L
= 4Ω + 15µH
0.0625W
0.125W
0.25W
Figure 19. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 12 dB
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.22.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
QUIESCE NT CURRENT (mA)
SUPPLY VOLT AGE (V)
09011-025
NO LOAD
GAIN = 12d B
8Ω + 33µH
4Ω + 15µH
Figure 20. Quiescent Current vs. Supply Voltage, Gain = 12 dB
SSM2375 Data Sheet
Rev. A | Page 10 of 16
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT POW ER (W)
SUPPLY VOLT AGE (V)
09011-026
f = 1kHz
GAIN = 0d B
RL = 8Ω + 33µH
THD + N = 10%
THD + N = 1%
Figure 21. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 0 dB
3.5
2.0
2.5
3.0
1.5
1.0
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT POW ER (W)
SUPPLY VOLT AGE (V)
09011-028
f = 1kHz
GAIN = 0d B
R
L
= 4Ω + 15µH
THD + N = 10%
THD + N = 1%
Figure 22. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 0 dB
100
90
80
70
60
50
40
30
20
10
000.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
EF FICIENCY ( %)
OUTPUT POW ER (W)
09011-030
VDD = 2.5V
VDD = 5V
VDD = 3.6V
RL = 8Ω + 33µH
GAIN = 6d B
Figure 23. Efficiency vs. Output Power into 8 Ω, Gain = 6 dB
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT POW ER (W)
SUPPLY VOLT AGE (V)
09011-027
f = 1kHz
GAIN = 12d B
RL = 8Ω + 33µH
THD + N = 10%
THD + N = 1%
Figure 24. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 12 dB
3.5
2.0
2.5
3.0
1.5
1.0
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT POW ER (W)
SUPPLY VOLT AGE (V)
09011-029
f
= 1kHz
GAIN = 12d B
R
L
= 4Ω + 15µH
THD + N = 10%
THD + N = 1%
Figure 25. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 12 dB
100
90
80
70
60
50
40
30
20
10
000.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
EF FICIENCY ( %)
OUTPUT POW ER (W)
09011-031
VDD = 2.5V
VDD = 5V
VDD
= 3.6V
R
L
= 4Ω + 15µH
GAIN = 6d B
Figure 26. Efficiency vs. Output Power into 4 Ω, Gain = 6 dB
Data Sheet SSM2375
Rev. A | Page 11 of 16
400
002.0
SUPP LY CURRENT (mA)
OUTPUT POW ER (W)
09011-032
50
100
150
200
250
300
350
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
R
L
= 8Ω + 33µH
GAIN = 6d B
Figure 27. Supply Current vs. Output Power into 8 Ω, Gain = 6 dB
0
–10010 100k
CMRR (dB)
FRE QUENCY ( Hz )
09011-036
100 1k 10k
–90
–80
–70
–60
–50
–40
–30
–20
–10
Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency
7
6
5
4
3
2
1
0
–1–8 –4 36322824201612840
VOLT AGE (V)
TIME (ms)
09011-038
SD I NP UT
OUTPUT
Figure 29. Turn-On Response
800
003.5
SUPP LY CURRENT (mA)
OUTPUT POW ER (W)
09011-033
100
200
300
400
500
600
700
0.5 1.0 1.5 2.0 2.5 3.0
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
R
L
= 4Ω + 15µH
GAIN = 6d B
Figure 30. Supply Current vs. Output Power into 4 Ω, Gain = 6 dB
0
–10010 100k
PSRR ( dB)
FRE QUENCY ( Hz )
09011-037
100 1k 10k
–90
–80
–70
–60
–50
–40
–30
–20
–10
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency
7
6
5
4
3
2
1
0
–50 –30 –10 10 30 50 70
VOLT AGE (V)
TIME (µs)
09011-039
SD I NP UT
OUTPUT
Figure 32. Turn-Off Response
SSM2375 Data Sheet
Rev. A | Page 12 of 16
TYPICAL APPLICATION CIRCUITS
FET
DRIVER
MODULATOR
(Σ-∆)
0.1µF
VDD
OUT+
OUT–
BIAS EDGE
IN+
POWER SUPPLY
2.5V TO 5.5V
IN–
INTERNAL
OSCILLATOR
EDGE
CONTROL
GND
10µF
22nF
22nF
R
GAIN
(9dB/12dB ONLY)
SHUTDOWN SD
G
AIN SELECT
IN–
IN+
SSM2375
GAIN
CONTROL
GAIN
G
AIN = 0dB (GND), 3dB (OPEN)*, 6dB (VDD), 9dB (GND), OR 12dB (VDD)
09011-005
*SEE THE GAIN SELECTION SECTION FOR MORE INFORMATION
ON AVOIDING EXCESSIVE INDUCED NOISE.
Figure 33. Monaural Differential Input Configuration
FET
DRIVER
MODULATOR
(Σ-∆)
0.1µF
VDD
OUT+
OUT–
BIAS EDGE
IN+
POWER SUPPLY
2.5V TO 5.5V
IN–
INTERNAL
OSCILLATOR
EDGE
CONTROL
GND
10µF
22nF
22nF
RGAIN (9dB/12dB ONLY)
SHUTDOWN SD
G
AIN SELECT
IN+
SSM2375
GAIN
CONTROL
GAIN
G
AIN = 0dB (GND), 3dB (OPEN)*, 6dB (VDD), 9dB (GND), OR 12dB (VDD)
0
9011-006
*SEE THE GAIN SELECTION SECTION FOR MORE INFORMATION
ON AVOIDING EXCESSIVE INDUCED NOISE.
Figure 34. Monaural Single-Ended Input Configuration
Data Sheet SSM2375
Rev. A | Page 13 of 16
THEORY OF OPERATION
OVERVIEW
The SSM2375 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and, thus, reducing systems cost.
The SSM2375 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the switching output.
Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM2375 uses Σ-Δ modulation to
determine the switching pattern of the output devices, resulting
in a number of important benefits.
• Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width
modulators often do.
• Σ-Δ modulation provides the benefits of reducing the
amplitude of spectral components at high frequencies,
that is, reducing EMI emissions that might otherwise be
radiated by speakers and long cable traces.
• Due to the inherent spread-spectrum nature of Σ-Δ modu-
lation, the need for oscillator synchronization is eliminated
for designs that incorporate multiple SSM2375 amplifiers.
The SSM2375 also integrates overcurrent and overtemperature
protection.
GAIN SELECTION
The preset gain of the SSM2375 can be set from 0 dB to 12 dB
in 3 dB steps with one external resistor (optional). The external
resistor is used to select the 9 dB or 12 dB gain setting, as shown
in Table 5.
To avoid excessive induced noise at high output power, observe
caution under the following conditions: GAIN pin is configured
to the 3 dB gain setting (open) and using both low impedance
(less than 3 Ω + 10 μH) loading and configured for low emissions
mode (EDGE = VDD). To safeguard against the potential induced
noise at high power levels in this configuration, connect a capacitor
from GAIN to GND with a value ranging from 2.2 μF to 4.7 μF.
Alternatively, apply a fixed voltage of VDD/2 to the GAIN pin
to stabilize the gain setting operation under the low impedance/
high power condition stated above.
Table 5. Gain Function Descriptions
Gain Setting (dB) GAIN Pin Configuration
12 Tie to VDD through 47 kΩ resistor
9 Tie to GND through 47 kΩ resistor
6 Tie to VDD
31 Open
0 Tie to GND
1 See the Gain Selection section for more information on avoiding excessive
induced noise.
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur
when shutdown is activated or deactivated. Voltage transients as
low as 10 mV can be heard as an audio pop in a low sensitivity
handset speaker. Clicks and pops can also be classified as undesir-
able audible transients generated by the amplifier system and,
therefore, as not coming from the system input signal.
The SSM2375 has a pop-and-click suppression architecture that
reduces these output transients, resulting in noiseless activation
and deactivation from the SD control pin while operating in a
typical audio configuration.
EMI NOISE
The SSM2375 uses a proprietary modulation and spread-spectrum
technology to minimize EMI emissions from the device. For
applications that have difficulty passing FCC Class B emission
tests, the SSM2375 includes a modulation select pin (ultralow
EMI emissions mode) that significantly reduces the radiated
emissions at the Class-D outputs, particularly above 100 MHz.
EMI emission tests on the SSM2375 were performed in a certified
FCC Class B laboratory in low emissions mode (EDGE = VDD).
With a pink noise source, an 8 Ω speaker load, and a 5 V supply,
the SSM2375 was able to pass FCC Class B limits with 50 cm,
unshielded twisted pair speaker cable. Note that reducing the
power supply voltage greatly reduces radiated emissions.
OUTPUT MODULATION DESCRIPTION
The SSM2375 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to VDD and vice versa. Ideally, when
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present.
Due to this constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differ-
ential pulse is generated.
Most of the time, however, the output differential voltage is 0 V,
due to the Analog Devices, Inc., three-level, Σ-Δ output modula-
tion. This feature ensures that the current flowing through the
inductive load is small.
When the user wants to send an input signal, an output pulse
is generated to follow the input voltage. The differential pulse
density is increased by raising the input signal level. Figure 35
depicts three-level, Σ-Δ output modulation with and without
input stimulus.
SSM2375 Data Sheet
Rev. A | Page 14 of 16
OUTPUT > 0V
+5V
0V
OUT+
+5V
0V
OUT–
+5V
0V
VOUT
OUTPUT < 0V
+5V
0V
OUT+
+5V
0V
OUT–
0V
–5V
VOUT
OUTPUT = 0V
OUT+ +5V
0V
+5V
0V
OUT–
+5V
–5V
0V
VOUT
09011-009
Figure 35. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply. A good practice is to use short, wide PCB tracks to
decrease voltage drops and minimize inductance. The PCB
layout engineer must avoid ground loops where possible to
minimize common-mode current associated with separate paths
to ground. Ensure that track widths are at least 200 mil for every
inch of track length for lowest DCR, and use 1 oz or 2 oz copper
PCB traces to further reduce IR drops and inductance. A poor
layout increases voltage drops, consequently affecting efficiency.
Use large traces for the power supply inputs and amplifier outputs
to minimize losses due to parasitic trace resistance.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.
In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
INPUT CAPACITOR SELECTION
The SSM2375 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recom-
mended input dc common-mode voltage range, if high-pass
filtering is needed, or if a single-ended source is used. If high-
pass filtering is needed at the input, the input capacitor and the
input resistor of the SSM2375 form a high-pass filter whose
corner frequency is determined by the following equation:
fC = 1/(2π × RIN × CIN)
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. These spikes can contain frequency components
that extend into the hundreds of megahertz. The power supply
input must be decoupled with a good quality, low ESL, low ESR
capacitor, with a minimum value of 4.7 µF. This capacitor
bypasses low frequency noises to the ground plane. For high
frequency transient noises, use a 0.1 µF capacitor as close as
possible to the VDD pin of the device. Placing the decoupling
capacitors as close as possible to the SSM2375 helps to maintain
efficient performance.
Data Sheet SSM2375
Rev. A | Page 15 of 16
OUTLINE DIMENSIONS
1.490
1.460 S Q
1.430
0.385
0.360
0.335
09-04-2012-C
A
B
C
0.655
0.600
0.545
1
2
3
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SI DE DOW N)
END VIEW
0.350
0.320
0.290
1.00
REF
0.50
BSC
SEATING
PLANE 0.270
0.240
0.210
COPLANARITY
0.05
BALLA1
IDENTIFIER
Figure 36. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option2
SSM2375CBZ-REEL −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
SSM2375CBZ-REEL7 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
EVAL-SSM2375Z Evaluation Board
1 Z = RoHS Compliant Part.
2 This package option is halide free.
