© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 0 1Publication Order Number:
CAS24F64/D
CAS24F64
64 Kb I2C CMOS Serial
EEPROM
Description
The CAS24F64 is a 64 Kb CMOS Serial EEPROM device,
internally organized as 8192 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
Features
•Supports Standard, Fast and Fast−Plus I2C Protocol
•1.7 V to 5.5 V Supply Voltage Range
•32−Byte Page Write Buffer
•Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
•Low Power CMOS Technology
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
Figure 1. Functional Symbol
SDA
SCL CAS24F64
VCC
VSS
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PIN CONFIGURATIONS
(Top View)
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
Serial DataSDA Serial ClockSCL Power SupplyVCC GroundVSS
FunctionPin Name
PIN FUNCTION
WLCSP4
C4B SUFFIX
CASE 567NH
WLCSP−4
A1 A2
B1 B2 SDA
VSS
SCL
VCC
1
T = Specific Device Code
Y = Year
W = Work Week
T
YW
MARKING
DIAGRAM
CAS24F64
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2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature –65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program/Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 1 MHz 1 mA
ICCW Write Current Write, fSCL = 1 MHz 2 mA
ISB Standby Current All I/O Pins at GND or VCC 1mA
ILI/O Pin Leakage Pin at GND or VCC 2mA
VIL Input Low Voltage VCC ≥ 2.2 V −0.5 VCC x 0.3 V
VCC < 2.2 V −0.5 VCC x 0.25 V
VIH Input High Voltage VCC ≥ 2.2 V VCC x 0.7 VCC + 0.5 V
VCC < 2.2 V VCC x 0.75 VCC + 0.5 V
VOL Output Low Voltage VCC ≥ 2.2 V, IOL = 3.0 mA 0.4 V
VCC < 2.2 V, IOL = 1.0 mA 0.2 V
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
CAS24F64
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Table 5. A.C. CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C.) (Note 5)
Symbol Parameter
Standard Fast Fast−Plus
Units
Min Max Min Max Min Max
FSCL Clock Frequency 100 400 1,000 kHz
tHD:STA START Condition Hold Time 4 0.6 0.26 ms
tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms
tHIGH High Period of SCL Clock 4 0.6 0.35 ms
tSU:STA START Condition Setup Time 4.7 0.6 0.26 ms
tHD:DAT Data In Hold Time 0 0 0 ns
tSU:DAT Data In Setup Time 250 100 50 ns
tR (Note 6) SDA and SCL Rise Time 1,000 300 100 ns
tF (Note 6) SDA and SCL Fall Time 300 300 100 ns
tSU:STO STOP Condition Setup Time 4 0.6 0.26 ms
tBUF Bus Free Time Between
STOP and START 4.7 1.3 0.5 ms
tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms
tDH Data Out Hold Time 100 100 100 ns
Ti (Note 6) Noise Pulse Filtered at SCL
and SDA Inputs 50 50 50 ns
tWR Write Cycle Time 4 4 4 ms
tPU (Notes 6, 7) Power−up to Ready Mode 0.35 0.35 0.35 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Test conditions according to “A.C. Test Conditions” table.
6. Tested initially and after a design or process change that affects this parameter.
7. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels 0.20 x VCC to 0.8 x VCC for VCC ≥ 2.2 V & 0.15 x VCC to 0.85 x VCC for VCC < 2.2 V
Input Rise and Fall Times ≤ 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load Current Source: IOL = 3 mA (VCC ≥ 2.2 V); IOL = 1 mA (VCC < 2.2 V); CL = 100 pF
CAS24F64
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Power−On Reset (POR)
Each CAS24F64 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after VCC exceeds the POR trigger level and will
power down into Reset mode when VCC drops below the
POR trigger level. This bi−directional POR behavior
protects the device against ‘brown−out’ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
Functional Description
The CAS24F64 supports the Inter−Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAS24F64
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
I2C Bus Protocol
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
Master provides the clock to the SCL line, and either the
Master o r the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address. For
the CAS24F64, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A2, A1 and A0, must match
the logic state of the similarly named input pins. The devices
in WLCSP 4−bumps respond only to the Slave Address with
A2 A1 A0 = 000. The R/W bit tells the Slave whether the
Master intends to read (1) or write (0) data (Figure 3).
Acknowledge
During the 9th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
START
CONDITION STOP
CONDITION
SDA
SCL
Figure 2. Start/Stop Timing
Figure 3. Slave Address Bits
1010
DEVICE ADDRESS*
A2A1A0R/W
* The devices in WLCSP 4−bumps respond only to the Slave Address with A2 A1 A0 = 000.
CAS24F64
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5
Figure 4. Acknowledge Timing
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 5. Bus Timing
SCL
SDA IN
SDA OUT
tBUF
tSU:STO
tSU:DAT
tR
tAA tDH
tLOW
tHIGH
tLOW
tSU:STA tHD:STA
tHD:DAT
tF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tri−stated
and the Slave does not acknowledge the Master (Figure 7).
Page Write
The Byte W rite operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Delivery State
The CAS24F64 is shipped erased, i.e., all bytes are FFh.
CAS24F64
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6
SLAVE
ADDRESS
S
A
***
C
K
A
C
K
A
C
K
S
T
O
P
P
S
T
A
R
T
A
C
K
BUS ACTIVITY :
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
BYTE DATA
BYTE
Figure 6. Byte Write Sequence
*a15 − a13 are don’t care bits.
a15 − a8a7 − a0d7 − d0
Figure 7. Write Cycle Timing
STOP
CONDITION START
CONDITION ADDRESS
ACK8th Bit
Byte n
SCL
SDA
tWR
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
P
A
C
K
BUS
ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
Figure 8. Page Write Sequence
CAS24F64
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7
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 9). The Slave then returns to Standby mode.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 10).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 11). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
Figure 9. Immediate Read Sequence and Timing
SCL
SDA 8th Bit
STOP
NO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
KDATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY :
MASTER
SLAVE
Figure 10. Selective Read Sequence
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
TSLAVE
S
A
C
K
S
T
A
R
T
P
S
T
O
P
ADDRESS
BYTE ADDRESS
BYTE ADDRESS
N
O
A
C
K
DATA
BYTE
BUS ACTIVITY :
MASTER
SLAVE
Figure 11. Sequential Read Sequence
S
T
O
P
P
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
BUS ACTIVITY :
MASTER
SLAVE
CAS24F64
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8
PACKAGE DIMENSIONS
WLCSP4 0.77x0.77, 0.35P
CASE 567NH
ISSUE O
ÈÈ
SEATING
PLANE
0.02 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE
SPHERICAL CROWNS OF THE CONTACT BALLS.
4. COPLANARITY APPLIES TO SPHERICAL CROWNS OF
CONTACT BALLS.
5. DIMENSION b IS MEASURED AT THE MAXIMUM CON-
TACT BALL DIAMETER PARALLEL TO DATUM C.
2X
DIM
AMIN MAX
0.28
MILLIMETERS
A1
D0.77 BSC
E
b0.16 0.20
e0.35 BSC
0.38
E
D
AB
PIN A1
REFERENCE
e
A0.05 BC
0.03 C
0.05 C
4X b
12
B
A
0.10 C
A
A1
A2
C
0.08 0.12
0.77 BSC
0.02 C
2X TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 4
e
A2 0.23 REF
PITCH 0.18
4X
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.35 0.35
RECOMMENDED
A1 PACKAGE
OUTLINE
PITCH
DIE COAT
DETAIL A
OPTIONAL CONSTRUCTION
A2
A3
A3 0.025 REF
DET AIL A
A
NOTE 5
CAS24F64
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9
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking Package Type Temperature Range Lead Finish Shipping
CAS24F64C4BTR TWLCSP−4 (−40°C to +85°C) SnAgCu Tape & Reel,
5,000 Units / Reel
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
10.Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultra violet light. When exposed to ultra violet light
the EEPROM cells lose their stored data.
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. S CILLC r eserves the right t o make changes without further n otice to any product s herein. S CILLC makes no warrant y, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all l iabilit y, including without l imit at ion s pecial, c onsequent ial o r i n cidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application b y c ust omer’s technical e xperts. SCILLC does not c onvey a ny license under its p atent rights nor t he r ights o f o t hers. S CI LLC p roduct s a re n ot designed, int ended,
or authorized for use as c omponent s i n s yst ems i nt ended f or s urgic al i m plant i nt o the body, or other applications intended t o s upport o r s ust ain life, or for any other a pplicat ion in w hich
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC an d it s officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and r easonable a ttorney f ees a rising o ut of, directly or i ndirectly, a ny c laim o f personal injury or d eath a ssociated w ith s uch u nint ended o r u nauthorized u se, e ven if such claim
alleges that SCILLC was negligent regarding the d esign or manufacture of the p art. SCILLC i s a n E qual O pportunity/Af firmative Act ion Employer. T his literature is s ubject t o all applicable
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P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
CAS24F64/D
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
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