APL5913 0.8V Reference Ultra Low Dropout (0.25V@3A) Linear Regulator Features General Description * Ultra Low Dropout - 0.25V(typical) at 3A Output Current * The APL5913 is a 3A ultra low dropout linear regulator. This product is specifically designed to provide well sup- Low ESR Output Capacitor (Multi-layer Chip Capacitors (MLCC)) Applicable * * pl y vo la tag e fo r fro nt -s id e-b us t er m in at io n on motherboards and NB applications. The IC needs two 0.8V Reference Voltage High Output Accuracy supply voltages, a control voltage for the circuitry and a main supply voltage for power conversion, to reduce * * - 1.5% over Line, Load and Temperature Fast Transient Response power dissipation and provide extremely low dropout. The APL5913 integrates many functions. A Power-On-Reset (POR) circuit monitors both supply voltages to pre- Adjustable Output Voltage by External Resistors * Power-On-Reset Monitoring on Both VCNTL and VIN Pins * * * * * * * * Internal Soft-Start Current-Limit Protection vent wrong operations. A thermal shutdown and current limit functions protect the device against thermal and current over-loads. A POK indicates the output status with time delay which is set internally. It can control other converter for power sequence. The APL5913 is enabled by other power system. Pulling and holding the EN pin be- Under-Voltage Protection Thermal Shutdown with Hysteresis low 0.3V shuts off the output. Power-OK Output with a Delay Time Shutdown for Standby or Suspend Mode The APL5913 is available in SOP-8P package which features small size as SOP-8 and an Exposed Pad to reduce Simple SOP-8P Package with Exposed Pad Lead Free and Green Devices Available the junction-to-case resistance, being applicable in 2~2.4W applications. (RoHS Compliant) Applications Pin Configuration * Front Side Bus VTT (1.2V/3A) * Note Book PC Applications * Motherboard Applications GND FB VOUT VOUT 1 8 2 7 3 VIN 4 6 5 EN POK VCNTL VIN SOP-8P (Top View) = Exposed Pad (connected to VIN plane for better heat dissipation) Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 1 www.anpec.com.tw APL5913 Ordering and Marking Information APL5913 Package Code KA : SOP-8P Operating Ambient Temperature Range C : 0 to 70 oC Handing Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code APL5913 XXXXX APL5913 KA : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Block Diagram EN VCNTL VIN PowerOn-Reset UV Soft-Start and Control Logic Thermal Limit 0.4V VREF 0.8V EAMP VOUT Current Limit FB POK Delay GND 90% VREF POK Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 2 www.anpec.com.tw APL5913 Typical Application Circuits 1. Using an Output Capacitor with ESR18m VCNTL +5V CCNTL 1F 6 R3 1k VCNTL 7 POk VIN 5 POk 3 VOUT 4 VOUT APL5913 8 EN EN FB VOUT +1.2V / 3A COUT 220F 2 R1 1k GND Enable VIN +1.5V CIN 100F 1 R2 2k C1 33nF (in the range of 12 ~ 48nF) 2. Using an MLCC as the Output Capacitor VCNTL +5V CCNTL 1F 6 R3 1k CIN 22F VCNTL 7 POk VIN 5 POk 3 VOUT 4 VOUT EN 8 APL5913 EN FB COUT 22F 2 VOUT +1.2V / 3A R1 39k GND Enable VIN +1.5V 1 R2 78k C1 56pF VOUT (V) 1.05 1.5 1.8 R1 (k) 43 27 15 Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 R2 (k) 137.6 30.86 12 3 C1 (pF) 47 82 150 www.anpec.com.tw APL5913 Absolute Maximum Ratings Symbol VCNTL Parameter VCNTL Supply Voltage (VCNTL to GND) VIN VIN Supply Voltage (VIN to GND) VI/O EN and FB to GND VPOK POK to GND PD TJ TSTG TSDR Power Dissipation Rating Unit -0.3 ~ 7 V -0.3 ~ 3.3 V -0.3 ~ VCNTL+0.3 V -0.3 ~ 7 V 3 Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds W 150 o -65 ~ 150 o 260 o C C C Thermal Characteristics Symbol JA JC Parameter Value Junction-to-Ambient Thermal Resistance in Free Air Junction-to-Case Thermal Resistance in Free Air (Note1) (Note 2) Unit 42 o C/W 18 o C/W Note 1 : JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 2 : The "Thermal Pad Temperature" is measured on the PCB copper area connected to the thermal pad of package. 1 2 3 4 8 VIN 7 6 5 Measured Point PCB Copper Recommended Operating Conditions Symbol VCNTL VIN Parameter Range VCNTL Supply Voltage Unit 3.1 ~ 6 V 1.1 ~ 3.3 V VCNTL=3.35% 0.8 ~ 1.2 V VCNTL=5.05% 0.8 ~ VIN-0.2 VIN Supply Voltage Output Voltage VOUT IOUT TJ VOUT Output Current 0~4 Junction Temperature Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 A -25 ~ 125 4 o C www.anpec.com.tw APL5913 Electrical Characteristics Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0 to 70C, unless otherwise specified. Typical values refer to TA = 25C. Symbol Parameter APL5913 Test Conditions Unit Min Typ Max 0.4 1 2 mA 180 380 A 2.9 3.1 V SUPPLY CURRENT ICNTL ISD VCNTL Supply Current EN = VCNTL, VFB is well regulated VCNTL Shutdown Current EN = GND POWER-ON-RESET VCNTL POR Threshold VCNTL Rising 2.7 VCNTL POR Hysteresis VIN POR Threshold 0.4 VIN Rising 0.8 VIN POR Hysteresis 0.9 V 1.0 0.5 V OUTPUT VOLTAGE VREF Reference Voltage FB =VOUT Output Voltage Accuracy IOUT=0A ~ 3A, TJ= -25 ~125oC -1.5 0.8 Line Regulation VCNTL=3.3 ~ 5.5V -0.13 Load Regulation IOUT=0A ~ 3A V +1.5 % 0 0.13 %/V 0.06 0.15 % 0.17 0.25 V 0.3 V DROPOUT VOLTAGE o Dropout Voltage IOUT = 3A, VCNTL=5V, TJ= 25 C o IOUT = 3A, VCNTL=5V, TJ= -50~125 C PROTECTION VCNTL=5V, TJ= 25oC ILIM Current Limit 4.8 VCNTL=5V, TJ= -25 ~ 125oC o VCNTL=3.3V, TJ= 25 C 4.6 o VCNTL=3.3V, TJ= -25 ~ 125 C TSD Thermal Shutdown Temperature 6.6 TJ Rising VFB Falling A A 5.5 6.4 3.8 Thermal Shutdown Hysteresis Under-Voltage Threshold 5.7 4 A A 150 o 50 o C C 0.4 V ENABLE AND SOFT-START EN Logic High Threshold Voltage VEN Rising 0.3 EN Hysteresis EN Pin Pull-Up Current TSS TDELAY V mV 10 A 2 ms VFB Rising 90% 92% 94% VREF VFB Falling 79% 81% 83% VREF 0.25 0.4 V 3 10 ms POK sinks 5mA POK Delay Time Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 0.5 30 EN=GND Soft-Start Interval POWER OK AND DELAY POK Threshold Voltage for Power VPOK OK POK Threshold Voltage for Power VPNOK Not OK POK Low Voltage 0.4 1 5 www.anpec.com.tw APL5913 Typical Operating Characteristics Current-limit vs. Junction Temperature 5.5 1.0 0.9 5.4 VCNTL=5V 5.3 0.8 Current-limit, ILIM (A) VCNTL Supply Current, ICNTL (mA) VCNTL Supply Current vs. Junction Temperature 0.7 0.6 0.5 VCNTL=3.3V 0.4 0.3 5.2 5 4.9 4.8 0.2 4.7 0.1 4.6 -25 0 25 50 75 100 VCNTL=3.3V 4.5 -50 0.0 -50 VCNTL=5V 5.1 125 0 25 50 75 100 125 Junction Temperature (C) Junction Temperature (C) Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current 450 250 VCNTL=3.3V VOUT=1.2V 400 VCNTL=5V VOUT=1.2V TJ=125C 350 TJ=75C Dropout Voltage (mV) Dropout Voltage (mV) -25 TJ=25C 300 250 TJ=0C 200 150 TJ=-25C 100 200 TJ=125C TJ=75C 150 TJ=25C 100 TJ=0C TJ=-25C 50 50 0 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 3.0 Output Current, lOUT(A) Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 0.5 1.0 1.5 2.0 2.5 3.0 Output Current, lOUT(A) 6 www.anpec.com.tw APL5913 Typical Operating Characteristics POK Delay Time vs. Junction Temperature Reference Voltage vs. Junction Temperature 4.5 4.3 0.806 4.1 POK Delay Time (ms) Reference Voltage, VREF (mV) 0.808 0.804 0.802 0.800 0.798 0.796 0.794 3.9 VCNTL=5V 3.7 3.5 3.3 VCNTL=3.3V 3.1 2.9 2.7 2.5 0.792 -50 -25 0 25 50 75 100 -50 125 Junction Temperature (C) -25 0 50 75 100 125 Junction Temperature (C) VIN PSRR VCNTL PSRR 0 0.00 VCNTL = 4.5V~5.5V VIN = 1.5V VOUT = 1.2V IOUT = 3A CIN = 100F COUT = 330F(ESR=30m) -20.00 VCNTL = 5V VIN = 1.5V(lower bound) VINPK-PK = 100mV CIN = 47F COUT = 330F(30m) IOUT = 3A VOUT = 1.2V -10 -20 Amplitude (dB) -10.00 Ripple Rejection (dB) 25 -30.00 -40.00 -50.00 -30 -40 -50 -60 -70 -60.00 100 1000 10000 100000 100 1000000 10000 100000 1000000 Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 1000 7 www.anpec.com.tw APL5913 Operating Waveforms Test Circuit R4 C2 1F L1 1H 2.2 +5V 5 C8 470pF R8 8.2k VCC BOOT 7 UGATE PHASE 2 FB Q1 APM2014N VIN +1.5 V 8 LGATE POK VCNTL 5 POK VIN CIN 100F C5 1000F x2 Q2 APM2014N 4 VCNTL +5V CVCNTL 1F L2 3.3H U2 APW7057 6 C9 47F 6 C6 0.1F Q3 C4 470F x2 1 OCSET Shutdown C3 1F D1 1N4148 VOUT VOUT GND 3 R5 1.75k EN Enable 8 U1 APL5913 EN FB C7 0.1F R3 1k 3 VOUT +1.2V/3A 4 COUT 220F 2 GND 1 R7 2k 7 R2 2k R1 1k C1 33nF R6 0 1. Load Transient Response : 1.1 Using an Output Capacitor with ESR18m - COUT = 220F/6.3V (ESR = 30m), CIN = 100F/6.3V - IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1s IOUT = 10mA ->3A IOUT = 10mA -> 3A ->10mA IOUT = 3A ->10mA R1=1k, R2=2k, C1=33n F VOUT VOUT IOUT IOUT 1 VOUT IOUT 2 Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 1A/Div Time : 2s/Div Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 1A/Div Time : 20s/Div 8 Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 1A/Div Time : 2s/Div www.anpec.com.tw APL5913 Operating Waveforms (Cont.) 1.2 Using a MLCC as the Output Capacitor - COUT = 22F/6.3V (ESR = 3m), CIN = 22F/6.3V - IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1s IOUT = 10mA ->3A IOUT = 10mA -> 3A ->10mA VOUT 1 1 R1=39k, R2=78k C1=56pF VOUT IOUT = 3A ->10mA VOUT 1 2 IOUT IOUT IOUT 2 2 Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 1A/Div Time : 20s/Div Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 1A/Div Time : 2s/Div Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 1A/Div Time : 2s/Div 2. Power ON and Power OFF : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220F/6.3V (ESR = 30m), CIN = 100F/6.3V, RL=1 Power OFF Power ON VIN Ch1 Ch1 V VIN IN VOUT VOUT VOUT Ch2 VCNTL Ch2 VVCNTL CNTL VPOK VVPOK POK Ch3 Ch3 Ch4 Ch4 Ch1 : VIN, 1V/div Ch2 : VOUT, 1V/div Ch3 : VPOK, 1V/div Ch4 : VCNTL, 2V/div Time : 10ms/div Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 Ch1 : VIN, 1V/div Ch2 : VOUT, 1V/div Ch3 : VPOK, 1V/div Ch4 : VCNTL, 2V/div Time : 10ms/div 9 www.anpec.com.tw APL5913 Operating Waveforms (Cont.) 3. Shutdown and Enable : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220F/6.3V (ESR = 30m), CIN = 100F/6.3V, RL=1 Enable Shutdown VEN V EN Ch1 VEN VEN Ch1 VOUT OUT VVOUT OUT Ch2 Ch2 IIOUT OUT IIOUT OUT Ch3 Ch3 POK VVPOK VPOK V POK Ch4 Ch4 Ch1 : VEN, 5V/div Ch2 : VOUT, 1V/div Ch3 : IOUT, 1A/div Ch4 : VPOK, 1V/div Time : 1ms/div Ch1 : VEN, 5V/div Ch2 : VOUT, 1V/div Ch3 : IOUT, 1A/div Ch4 : VPOK, 1V/div Time : 1ms/div 4. POK Delay : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220F/6.3V (ESR = 30m), CIN = 100F/6.3V, RL=1 IN VVIN Ch1 POK Delay VVOUT OUT Ch2 Ch3 VPOK V POK Ch1 : VIN, 1V/div Ch2 : VOUT, 1V/div Ch3 : VPOK, 1V/div Time : 1ms/div Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 10 www.anpec.com.tw APL5913 Functional Pin Description GND (Pin 1) VCNTL (Pin 6) Ground pin of the circuitry. All voltage levels are mea- Power input pin of the control circuitry. Connecting this sured with respect to this pin. pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is FB (Pin 2) monitored for Power-On-Reset purpose. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage POK (Pin 7) set by the resistor divider is determined by: VOUT = 0.8 1+ R1 R2 Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sens- (V) where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to GND. A bypass capacitor may be connected with R1 in parallel to improve load transient response. ing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. EN (Pin 8) VOUT (Pin 3,4) Enable control pin. Pulling and holding this pin below 0. Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a 3V shuts down the output. When re-enabled, the IC undergoes a new soft-start cycle. When leave this pin open, output capacitor with this pin for closed-loop compensation and improve transient responses. an internal current source 10A pulls this pin up to VCNTL voltage, enabling the regulator. VIN (Pin 5) and Exposed Pad Main supply input pins for power conversions. The Exposed Pad provides a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for Power-On-Reset purpose. Function Description Power-On-Reset Internal Soft-Start A Power-On-Reset (POR) circuit monitors both input volt- An internal soft-start function controls rising rate of the output voltage to limit the current surge at start-up. The ages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process typical soft-start interval is about 2ms. after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR func- Output Voltage Regulation tion also pulls low the POK pin regardless the output voltage when the VCNTL voltage falls below its falling An error amplifier works with a temperature- compensated 0.8V reference and an output NMOS regulates out- POR threshold. put to the preset voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 11 www.anpec.com.tw APL5913 Function Description (Cont.) Output Voltage Regulation (Cont.) For normal operation, device power dissipation should reference with the feedback voltage and amplifies the dif- be externally limited so that junction temperatures will not exceed +125C. ference to drive the output NMOS which provides load current from VIN to VOUT. Enable Control Current-Limit The APL5913 has a dedicated enable pin (EN). A logic The APL5913 monitors the current via the output NMOS low signal (VEN< 0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-en- and limits the maximum current to prevent load and APL5913 from damages during overload or short-circuit conditions. ables the output through initiation of a new softstart cycle. when leave it opens, this pin is pulled up by an internal Under-Voltage Protection (UVP) current source (10A, typical) to enable operation. It's not necessary to use an external transistor to save cost. The APL5913 monitors the voltage on FB pin after softstart process is finished. Therefore, the UVP is disable Power-OK and Delay The APL5913 indicates the status of the output voltage by during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK threshold output immediately. After a while, the APL5913 starts a new soft-start to regulate output. (VPOK), an internal delay function starts to perform a delay time. At the end of the delay time, the IC turns off the Thermal Shutdown internal NMOS of the POK to indicate the output is OK. As the VFB falls and reaches the falling Power-OK threshold A thermal shutdown circuit limits the junction temperature of APL5913. When the junction temperature exceeds +150C, a thermal sensor turns off the output NMOS, allowing the (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time. device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature cools by 50C, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown is designed with a 50oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. Application Information Power Sequencing Output Capacitor The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to VOUT The APL5913 requires a proper output capacitor to maintain stability and improve transient response over for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from temperature and current. The output capacitor selection is to select proper ESR (equivalent series resistance) VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. and capacitance of the output capacitor for good stability Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 and load transient response. 12 www.anpec.com.tw APL5913 Application Information (Cont.) and FB pins. It works with the internal error amplifier to provide proper frequency response for the linear regulator. Output Capacitor (Cont.) The APL5913 is designed with a programmable feedback compensation adjusted by an external feedback network The ESR is the equivalent series resistance of the output capacitor. The C OUT is ideal capacitance in the output for the use of wide ranges of ESR and capacitance in all applications. Ultra-low-ESR capacitors (such as ceramic capacitor. The VOUT is the setting of the output voltage. chip capacitors) and low-ESR bulk capacitors (such as solid Tantalum, POSCap, and Aluminum electrolytic VOUT VOUT capacitors) can all be used as an output capacitor. The value of the output capacitors can be increased without APL5913 R1 limit. ESR FB V ERR During load transients, the output capacitors, depending on the stepping amplitude and slew rate of load current, C1 VREF are used to reduce the slew rate of the current seen by the APL5913 and help the device to minimize the variations C OUT VFB EAMP of output voltage for good transient response. For the applications with large stepping load current, the low- R2 Figure 1 The feedback network selection depends on the values ESR bulk capacitors are normally recommended. of the ESR and COUT which has been classified into three conditions: Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance * Condition 1 : Large ESR ( 18m ) of the layout must be minimized. - Select the R1 in the range of 400 ~ 2.4k Input Capacitor - Calculate the R2 as the following : The APL5913 requires proper input capacitors to supply R2(k) = R1(k) current surge during stepping load transients to prevent the input rail from dropping. Because the parasitic in- 0.8(V) .......... (1) VOUT(V) - 0.8(V) - Calculate the C1 as the following : ductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, 10 more parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors (such as ceramic chip VOUT(V) VOUT(V) ...... (2) C1(nF) 40 R1(k ) R1(k ) * Condition 2 : Middle ESR - Calculate the R1 as the following: capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) R1(k) = can all be used as an input capacitor of VIN. For most of applications, the recommended input capacitance of VIN 2157 - 37.5 VOUT(V) + 15 ......... (3) ESR(m) Select a proper R1(selected) to be a little larger than is 10F at least. If the drop of the input voltage is not the calculated R1. - Calculate the C1 as the following : cared, the input capacitance can be less than 10F. More capacitance reduces the variations of the input voltage of C1(pF) = [0.71 ESR(m ) + 101] VIN pin. COUT(F) ........ (4) R1(k) Where R1=R1(selected) Feedback Network Select a proper C1(selected) to be a little smaller than the calculated C1. Figure 1 shows the feedback network among VOUT, GND, - The C1 calculated from equation (4) must meet the following equation: Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 13 www.anpec.com.tw APL5913 Application Information (Cont.) Feedback Network (Cont.) PCB Layout Consideration (See Figure 2) 1. Please solder the Exposed Pad and VIN together on 143 37.5 VOUT(V) C1(pF) 7.2 1 + 1 + .. (5) ESR(m R1(k) ) the PCB. The main current flow is through the ex posed pad. Where R1=R1(calculated) from equation (3) 2. Please place the input capacitors for VIN and VCNTL If the C1(calculated) can not meet the equation (5), pins near pins as close as possible. please use the Condition 3. 3. Ceramic decoupling capacitors for load must be - Use equation (2) to calculate the R2. placed near the load as close as possible. 4. To place APL5913 and output capacitors near the load * Condition 3 : Low ESR (eg. Ceramic Capacitors) is good for performance. - Calculate the R1 as the following: 5. The negative pins of the input and output capaci-tors R1(k) = (2.1 ESR(m) + 300) COUT(F) - 37.5 VOUT(V) .. (6) and the GND pin of the APL5913 are connected to the ground plane of the load. Select a proper R1(selected) to be a little larger than the calculated R1. The minimum selected R1 is 6. Please connect PIN 3 and 4 together by a wide track. 7. Large current paths must have wide tracks. equal to 1k when the calculated R1 is smaller than 1k or negative. 8. See the Typical Application - Calculate the C1 as the following : (See Figure 2) 37.5 VOUT(V) C1(pF) = (0.24 ESR(m) + 34.2) COUT(F) 1+ .. (7) R1(k) - Connect the one pin of the R2 to the GND of APL5913 - Connect the one pin of R1 to the Pin 3 of APL5913 Where R1=R1(selected) - Connect the one pin of C1 to the Pin 3 of APL5913 Select a proper C1(selected) to be a little smaller than the calculated C1. - The C1 calculated from equation (7) must meet VCNTL CCNTL the following equation : CIN VCNTL 1.25 VOUT (V) C1(pF) 0.033 + ESR(m ) COUT (F) .(8) R1(k ) VIN VIN APL5913 Where R1=R1(calculated) from equation (6) VOUT VOUT VOUT If the C1(calculated) can not meet the equation (8), please use the Condition 2. COUT C1 R1 FB Load GND - Use equation (2) to calculate the R2. R2 The reason to have three conditions described above is to optimize the load transient responses for all kinds of the output capacitor. For stability only, the Condition 2, Figure 2 regardless of equation (5), is enough for all kinds of output capacitor. Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 14 www.anpec.com.tw APL5913 Application Information (Cont.) Thermal Consideration See Figure 3. The SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top VIN plane. The copper of the VIN plane on the Top layer conducts heat into the PCB and air. Please enlarge the area to reduce the case-to-ambient resistance (CA). 102 mil 118 mil 1 8 2 7 SOP-8-P SOP-8P 3 6 5 4 Top VOUT plane Die Exposed Pad Top VIN plane Ambient Air PCB Figure 3 Recommended Minimum Footprint 8 7 6 5 0.072 0.024 0.118 0.212 0.138 1 2 0.050 3 4 Unit : Inch Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 15 www.anpec.com.tw APL5913 Package Information SOP-8P D SEE VIEW A E E1 THERMAL PAD E2 D1 h X 45 c A 0.25 b L 0 GAUGE PLANE SEATING PLANE A1 A2 e VIEW A S Y M B O L SOP-8P MILLIMETERS MIN. INCHES MAX. MAX. MIN. 0.063 A 1.60 A1 0.00 0.15 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 D1 2.25 3.50 0.098 0.138 0.006 0.000 0.049 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 e h 1.27 BSC 0.25 0.050 BSC 0.50 0.010 0.020 0.050 8o L 0.40 1.27 0.016 0 0o 8o 0o Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 16 www.anpec.com.tw APL5913 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8(P) A 330.0 2.00 P0 4.00.10 H T1 C d D W E1 F 12.4+2.00 13.0+0.50 0.30 1.750.10 5.5 0.05 50 MIN. 1.5 MIN. 20.2 MIN. 12.0 -0.00 -0.20 P1 P2 D0 D1 T A0 B0 K0 1.5+0.10 0.6+0.00 8.00.10 2.0 0.05 6.40 0.20 5.20 0.20 2.10 0.20 1.5 MIN. -0.00 -0.40 (mm) Devices Per Unit Package Type SOP- 8P Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 Quantity 2500 17 www.anpec.com.tw APL5913 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3C/second max. 3C/second max. 100C 150C 60-120 seconds 150C 200C 60-180 seconds 183C 60-150 seconds 217C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 18 www.anpec.com.tw APL5913 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5C 2.5 mm 225 +0/-5C 3 Volume mm 350 225 +0/-5C 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.7 - Apr., 2008 19 www.anpec.com.tw