LM2767M5NOPB - NATIONAL SEMICONDUCTOR

LM2745 / LM2748

January 18, 2012

Synchronous Buck Controller with Pre-Bias Startup, and

Optional Clock Synchronization

General Description

The LM2745/8 are high-speed synchronous buck regulator

controllers with an accurate feedback voltage accuracy of

±1.5%. It can provide simple down conversion to output volt-

ages as low as 0.6V. Though the control sections of the IC

are rated for 3 to 6V, the driver sections are designed to ac-

cept input supply rails as high as 14V. The use of adaptive

non-overlapping MOSFET gate drivers helps avoid potential

shoot-through problems while maintaining high efficiency.

The IC is designed for the more cost-effective option of driving

only N-channel MOSFETs in both the high-side and low-side

positions. It senses the low-side switch voltage drop for pro-

viding a simple, adjustable current limit.

The LM2745/8 features a fixed-frequency voltage-mode

PWM control architecture which is adjustable from 50 kHz to

1 MHz with one external resistor. In addition, the LM2745 also

allows the switching frequency to be synchronized to an ex-

ternal clock signal over the range of 250 kHz to 1 MHz. This

wide range of switching frequency gives the power supply

designer the flexibility to make better tradeoffs between com-

ponent size, cost and efficiency.

Features include the ability to startup with a pre-biased load

on the output, soft-start, input undervoltage lockout (UVLO)

and Power Good (based on both undervoltage and overvolt-

age detection). In addition, the shutdown pin of the IC can be

used for providing startup delay, and the soft-start pin can be

used for implementing precise tracking, for the purpose of

sequencing with respect to an external rail.

Features

■Switching frequency from 50 kHz to 1 MHz

■Switching frequency synchronize range 250 kHz to 1 MHz

(LM2745 Only)

■Startup with a pre-biased output load

■Power stage input voltage from 1V to 14V

■Control stage input voltage from 3V to 6V

■Output voltage adjustable down to 0.6V

■Power Good flag and shutdown

■Output overvoltage and undervoltage detection

■±1.5% feedback voltage accuracy over temperature

■Low-side adjustable current sensing

■Adjustable soft-start

■Tracking and sequencing with shutdown and soft start pins

■TSSOP-14 package

Applications

■Down Conversion from 3.3V

■Cable Modem, DSL and ADSL

■Laser Jet and Ink Jet Printers

■Low Voltage Power Modules

■DSP, ASIC, Core and I/O

Typical Application

20137401

LM2745/8 Synchronous Buck Controller with Pre-Bias Startup, and Optional Clock

Synchronization

Connection Diagrams

20137490

14-Lead Plastic TSSOP

θJA = 155°C/W

NS Package Number MTC14

20137402

14-Lead Plastic TSSOP

θJA = 155°C/W

NS Package Number MTC14

Ordering Information

Order Number Package Type NSC Package Drawing Supplied As

LM2745MTC

TSSOP-14 MTC14

94 Units on Rail

LM2745MTCX 2500 Units on Tape and Reel

LM2748MTC 94 Units on Rail

LM2748MTCX 2500 Units on Tape and Reel

Pin Descriptions

BOOT (Pin 1) - Bootstrap pin. This is the supply rail for the

high-side gate driver. When the high-side MOSFET turns on,

the voltage on this pin should be at least one gate threshold

above the regulator input voltage VIN to properly turn on the

MOSFET. See MOSFET Gate Drivers in the Application In-

formation section for more details on how to select MOSFETs.

LG (Pin 2) - Low-gate drive pin. This is the gate drive for the

low-side N-channel MOSFET. This signal is interlocked with

the high-side gate drive HG (Pin 14), so as to avoid shoot-

through.

PGND (Pins 3, 13) - Power ground. This is also the ground

for the low-side MOSFET driver. Both the pins must be con-

nected together on the PCB and form a ground plane, which

is usually also the system ground.

SGND (Pin 4) - Signal ground. It should be connected ap-

propriately to the ground plane with due regard to good layout

practices in switching power regulator circuits.

VCC (Pin 5) Supply rail for the control sections of the IC.

PWGD (Pin 6) - Power Good pin. This is an open drain output,

which is typically meant to be connected to VCC or any other

low voltage source through a pull-up resistor. Choose the pull-

up resistor so that the current going into this pin is kept below

1 mA. A recommended value for the pull-up resistor is 100

kΩ for most applications. The voltage on this pin is thus pulled

low under output undervoltage or overvoltage fault conditions

and also under input UVLO.

ISEN (Pin 7) - Current limit threshold setting pin. This sources

a fixed 40 µA current. A resistor of appropriate value should

be connected between this pin and the drain of the low-side

MOSFET (switch node). The minimum value for this resistor

is 1 kΩ.

EAO (Pin 8) - Output of the error amplifier. The voltage level

on this pin is compared with an internally generated ramp

signal to determine the duty cycle. This pin is necessary for

compensating the control loop.

SS/TRACK (Pin 9) - Soft-start and tracking pin. This pin is

internally connected to the non-inverting input of the error

amplifier during soft-start, and in fact any time the SS/TRACK

pin voltage happens to be below the internal reference volt-

age. For the basic soft-start function, a capacitor of minimum

value 1 nF is connected from this pin to ground. To track the

rising ramp of another power supply’s output, connect a re-

sistor divider from the output of that supply to this pin as

described in Application Information.

FB (Pin 10) - Feedback pin. This is the inverting input of the

error amplifier, which is used for sensing the output voltage

and compensating the control loop.

FREQ/SYNC (Pin 11) - Frequency adjust pin. The switching

frequency is set by connecting a resistor of suitable value be-

tween this pin and ground. Some typical values (rounded up

to the nearest standard values) are 150 kΩ for 200 kHz, 100

kΩ for 300 kHz, 51.1 kΩ for 500 kHz, 18.7 kΩ for 1 MHz. This

pin is also used in the LM2745 to synchronize to an external

clock.

SD (Pin 12) - IC shutdown pin. Pull this pin to VCC to ensure

the IC is enabled. Connect to ground to disable the IC. Under

shutdown, both high-side and low-side drives are off. This pin

also features a precision threshold for power supply sequenc-

ing purposes, as well as a low threshold to ensure minimal

quiescent current.

HG (Pin 14) - High-gate drive pin. This is the gate drive for

the high-side N-channel MOSFET. This signal is interlocked

with LG (Pin 2) to avoid shoot-through.

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LM2745/8

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

VCC -0.3 to 7V

BOOT Voltage -0.3 to 18V

ISEN -0.3 to 14V

FREQ/SYNC Voltage -0.5 to VCC + 0.3V

All other pins -0.3 to VCC + 0.3V

Junction Temperature 150°C

Storage Temperature −65°C to 150°C

Soldering Information

Lead Temperature (soldering, 10sec) 260°C

Infrared or Convection (20sec) 235°C

ESD Rating (Note 3) 2kV

Operating Ratings

Supply Voltage Range, VCC (Note 2)3V to 6V

BOOT Voltage Range 1V to 17V

Junction Temperature Range (TJ) −40°C to

+125°C

Thermal Resistance (θJA)155°C/W

Electrical Characteristics

VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in

boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design,

test, or statistical analysis.

Symbol Parameter Conditions Min Typ Max Units

VFB FB Pin Voltage VCC = 3V to 6V 0.591 0.6 0.609 V

VON UVLO Thresholds VCC Rising

VCC Falling

2.79

2.42

IQ_VCC

Operating VCC Current

VCC = 3.3V, VSD = 3.3V

fSW = 600 kHz

LM2745 1.1 1.7 2.3

LM2748 1.0 1.5 2.1

VCC = 5V, VSD = 3.3V

fSW = 600 kHz

LM2745 1.3 22.6

LM2748 1.0 1.8 2.6

Shutdown VCC Current VCC = 3.3V, VSD = 0V 1 3µA

tPWGD1 PWGD Pin Response Time VFB Rising 10 µs

tPWGD2 PWGD Pin Response Time VFB Falling 10 µs

ISS-ON SS Pin Source Current VSS = 0V 710 14 µA

ISS-OC SS Pin Sink Current During Over

Current

VSS = 2.0V 90 µA

ISEN-TH ISEN Pin Source Current Trip Point 25 40 55 µA

IFB FB Pin Current Sourcing 20 nA

ERROR AMPLIFIER

GBW Error Amplifier Unity Gain Bandwidth 9 MHz

G Error Amplifier DC Gain 118 dB

SR Error Amplifier Slew Rate 2 V/µs

IEAO EAO Pin Current Sourcing and

Sinking Capability

VEAO Error Amplifier Output Voltage Minimum 1 V

Maximum 2.2 V

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LM2745/8

Symbol Parameter Conditions Min Typ Max Units

GATE DRIVE

IQ-BOOT BOOT Pin Quiescent Current VBOOT = 12V, VSD = 0 18 90 µA

RHG_UP High-Side MOSFET Driver Pull-Up

ON resistance VBOOT = 5V @ 350 mA Sourcing 2.7 Ω

RHG_DN High-Side MOSFET Driver Pull-

Down ON resistance 350 mA Sinking 0.8 Ω

RLG_UP Low-Side MOSFET Driver Pull-Up

ON resistance VBOOT = 5V @ 350 mA Sourcing 2.7 Ω

RLG_DN Low-Side MOSFET Driver Pull-

Down ON resistance 350 mA Sinking 0.8 Ω

OSCILLATOR

fSW

PWM Frequency

RFADJ = 750 kΩ 50

kHz

RFADJ = 100 kΩ 300

RFADJ = 42.2 kΩ475 600 725

RFADJ = 18.7 kΩ 1000

LM2745 External Synchronizing

Signal Frequency Voltage Swing = 0V to VCC 250 1000

SYNCL

LM2745 Synchronization Signal Low

Threshold fSW = 250 kHz to 1 MHz 1 V

SYNCH

LM2745 Synchronization Signal

High Threshold fSW = 250 kHz to 1 MHz 2 V

DMAX Max High-Side Duty Cycle fSW = 300 kHz

fSW = 600 kHz

fSW = 1 MHz

LOGIC INPUTS AND OUTPUTS

VSTBY-IH Standby High Trip Point VFB = 0.575V, VBOOT = 3.3V

VSD Rising

1.1 V

VSTBY-IL Standby Low Trip Point VFB = 0.575V, VBOOT = 3.3V

VSD Falling

0.232 V

VSD-IH SD Pin Logic High Trip Point VSD Rising 1.3 V

VSD-IL SD Pin Logic Low Trip Point VSD Falling 0.8 V

VPWGD-TH-LO PWGD Pin Trip Points VFB Falling 0.408 0.434 0.457 V

VPWGD-TH-HI PWGD Pin Trip Points VFB Rising 0.677 0.710 0.742 V

VPWGD-HYS PWGD Hysteresis VFB Falling

VFB Rising

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device

operates correctly. Operating Ratings do not imply guaranteed performance limits.

Note 2: The power MOSFETs can run on a separate 1V to 14V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the external MOSFET.

See the MOSFET GATE DRIVERS section under Application Information for further details.

Note 3: ESD using the human body model which is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin.

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LM2745/8

Typical Performance Characteristics

Efficiency (VOUT = 1.2V)

VCC = 3.3V, fSW = 1 MHz

20137440

Internal Reference Voltage vs Temperature

20137458

Frequency vs Temperature

20137460

Output Voltage vs Output Current

20137456

Switch Waveforms

VCC = 3.3V, VIN = 5V, VOUT = 1.2V

IOUT = 3A, CSS = 12 nF, fSW = 1 MHz

20137446

Start-Up (Full-Load)

VCC = 3.3V, VIN = 5V, VOUT = 1.2V

IOUT = 3A, CSS = 12 nF, fSW = 1 MHz

20137448

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LM2745/8

Start-Up (No-Load)

VCC = 3.3V, VIN = 5V, VOUT = 1.2V

CSS = 12 nF, fSW = 1 MHz

20137449

Shutdown (Full-Load)

VCC = 3.3V, VIN = 5V, VOUT = 1.2V

IOUT = 3A, CSS = 12 nF, fSW = 1 MHz

20137450

Load Transient Response

VCC = 3.3V, VIN = 14V, VOUT = 1.2V

fSW = 1 MHz

20137453

Line Transient Response (VIN = 3V to 9V)

VCC = 3.3V, VOUT = 1.2V

IOUT = 2A, fSW = 1 MHz

20137454

Frequency vs. Frequency Adjust Resistor

20137455

Maximum Duty Cycle vs Frequency

VCC = 3.3V

20137492

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LM2745/8

Maximum Duty Cycle vs VCC

fSW = 600 kHz

20137493

Maximum Duty Cycle vs VCC

fSW = 1 MHz

20137494

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LM2745/8

Block Diagram

20137403

Application Information

The LM2745/8 is a voltage-mode, high-speed synchronous

buck regulator with a PWM control scheme. It is designed for

use in set-top boxes, thin clients, DSL/Cable modems, and

other applications that require high efficiency buck convert-

ers. It has output shutdown (SD), input undervoltage lock-out

(UVLO) mode and power good (PWGD) flag (based on over-

voltage and undervoltage detection). The overvoltage and

undervoltage signals are OR-gated to drive the power good

signal and provide a logic signal to the system if the output

voltage goes out of regulation. Current limit is achieved by

sensing the voltage VDS across the low side MOSFET. The

LM2745/8 is also able to start-up with the output pre-biased

with a load. The LM2745 also allows for the switching fre-

quency to be synchronized with an external clock source.

START UP/SOFT-START

When VCC exceeds 2.79V and the shutdown pin (SD) sees a

logic high, the soft-start period begins. Then an internal, fixed

10 µA source begins charging the soft-start capacitor. During

soft-start the voltage on the soft-start capacitor CSS is con-

nected internally to the non-inverting input of the error ampli-

fier. The soft-start period lasts until the voltage on the soft-

start capacitor exceeds the LM2745/8 reference voltage of

0.6V. At this point the reference voltage takes over at the non-

inverting error amplifier input. The capacitance of CSS deter-

mines the length of the soft-start period, and can be

approximated by:

Where CSS is in µF and tSS is in ms.

During soft start the Power Good flag is forced low and it is

released when the FB pin voltage reaches 70% of 0.6V. At

this point the chip enters normal operation mode, and the

output overvoltage and undervoltage monitoring starts.

SETTING THE OUTPUT VOLTAGE

The LM2745/8 regulates the output voltage by controlling the

duty cycle of the high side and low side MOSFETs (see Typ-

ical Application Circuit).The equation governing output volt-

age is:

SETTING THE SWITCHING FREQUENCY

During fixed-frequency mode of operation the PWM frequen-

cy is adjustable between 50 kHz and 1 MHz and is set by an

external resistor, RFADJ, between the FREQ/SYNC pin and

ground. The resistance needed for a desired frequency is ap-

proximated by the curve FREQUENCY vs. FREQUENCY

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LM2745/8

ADJUST RESISTOR in the Typical Performance Character-

istics section.

When it is desired to synchronize the switching frequency with

an external clock source, the LM2745 has the unique ability

to synchronize from this external source within the range of

250 kHz to 1 MHz. The external clock signal should be AC

coupled to the FREQ/SYNC pin as shown below in Figure 1,

where the RFADJ is chosen so that the fixed frequency is ap-

proximately within ±30% of the external synchronizing clock

frequency. An internal protection diode clamps the low level

of the synchronizing signal to approximately -0.5V. The inter-

nal clock sychronizes to the rising edge of the external clock.

20137489

FIGURE 1. AC Coupled Clock

It is recommended to choose an AC coupling capacitance in

the range of 50 pF to 100 pF. Exceeding the recommended

capacitance may inject excessive energy through the internal

clamping diode structure present on the FREQ/SYNC pin.

The typical trip level of the synchronization pin is 1.5V. To

ensure proper synchronization and to avoid damaging the IC,

the peak-to-peak value (amplitude) should be between 2.5V

and VCC. The minimum width of this pulse must be greater

than 100 ns, and it's maximum width must be 100ns less than

the period of the switching cycle.

The external clock synchronization process begins once the

LM2745 is enabled and an external clock signal is detected.

During the external clock synchronization process the internal

clock initially switches at approximately 1.5 MHz and de-

creases until it has matched the external clock’s frequency.

The lock-in period is approximately 30 µs if the external clock

is switching at 1 MHz, and about 100 µs if the external clock

is at 200 kHz. When there is no clock signal present, the

LM2745 enters into fixed-frequency mode and begins switch-

ing at the frequency set by the RFADJ resistor. If the external

clock signal is removed after frequency synchronization, the

LM2745 will enter fixed-frequency mode within two clock cy-

cles. If the external clock is removed within the 30 µs lock-in

period, the LM2745 will re-enter fixed-frequency mode within

two internal clock cycles after the lock-in period.

OUTPUT PRE-BIAS STARTUP

If there is a pre-biased load on the output of the LM2745/8

during startup, the IC will disable switching of the low-side

MOSFET and monitor the SW node voltage during the off-

time of the high-side MOSFET. There is no load current

sensing while in pre-bias mode because the low-side MOS-

FET never turns on. The IC will remain in this pre-bias mode

until it sees the SW node stays below 0V during the entire

high-side MOSFET's off-time. Once it is determined that the

SW node remained below 0V during the high-side off-time,

the low-side MOSFET begins switching during the next

switching cycle. Figure 2 shows the SW node, HG, and LG

signals during pre-bias startup. The pre-biased output voltage

should not exceed VCC + VGS of the external High-Side MOS-

FET to ensure that the High-Side MOSFET will be able to

switch during startup.

20137491

FIGURE 2. Output Pre-Bias Mode Waveforms

TRACKING A VOLTAGE LEVEL

The LM2745/8 can track the output of a master power supply

during soft-start by connecting a resistor divider to the SS/

TRACK pin. In this way, the output voltage slew rate of the

LM2745/8 will be controlled by the master supply for loads

that require precise sequencing. When the tracking function

is used no soft-start capacitor should be connected to the SS/

TRACK pin. However in all other cases, a CSS value of at least

1 nF between the soft-start pin and ground should be used.

20137407

FIGURE 3. Tracking Circuit

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LM2745/8

One way to use the tracking feature is to design the tracking

resistor divider so that the master supply’s output voltage

(VOUT1) and the LM2745/8’s output voltage (represented sym-

bolically in Figure 3 as VOUT2, i.e. without explicitly showing

the power components) both rise together and reach their

target values at the same time. For this case, the equation

governing the values of the tracking divider resistors RT1 and

RT2 is:

The current through RT1 should be about 4 mA for precise

tracking. The final voltage of the SS/TRACK pin should be set

higher than the feedback voltage of 0.6V (say about 0.65V as

in the above equation). If the master supply voltage was 5V

and the LM2745/8 output voltage was 1.8V, for example, then

the value of RT1 needed to give the two supplies identical soft-

start times would be 150Ω. A timing diagram for the equal soft-

start time case is shown in Figure 4.

20137408

FIGURE 4. Tracking with Equal Soft-Start Time

TRACKING A VOLTAGE SLEW RATE

The tracking feature can alternatively be used not to make

both rails reach regulation at the same time but rather to have

similar rise rates (in terms of output dV/dt). This method en-

sures that the output voltage of the LM2745/8 always reaches

regulation before the output voltage of the master supply. In

this case, the tracking resistors can be determined based on

the following equation:

For the example case of VOUT1 = 5V and VOUT2 = 1.8V, with

RT1 set to 150Ω as before, RT2 is calculated from the above

equation to be 265Ω. A timing diagram for the case of equal

slew rates is shown in Figure 5.

20137410

FIGURE 5. Tracking with Equal Slew Rates

SEQUENCING

The start up/soft-start of the LM2745/8 can be delayed for the

purpose of sequencing by connecting a resistor divider from

the output of a master power supply to the SD pin, as shown

in Figure 6.

20137414

FIGURE 6. Sequencing Circuit

A desired delay time tDELAY between the startup of the master

supply output voltage and the LM2745/8 output voltage can

be set based on the SD pin low-to-high threshold VSD-IH and

the slew rate of the voltage at the SD pin, SRSD:

tDELAY = VSD-IH / SRSD

Note again, that in Figure 6, the LM2745/8’s output voltage

has been represented symbolically as VOUT2, i.e. without ex-

plicitly showing the power components.

VSD-IH is typically 1.08V and SRSD is the slew rate of the SD

pin voltage. The values of the sequencing divider resistors

RS1 and RS2 set the SRSD based on the master supply output

voltage slew rate, SROUT1, using the following equation:

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LM2745/8

For example, if the master supply output voltage slew rate

was 1V/ms and the desired delay time between the startup of

the master supply and LM2745/8 output voltage was 5 ms,

then the desired SD pin slew rate would be (1.08V/5 ms) =

0.216V/ms. Due to the internal impedance of the SD pin, the

maximum recommended value for RS2 is 1 kΩ. To achieve

the desired slew rate, RS1 would then be 274Ω. A timing dia-

gram for this example is shown in Figure 7.

20137411

FIGURE 7. Delay for Sequencing

SD PIN IMPEDANCE

When connecting a resistor divider to the SD pin of the

LM2745/8 some care has to be taken. Once the SD voltage

goes above VSD-IH, a 17 µA pull-up current is activated as

shown in Figure 8. This current is used to create the internal

hysteresis (≊170 mV); however, high external impedances

will affect the SD pin logic thresholds as well. The external

impedance used for the sequencing divider network should

preferably be a small fraction of the impedance of the SD pin

for good performance (around 1 kΩ).

20137406

FIGURE 8. SD Pin Logic

MOSFET GATE DRIVERS

The LM2745/8 has two gate drivers designed for driving N-

channel MOSFETs in a synchronous mode. Note that unlike

most other synchronous controllers, the bootstrap capacitor

of the LM2745/8 provides power not only to the driver of the

upper MOSFET, but the lower MOSFET driver too (both

drivers are ground referenced, i.e. no floating driver).

Two things must be kept in mind here. First, the BOOT pin

has an absolute maximum rating of 18V. This must never be

exceeded, even momentarily. Since the bootstrap capacitor

is connected to the SW node, the peak voltage impressed on

the BOOT pin is the sum of the input voltage (VIN) plus the

voltage across the bootstrap capacitor (ignoring any forward

drop across the bootstrap diode). The bootstrap capacitor is

charged up by a given rail (called VBOOT_DC here) whenever

the upper MOSFET turns off. This rail can be the same as

VCC or it can be any external ground-referenced DC rail. But

care has to be exercised when choosing this bootstrap DC

rail that the BOOT pin is not damaged. For example, if the

desired maximum VIN is 14V, and VBOOT_DC is chosen to be

the same as VCC, then clearly if the VCC rail is 6V, the peak

voltage on the BOOT pin is 14V + 6V = 20V. This is unac-

ceptable, as it is in excess of the rating of the BOOT pin. A

VCC of 3V would be acceptable in this case. Or the VIN range

must be reduced accordingly. There is also the option of de-

riving the bootstrap DC rail from another 3V external rail,

independent of VCC.

The second thing to be kept in mind here is that the output of

the low-side driver swings between the bootstrap DC rail level

of VBOOT_DC and Ground, whereas the output of the high-side

driver swings between VIN+ VBOOT_DC and Ground. To keep

the high-side MOSFET fully on when desired, the Gate pin

voltage of the MOSFET must be higher than its instantaneous

Source pin voltage by an amount equal to the 'Miller plateau'.

It can be shown that this plateau is equal to the threshold

voltage of the chosen MOSFET plus a small amount equal to

Io/g. Here Io is the maximum load current of the application,

and g is the transconductance of this MOSFET (typically

about 100 for logic-level devices). That means we must

choose VBOOT_DC to at least exceed the Miller plateau level.

This may therefore affect the choice of the threshold voltage

of the external MOSFETs, and that in turn may depend on the

chosen VBOOT_DC rail.

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LM2745/8

So far, in the discussion above, the forward drop across the

bootstrap diode has been ignored. But since that does affect

the output of the driver somewhat, it is a good idea to include

this drop in the following examples. Looking at the Typical

Application schematic, this means that the difference voltage

VCC - VD1, which is the voltage the bootstrap capacitor

charges up to, must always be greater than the maximum tol-

erance limit of the threshold voltage of the upper MOSFET.

Here VD1 is the forward voltage drop across the bootstrap

diode D1. This may place restrictions on the minimum input

voltage and/or type of MOSFET used.

A basic bootstrap circuit can be built using one Schottky diode

and a small capacitor, as shown in Figure 9. The capacitor

CBOOT serves to maintain enough voltage between the top

MOSFET gate and source to control the device even when

the top MOSFET is on and its source has risen up to the input

voltage level. The charge pump circuitry is fed from VCC,

which can operate over a range from 3.0V to 6.0V. Using this

basic method the voltage applied to the gates of both high-

side and low-side MOSFETs is VCC - VD. This method works

well when VCC is 5V±10%, because the gate drives will get at

least 4.0V of drive voltage during the worst case of VCC-MIN =

4.5V and VD-MAX = 0.5V. Logic level MOSFETs generally

specify their on-resistance at VGS = 4.5V. When VCC = 3.3V

±10%, the gate drive at worst case could go as low as 2.5V.

Logic level MOSFETs are not guaranteed to turn on, or may

have much higher on-resistance at 2.5V. Sub-logic level

MOSFETs, usually specified at VGS = 2.5V, will work, but are

more expensive, and tend to have higher on-resistance. The

circuit in Figure 9 works well for input voltages ranging from

1V up to 14V and VCC = 5V±10%, because the drive voltage

depends only on VCC.

20137412

FIGURE 9. Basic Charge Pump (Bootstrap)

Note that the LM2745/8 can be paired with a low cost linear

regulator like the LM78L05 to run from a single input rail be-

tween 6.0 and 14V. The 5V output of the linear regulator

powers both the VCC and the bootstrap circuit, providing effi-

cient drive for logic level MOSFETs. An example of this circuit

is shown in Figure 10.

20137413

FIGURE 10. LM78L05 Feeding Basic Charge Pump

Figure 11 shows a second possibility for bootstrapping the

MOSFET drives using a doubler. This circuit provides an

equal voltage drive of VCC - 3VD + VIN to both the high-side

and low-side MOSFET drives. This method should only be

used in circuits that use 3.3V for both VCC and VIN. Even with

VIN = VCC = 3.0V (10% lower tolerance on 3.3V) and VD = 0.5V

both high-side and low-side gates will have at least 4.5V of

drive. The power dissipation of the gate drive circuitry is di-

rectly proportional to gate drive voltage, hence the thermal

limits of the LM2745/8 IC will quickly be reached if this circuit

is used with VCC or VIN voltages over 5V.

20137419

FIGURE 11. Charge Pump with Added Gate Drive

All the gate drive circuits shown in the above figures typically

use 100 nF ceramic capacitors in the bootstrap locations.

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LM2745/8

POWER GOOD SIGNAL

The open drain output on the Power Good pin needs a pull-

up resistor to a low voltage source. The pull-up resistor should

be chosen so that the current going into the Power Good pin

is less than 1 mA. A 100 kΩ resistor is recommended for most

applications.

The Power Good signal is an OR-gated flag which takes into

account both output overvoltage and undervoltage condi-

tions. If the feedback pin (FB) voltage is 18% above its nom-

inal value (118% x VFB = 0.708V) or falls 28% below that value

(72% x VFB = 0.42V) the Power Good flag goes low. The

Power Good flag can be used to signal other circuits that the

output voltage has fallen out of regulation, however the

switching of the LM2745/8 continues regardless of the state

of the Power Good signal. The Power Good flag will return to

logic high whenever the feedback pin voltage is between 72%

and 118% of 0.6V.

UVLO

The 2.79V turn-on threshold on VCC has a built in hysteresis

of about 300 mV. If VCC drops below 2.42V, the chip definitely

enters UVLO mode. UVLO consists of turning off the top and

bottom MOSFETS and remaining in that condition until VCC

rises above 2.79V. As with normal shutdown initiated by the

SD pin, the soft-start capacitor is discharged through an in-

ternal MOSFET, ensuring that the next start-up will be con-

trolled by the soft-start circuitry.

CURRENT LIMIT

Current limit is realized by sensing the voltage across the low-

side MOSFET while it is on. The RDSON of the MOSFET is a

known value; hence the current through the MOSFET can be

determined as:

VDS = IOUT x RDSON

The current through the low-side MOSFET while it is on is also

the falling portion of the inductor current. The current limit

threshold is determined by an external resistor, RCS, connect-

ed between the switching node and the ISEN pin. A constant

current (ISEN-TH) of 40 µA typical is forced through RCS, caus-

ing a fixed voltage drop. This fixed voltage is compared

against VDS and if the latter is higher, the current limit of the

chip has been reached. To obtain a more accurate value for

RCS you must consider the operating values of RDSON and

ISEN-TH at their operating temperatures in your application and

the effect of slight parameter differences from part to part.

RCS can be found by using the following equation using the

RDSON value of the low side MOSFET at it's expected hot

temperature and the absolute minimum value expected over

the full temperature range for the for the ISEN-TH which is 25

µA:

RCS = RDSON-HOT x ILIM / ISEN-TH

For example, a conservative 15A current limit in a 10A design

with a RDSON-HOT of 10 mΩ would require a 6 kΩ resistor. The

minimum value for RCS in any application is 1 kΩ. Because

current sensing is done across the low-side MOSFET, no

minimum high-side on-time is necessary. The LM2745/8 en-

ters current limit mode if the inductor current exceeds the

current limit threshold at the point where the high-side MOS-

FET turns off and the low-side MOSFET turns on. (The point

of peak inductor current, see Figure 12). Note that in normal

operation mode the high-side MOSFET always turns on at the

beginning of a clock cycle. In current limit mode, by contrast,

the high-side MOSFET on-pulse is skipped. This causes in-

ductor current to fall. Unlike a normal operation switching

cycle, however, in a current limit mode switching cycle the

high-side MOSFET will turn on as soon as inductor current

has fallen to the current limit threshold. The LM2745/8 will

continue to skip high-side MOSFET pulses until the inductor

current peak is below the current limit threshold, at which point

the system resumes normal operation.

20137488

FIGURE 12. Current Limit Threshold

Unlike a high-side MOSFET current sensing scheme, which

limits the peaks of inductor current, low-side current sensing

is only allowed to limit the current during the converter off-

time, when inductor current is falling. Therefore in a typical

current limit plot the valleys are normally well defined, but the

peaks are variable, according to the duty cycle. The PWM

error amplifier and comparator control the off-pulse of the

high-side MOSFET, even during current limit mode, meaning

that peak inductor current can exceed the current limit thresh-

old. Assuming that the output inductor does not saturate, the

maximum peak inductor current during current limit mode can

be calculated with the following equation:

Where TSW is the inverse of switching frequency fSW. The 200

ns term represents the minimum off-time of the duty cycle,

which ensures enough time for correct operation of the cur-

rent sensing circuitry.

In order to minimize the time period in which peak inductor

current exceeds the current limit threshold, the IC also dis-

charges the soft-start capacitor through a fixed 90 µA sink.

The output of the LM2745/8 internal error amplifier is limited

by the voltage on the soft-start capacitor. Hence, discharging

the soft-start capacitor reduces the maximum duty cycle D of

the controller. During severe current limit this reduction in duty

cycle will reduce the output voltage if the current limit condi-

tions last for an extended time. Output inductor current will be

reduced in turn to a flat level equal to the current limit thresh-

old. The third benefit of the soft-start capacitor discharge is a

13 www.ti.com

LM2745/8

smooth, controlled ramp of output voltage when the current

limit condition is cleared.

SHUTDOWN

If the shutdown pin is pulled low, (below 0.8V) the LM2745/8

enters shutdown mode, and discharges the soft-start capac-

itor through a MOSFET switch. The high and low-side MOS-

FETs are turned off. The LM2745/8 remains in this state as

long as VSD sees a logic low (see the Electrical Characteristics

table). To assure proper IC start-up the shutdown pin should

not be left floating. For normal operation this pin should be

connected directly to VCC or to another voltage between 1.3V

to VCC (see the Electrical Characteristics table).

DESIGN CONSIDERATIONS

The following is a design procedure for all the components

needed to create the Typical Application Circuit shown on the

front page. This design converts 3.3V (VIN) to 1.2V (VOUT) at

a maximum load of 4A with an efficiency of 89% and a switch-

ing frequency of 300 kHz. The same procedures can be

followed to create many other designs with varying input volt-

ages, output voltages, and load currents.

Input Capacitor

The input capacitors in a Buck converter are subjected to high

stress due to the input current trapezoidal waveform. Input

capacitors are selected for their ripple current capability and

their ability to withstand the heat generated since that ripple

current passes through their ESR. Input rms ripple current is

approximately:

Where duty cycle D = VOUT/VIN.

The power dissipated by each input capacitor is:

where n is the number of paralleled capacitors, and ESR is

the equivalent series resistance of each capacitor. The equa-

tion above indicates that power loss in each capacitor de-

creases rapidly as the number of input capacitors increases.

The worst-case ripple for a Buck converter occurs during full

load and when the duty cycle (D) is 0.5. For this 3.3V to 1.2V

design the duty cycle is 0.364. For a 4A maximum load the

ripple current is 1.92A.

Output Inductor

The output inductor forms the first half of the power stage in

a Buck converter. It is responsible for smoothing the square

wave created by the switching action and for controlling the

output current ripple (ΔIOUT). The inductance is chosen by

selecting between tradeoffs in efficiency and response time.

The smaller the output inductor, the more quickly the con-

verter can respond to transients in the load current. However,

as shown in the efficiency calculations, a smaller inductor re-

quires a higher switching frequency to maintain the same

level of output current ripple. An increase in frequency can

mean increasing loss in the MOSFETs due to the charging

and discharging of the gates. Generally the switching fre-

quency is chosen so that conduction loss outweighs switching

loss. The equation for output inductor selection is:

L = 1.6 µH

Here we have plugged in the values for output current ripple,

input voltage, output voltage, switching frequency, and as-

sumed a 40% peak-to-peak output current ripple. This yields

an inductance of 1.6 µH. The output inductor must be rated

to handle the peak current (also equal to the peak switch cur-

rent), which is (IOUT + (0.5 x ΔIOUT)) = 4.8A, for a 4A design.

The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.4A peak,

and has a direct current resistance (DCR) of 12 mΩ. After

selecting the Coilcraft DO3316P-222P for the output inductor,

actual inductor current ripple should be re-calculated with the

selected inductance value, as this information is needed to

select the output capacitor. Re-arranging the equation used

to select inductance yields the following:

VIN(MAX) is assumed to be 10% above the steady state input

voltage, or 3.6V at VIN = 3.3V. The re-calculated current ripple

will then be 1.2A. This gives a peak inductor/switch current

will be 4.6A.

Output Capacitor

The output capacitor forms the second half of the power stage

of a Buck switching converter. It is used to control the output

voltage ripple (ΔVOUT) and to supply load current during fast

load transients.

In this example the output current is 4A and the expected type

of capacitor is an aluminum electrolytic, as with the input ca-

pacitors. Other possibilities include ceramic, tantalum, and

solid electrolyte capacitors, however the ceramic type often

do not have the large capacitance needed to supply current

for load transients, and tantalums tend to be more expensive

than aluminum electrolytic. Aluminum capacitors tend to have

very high capacitance and fairly low ESR, meaning that the

ESR zero, which affects system stability, will be much lower

than the switching frequency. The large capacitance means

that at the switching frequency, the ESR is dominant, hence

the type and number of output capacitors is selected on the

basis of ESR. One simple formula to find the maximum ESR

based on the desired output voltage ripple, ΔVOUT and the

designed output current ripple, ΔIOUT, is:

www.ti.com 14

LM2745/8

In this example, in order to maintain a 2% peak-to-peak output

voltage ripple and a 40% peak-to-peak inductor current ripple,

the required maximum ESR is 20 mΩ. The Sanyo 4SP560M

electrolytic capacitor will give an equivalent ESR of 14 mΩ.

The capacitance of 560 µF is enough to supply energy even

to meet severe load transient demands.

MOSFETs

Selection of the power MOSFETs is governed by a trade-off

between cost, size, and efficiency. One method is to deter-

mine the maximum cost that can be endured, and then select

the most efficient device that fits that price. Breaking down the

losses in the high-side and low-side MOSFETs and then cre-

ating spreadsheets is one way to determine relative efficien-

cies between different MOSFETs. Good correlation between

the prediction and the bench result is not guaranteed, how-

ever. Single-channel buck regulators that use a controller IC

and discrete MOSFETs tend to be most efficient for output

currents of 2 to 10A.

Losses in the high-side MOSFET can be broken down into

conduction loss, gate charging loss, and switching loss. Con-

duction, or I2R loss, is approximately:

PC = D (IO2 x RDSON-HI x 1.3)

(High-Side MOSFET)

PC = (1 - D) x (IO2 x RDSON-LO x 1.3)

(Low-Side MOSFET)

In the above equations the factor 1.3 accounts for the in-

crease in MOSFET RDSON due to heating. Alternatively, the

1.3 can be ignored and the RDSON of the MOSFET estimated

using the RDSON Vs. Temperature curves in the MOSFET

datasheets.

Gate charging loss results from the current driving the gate

capacitance of the power MOSFETs, and is approximated as:

PGC = n x (VDD) x QG x fSW

where ‘n’ is the number of MOSFETs (if multiple devices have

been placed in parallel), VDD is the driving voltage (see MOS-

FET Gate Drivers section) and QGS is the gate charge of the

MOSFET. If different types of MOSFETs are used, the ‘n’ term

can be ignored and their gate charges simply summed to form

a cumulative QG. Gate charge loss differs from conduction

and switching losses in that the actual dissipation occurs in

the LM2745/8, and not in the MOSFET itself.

Switching loss occurs during the brief transition period as the

high-side MOSFET turns on and off, during which both current

and voltage are present in the channel of the MOSFET. It can

be approximated as:

PSW = 0.5 x VIN x IO x (tr + tf) x fSW

where tr and tf are the rise and fall times of the MOSFET.

Switching loss occurs in the high-side MOSFET only.

For this example, the maximum drain-to-source voltage ap-

plied to either MOSFET is 3.6V. The maximum drive voltage

at the gate of the high-side MOSFET is 3.1V, and the maxi-

mum drive voltage for the low-side MOSFET is 3.3V. Due to

the low drive voltages in this example, a MOSFET that turns

on fully with 3.1V of gate drive is needed. For designs of 5A

and under, dual MOSFETs in SO-8 provide a good trade-off

between size, cost, and efficiency.

Support Components

CIN2 - A small (0.1 to 1 µF) ceramic capacitor should be placed

as close as possible to the drain of the high-side MOSFET

and source of the low-side MOSFET (dual MOSFETs make

this easy). This capacitor should be X5R type dielectric or

better.

RCC, CCC- These are standard filter components designed to

ensure smooth DC voltage for the chip supply. RCC should be

1 to 10Ω. CCC should 1 µF, X5R type or better.

CBOOT- Bootstrap capacitor, typically 100 nF.

RPULL-UP – This is a standard pull-up resistor for the open-

drain power good signal (PWGD). The recommended value

is 100 kΩ connected to VCC. If this feature is not necessary,

the resistor can be omitted.

D1 - A small Schottky diode should be used for the bootstrap.

It allows for a minimum drop for both high and low-side

drivers. The MBR0520 or BAT54 work well in most designs.

RCS - Resistor used to set the current limit. Since the design

calls for a peak current magnitude (IOUT + (0.5 x ΔIOUT)) of

4.8A, a safe setting would be 6A. (This is below the saturation

current of the output inductor, which is 7A.) Following the

equation from the Current Limit section, a 1.3 kΩ resistor

should be used.

RFADJ - This resistor is used to set the switching frequency of

the chip. The resistor value is approximated from the Fre-

quency vs Frequency Adjust Resistor curve in the Typical

Performance Characteristics section. For 300 kHz operation,

a 100 kΩ resistor should be used.

CSS - The soft-start capacitor depends on the user require-

ments and is calculated based on the equation given in the

section titled START UP/SOFT-START. Therefore, for a 7 ms

delay, a 12 nF capacitor is suitable.

Control Loop Compensation

The LM2745/8 uses voltage-mode (‘VM’) PWM control to cor-

rect changes in output voltage due to line and load transients.

VM requires careful small signal compensation of the control

loop for achieving high bandwidth and good phase margin.

The control loop is comprised of two parts. The first is the

power stage, which consists of the duty cycle modulator, out-

put inductor, output capacitor, and load. The second part is

the error amplifier, which for the LM2745/8 is a 9 MHz op-amp

used in the classic inverting configuration. Figure 13 shows

the regulator and control loop components.

15 www.ti.com

LM2745/8

20137464

FIGURE 13. Power Stage and Error Amp

One popular method for selecting the compensation compo-

nents is to create Bode plots of gain and phase for the power

stage and error amplifier. Combined, they make the overall

bandwidth and phase margin of the regulator easy to see.

Software tools such as Excel, MathCAD, and Matlab are use-

ful for showing how changes in compensation or the power

stage affect system gain and phase.

The power stage modulator provides a DC gain ADC that is

equal to the input voltage divided by the peak-to-peak value

of the PWM ramp. This ramp is 1.0Vpk-pk for the LM2745/8.

The inductor and output capacitor create a double pole at fre-

quency fDP, and the capacitor ESR and capacitance create a

single zero at frequency fESR. For this example, with VIN =

3.3V, these quantities are:

In the equation for fDP, the variable RL is the power stage re-

sistance, and represents the inductor DCR plus the on resis-

tance of the top power MOSFET. RO is the output voltage

divided by output current. The power stage transfer function

GPS is given by the following equation, and Figure 14 shows

Bode plots of the phase and gain in this example.

a = LCO(RO + RC)

b = L + CO(RORL + RORC + RCRL)

c = RO + RL

20137469

20137470

FIGURE 14. Power Stage Gain and Phase

The double pole at 4.5 kHz causes the phase to drop to ap-

proximately -130° at around 10 kHz. The ESR zero, at 20.3

kHz, provides a +90° boost that prevents the phase from

dropping to -180º. If this loop were left uncompensated, the

bandwidth would be approximately 10 kHz and the phase

margin 53°. In theory, the loop would be stable, but would

suffer from poor DC regulation (due to the low DC gain) and

would be slow to respond to load transients (due to the low

bandwidth.) In practice, the loop could easily become unsta-

ble due to tolerances in the output inductor, capacitor, or

changes in output current, or input voltage. Therefore, the

loop is compensated using the error amplifier and a few pas-

sive components.

For this example, a Type III, or three-pole-two-zero approach

gives optimal bandwidth and phase.

www.ti.com 16

LM2745/8

In most voltage mode compensation schemes, including

Type III, a single pole is placed at the origin to boost DC gain

as high as possible. Two zeroes fZ1 and fZ2 are placed at the

double pole frequency to cancel the double pole phase lag.

Then, a pole, fP1 is placed at the frequency of the ESR zero.

A final pole fP2 is placed at one-half of the switching frequency.

The gain of the error amplifier transfer function is selected to

give the best bandwidth possible without violating the Nyquist

stability criteria. In practice, a good crossover point is one-fifth

of the switching frequency, or 60 kHz for this example. The

generic equation for the error amplifier transfer function is:

In this equation the variable AEA is a ratio of the values of the

capacitance and resistance of the compensation compo-

nents, arranged as shown in Figure 13. AEA is selected to

provide the desired bandwidth. A starting value of 80,000 for

AEA should give a conservative bandwidth. Increasing the

value will increase the bandwidth, but will also decrease

phase margin. Designs with 45-60° are usually best because

they represent a good trade-off between bandwidth and

phase margin. In general, phase margin is lowest and gain

highest (worst-case) for maximum input voltage and minimum

output current. One method to select AEA is to use an iterative

process beginning with these worst-case conditions.

1. Increase AEA

2. Check overall bandwidth and phase margin

3. Change VIN to minimum and recheck overall bandwidth

and phase margin

4. Change IO to maximum and recheck overall bandwidth

and phase margin

The process ends when the both bandwidth and the phase

margin are sufficiently high. For this example input voltage

can vary from 3.0 to 3.6V and output current can vary from 0

to 4A, and after a few iterations a moderate gain factor of

101dB is used.

The error amplifier of the LM2745/8 has a unity-gain band-

width of 9 MHz. In order to model the effect of this limitation,

the open-loop gain can be calculated as:

The new error amplifier transfer function that takes into ac-

count unity-gain bandwidth is:

The gain and phase of the error amplifier are shown in Figure

15.

20137474

20137475

FIGURE 15. Error Amp. Gain and Phase

In VM regulators, the top feedback resistor RFB2 forms a part

of the compensation. Setting RFB2 to 10 kΩ±1%, usually gives

values for the other compensation resistors and capacitors

that fall within a reasonable range. (Capacitances > 1 pF, re-

sistances <1 MΩ) CC1, CC2, CC3, RC1, and RC2 are selected

to provide the poles and zeroes at the desired frequencies,

using the following equations:

17 www.ti.com

LM2745/8

In practice, a good trade off between phase margin and band-

width can be obtained by selecting the closest ±10% capac-

itor values above what are suggested for CC1 and CC2, the

closest ±10% capacitor value below the suggestion for CC3,

and the closest ±1% resistor values below the suggestions

for RC1, RC2. Note that if the suggested value for RC2 is less

than 100Ω, it should be replaced by a short circuit. Following

this guideline, the compensation components will be:

CC1 = 27 pF±10%, CC2 = 820 pF±10%

CC3 = 2.7 nF±10%, RC1 = 39.2 kΩ±1%

RC2 = 2.55 kΩ±1%

The transfer function of the compensation block can be de-

rived by considering the compensation components as

impedance blocks ZF and ZI around an inverting op-amp:

As with the generic equation, GEA-ACTUAL must be modified to

take into account the limited bandwidth of the error amplifier.

The result is:

The total control loop transfer function H is equal to the power

stage transfer function multiplied by the error amplifier trans-

fer function.

H = GPS x HEA

The bandwidth and phase margin can be read graphically

from Bode plots of HEA as shown in Figure 16.

20137485

20137486

FIGURE 16. Overall Loop Gain and Phase

The bandwidth of this example circuit is 59 kHz, with a phase

margin of 60°.

EFFICIENCY CALCULATIONS

The following is a sample calculation.

A reasonable estimation of the efficiency of a switching buck

controller can be obtained by adding together the Output

Power (POUT) loss and the Total Power (PTOTAL) loss:

The Output Power (POUT) for the Typical Application Circuit

design is (1.2V x 4A) = 4.8W. The Total Power (PTOTAL), with

an efficiency calculation to complement the design, is shown

below.

The majority of the power losses are due to the low side and

high side MOSFET’s losses. The losses in any MOSFET are

group of switching (PSW) and conduction losses (PCND).

PFET = PSW + PCND = 61.38 mW + 270.42 mW

PFET = 331.8 mW

FET Switching Loss (PSW)

PSW = PSW(ON) + PSW(OFF)

PSW = 0.5 x VIN x IOUT x (tr + tf) x fSW

PSW = 0.5 x 3.3V x 4A x 300 kHz x 31 ns

PSW = 61.38 mW

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LM2745/8

The FDS6898A has a typical turn-on rise time tr and turn-off

fall time tf of 15 ns and 16 ns, respectively. The switching

losses for this type of dual N-Channel MOSFETs are 0.061W.

FET Conduction Loss (PCND)

PCND = PCND1 + PCND2

PCND1 = I2OUT x RDS(ON) x k x D

PCND2 = I2OUT x RDS(ON) x k x (1-D)

RDS(ON) = 13 mΩ and the factor is a constant value (k = 1.3)

to account for the increasing RDS(ON) of a FET due to heating.

PCND1 = (4A)2 x 13 mΩ x 1.3 x 0.364

PCND2 = (4A)2 x 13 mΩ x 1.3 x (1 - 0.364)

PCND = 98.42 mW + 172 mW = 270.42 mW

There are few additional losses that are taken into account:

IC Operating Loss (PIC)

PIC = IQ_VCC x VCC,

where IQ-VCC is the typical operating VCC current

PIC= 1.7 mA x 3.3V = 5.61 mW

FET Gate Charging Loss (PGATE)

PGATE = n x VCC x QGS x fSW

PGATE = 2 x 3.3V x 3 nC x 300 kHz

PGATE = 5.94 mW

The value n is the total number of FETs used and QGS is the

typical gate-source charge value, which is 3 nC. For the FD-

S6898A the gate charging loss is 5.94 mW.

Input Capacitor Loss (PCAP)

where,

Here n is the number of paralleled capacitors, ESR is the

equivalent series resistance of each, and PCAP is the dissipa-

tion in each. So for example if we use only one input capacitor

of 24 mΩ.

PCAP = 88.8 mW

Output Inductor Loss (PIND)

PIND = I2OUT x DCR

where DCR is the DC resistance. Therefore, for example

PIND = (4A)2 x 11 mΩ

PIND = 176 mW

Total System Efficiency

PTOTAL = PFET + PIC + PGATE + PCAP + PIND

19 www.ti.com

LM2745/8

Example Circuits

20137432

FIGURE 17. 3.3V to 1.8V @ 2A, fSW = 300 kHz

PART PART NUMBER TYPE PACKAGE DESCRIPTION VENDOR

U1 LM2745 Synchronous

Controller

TSSOP-14 NSC

Q1 FDS6898A Dual N-MOSFET SO-8 20V, 10 mΩ @ 4.5V,

16nC

Fairchild

D1 MBR0520LTI Schottky Diode SOD-123

L1 DO3316P-472 Inductor 4.7 µH, 4.8Arms 18

mΩ

Coilcraft

CIN1 16SP100M Aluminum

Electrolytic

10mm x 6mm 100 µF, 16V,

2.89Arms

Sanyo

CO1 6SP220M Aluminum

Electrolytic

10mm x 6mm 220 µF, 6.3V 3.1Arms Sanyo

CCC, CBOOT,

CIN2, CO2

VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay

CC3 VJ0805Y332KXXA Capacitor 805 3300 pF, 10% Vishay

CSS VJ0805A123KXAA Capacitor 805 12 nF, 10% Vishay

CC2 VJ0805A821KXAA Capacitor 805 820 pF 10% Vishay

CC1 VJ0805A220KXAA Capacitor 805 22 pF, 10% Vishay

RFB2 CRCW08051002F Resistor 805 10.0 kΩ 1% Vishay

RFB1 CRCW08054991F Resistor 805 4.99 kΩ1% Vishay

RFADJ CRCW08051003F Resistor 805 100 kΩ 1% Vishay

RC2 CRCW08052101F Resistor 805 2.1 kΩ 1% Vishay

RCS CRCW08052101F Resistor 805 2.1 kΩ 1% Vishay

RCC CRCW080510R0F Resistor 805 10.0Ω 1% Vishay

RC1 CRCW08055492F Resistor 805 54.9 kΩ 1% Vishay

RPULL-UP CRCW08051003J Resistor 805 100 kΩ 5% Vishay

CCLK VJ0805A560KXAA Capacitor 805 56 pF, 10% Vishay

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LM2745/8

20137433

FIGURE 18. 5V to 2.5V @ 2A, fSW = 300 kHz

PART PART NUMBER TYPE PACKAGE DESCRIPTION VENDOR

U1 LM2745 Synchronous

Controller

TSSOP-14 NSC

Q1 FDS6898A Dual N-MOSFET SO-8 20V, 10 mΩ @ 4.5V, 16

Fairchild

D1 MBR0520LTI Schottky Diode SOD-123

L1 DO3316P-682 Inductor 6.8 µH, 4.4Arms, 27 mΩCoilcraft

CIN1 16SP100M Aluminum

Electrolytic

10mm x 6mm 100 µF, 16V, 2.89Arms Sanyo

CO1 10SP56M Aluminum

Electrolytic

6.3mm x 6mm 56 µF, 10V 1.7Arms Sanyo

CCC, CBOOT,

CIN2, CO2

VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay

CC3 VJ0805Y182KXXA Capacitor 805 1800 pF, 10% Vishay

CSS VJ0805A123KXAA Capacitor 805 12 nF, 10% Vishay

CC2 VJ0805A821KXAA Capacitor 805 820 pF 10% Vishay

CC1 VJ0805A330KXAA Capacitor 805 33 pF, 10% Vishay

RFB2 CRCW08051002F Resistor 805 10.0 kΩ 1% Vishay

RFB1 CRCW08053161F Resistor 805 3.16 kΩ 1% Vishay

RFADJ CRCW08051003F Resistor 805 100 kΩ 1% Vishay

RC2 CRCW08051301F Resistor 805 1.3 kΩ 1% Vishay

RCS CRCW08052101F Resistor 805 2.1 kΩ 1% Vishay

RCC CRCW080510R0F Resistor 805 10.0Ω 1% Vishay

RC1 CRCW08053322F Resistor 805 33.2 kΩ 1% Vishay

RPULL-UP CRCW08051003J Resistor 805 100 kΩ 5% Vishay

CCLK VJ0805A560KXAA Capacitor 805 56 pF, 10% Vishay

21 www.ti.com

LM2745/8

20137434

FIGURE 19. 12V to 3.3V @ 4A, fSW = 300kHz

PART PART NUMBER TYPE PACKAGE DESCRIPTION VENDOR

U1 LM2745 Synchronous

Controller

TSSOP-14 NSC

Q1 FDS6898A Dual N-MOSFET SO-8 20V, 10 mΩ @ 4.5V, 16

Fairchild

D1 MBR0520LTI Schottky Diode SOD-123

L1 DO3316P-332 Inductor 3.3 µH, 5.4Arms 15 mΩCoilcraft

CIN1 16SP100M Aluminum

Electrolytic

10mm x 6mm 100 µF, 16V, 2.89Arms Sanyo

CO1 6SP220M Aluminum

Electrolytic

10mm x 6mm 220 µF, 6.3V 3.1Arms Sanyo

CCC, CBOOT,

CIN2, CO2

VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay

CC3 VJ0805Y222KXXA Capacitor 805 2200 pF, 10% Vishay

CSS VJ0805A123KXAA Capacitor 805 12 nF, 10% Vishay

CC2 VJ0805Y332KXXA Capacitor 805 3300 pF 10% Vishay

CC1 VJ0805A820KXAA Capacitor 805 82 pF, 10% Vishay

RFB2 CRCW08051002F Resistor 805 10.0 kΩ 1% Vishay

RFB1 CRCW08052211F Resistor 805 2.21 kΩ 1% Vishay

RFADJ CRCW08051003F Resistor 805 100 kΩ 1% Vishay

RC2 CRCW08052611F Resistor 805 2.61 kΩ 1% Vishay

RCS CRCW08054121F Resistor 805 4.12 kΩ 1% Vishay

RCC CRCW080510R0F Resistor 805 10.0Ω 1% Vishay

RC1 CRCW08051272F Resistor 805 12.7kΩ 1% Vishay

RPULL-UP CRCW08051003J Resistor 805 100 kΩ 5% Vishay

CCLK VJ0805A560KXAA Capacitor 805 56 pF, 10% Vishay

www.ti.com 22

LM2745/8

Physical Dimensions inches (millimeters) unless otherwise noted

TSSOP-14 Pin Package

NS Package Number MTC14

23 www.ti.com

LM2745/8

Notes

LM2745/8 Synchronous Buck Controller with Pre-Bias Startup, and Optional Clock

Synchronization

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