100 MHz to 30 GHz,
Silicon, SP4T Switch
Data Sheet ADRF5044
Rev. A Document Feedback
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Tel: 781.329.4700 ©2017–2020 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Ultrawideband frequency range: 100 MHz to 30 GHz
Nonreflective 50 Ω design
Low insertion loss: 2.6 dB at 20 GHz to 30 GHz
High isolation: 43 dB at 20 GHz to 30 GHz
High input linearity
P1dB: 28 dBm typical
IP3: 50 dBm typical
High power handling
24 dBm through path
24 dBm terminated path
No low frequency spurious
0.1 dB settling time (50% VCTL to 0.1 dB of final RF output): 37 ns
24-terminal LGA package
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Broadband telecommunications systems
FUNCTIONAL BLOCK DIAGRAM
RF2
GND
GND
RF1
GND
GND
RF4
GND
GND
GND
RF3
GND
GND
GND
RFC
GND
GND
GND
V2
V1
VDD
GND
50Ω
VSS
GND
1
2
3
4
5
6
7 8 9 101112
13
14
15
16
17
18
19
2021222324
DRIVER
50Ω
50Ω50Ω
ADRF5044
16313-001
Figure 1.
GENERAL DESCRIPTION
The ADRF5044 is a general-purpose, single-pole, four-throw
(SP4T) switch manufactured using a silicon process. It comes
in a 24-terminal land grid array (LGA) package and provides
high isolation and low insertion loss from 100 MHz to 30 GHz.
This broadband switch requires dual-supply voltages, +3.3 V and
−3.3 V, and provides complementary metal-oxide semiconductor
(CMOS)/low voltage transistor-transistor logic (LVTTL) logic-
compatible control.
ADRF5044 Data Sheet
Rev. A | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance ...................................................................... 5
Power Derating Curves ............................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions ............................ 6
Interface Schematics .................................................................... 6
Typical Performance Characteristics .............................................7
Insertion Loss, Return Loss, and Isolation ................................7
Input 0.1 dB, 1 dB Power Compression, and Third-Order
Intercept .........................................................................................9
Theory of Operation ...................................................................... 10
Applications Information ............................................................. 11
Evaluation Board ........................................................................ 11
Probe Matrix Board ................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
3/2020—Rev. 0 to Rev. A
Changes to Digital Control Inputs Parameter, Table 2 .............. 5
Added Endnote 1, Table 2; Renumbered Sequentially ............... 5
Changes to Theory of Operation Section .................................... 10
12/2017—Revision 0: Initial Version
Data Sheet ADRF5044
Rev. A | Page 3 of 14
SPECIFICATIONS
VDD = 3.3 V, VSS = −3.3 V, V1 = 0 V or 3.3 V, V2 = 0 V or 3.3 V, and TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 100 30,000 MHz
INSERTION LOSS
Between RFC and RF1 to RF4 (On) (Worst Case) 100 MHz to 10 GHz 1.7 dB
10 GHz to 20 GHz 2.1 dB
20 GHz to 30 GHz 2.6 dB
ISOLATION
Between RFC and RF1 to RF4 (Off) (Worst Case) 100 MHz to 10 GHz 55 dB
10 GHz to 20 GHz 52 dB
20 GHz to 30 GHz 43 dB
RETURN LOSS
RFC and RF1 to RF4 (On) 100 MHz to 10 GHz 16 dB
10 GHz to 20 GHz 22 dB
20 GHz to 30 GHz 22 dB
RF1 to RF4 (Off) 100 MHz to 10 GHz 24 dB
10 GHz to 20 GHz 24 dB
20 GHz to 30 GHz 16 dB
SWITCHING TIME
Rise and Fall tRISE, tFALL 10% to 90% of radio frequency (RF) output 4 ns
On and Off tON, tOFF 50% VCTL to 90% of RF output 19 ns
Settling
0.1 dB 50% VCTL to 0.1 dB of final RF output 37 ns
0.05 dB 50% VCTL to 0.05 dB of final RF output 50 ns
INPUT LINEARITY
Power Compression
0.1 dB P0.1dB 26 dBm
1 dB P1dB 28 dBm
Third-Order Intercept IP3 Two-tone input power = 14 dBm each tone,
Δf = 1 MHz
50 dBm
SUPPLY CURRENT VDD, VSS pins
Positive IDD Typical at VCTL = 0 V or 3.3 V, maximum at
VCTL = 0.8 V or 1.4 V
12 20 μA
Negative ISS Typical at VCTL = 0 V or 3.3 V, maximum at
VCTL = 0.8 V or 1.4 V
110 130 μA
DIGITAL CONTROL INPUTS V1, V2 pins
Voltage
Low VINL 0 0.8 V
High VINH 1.2 3.3 V
Current
Low and High IINL, IINH <1 μA
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive VDD 3.15 3.45 V
Negative VSS −3.45 −3.15 V
Digital Control Voltage VCTL 0 VDD V
ADRF5044 Data Sheet
Rev. A | Page 4 of 14
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
RFx Input Power PIN T
CASE = 85°C
Through Path RF signal is applied to RFC or through
connected RF1/RF2
24 dBm
Terminated Path RF signal is applied to terminated
RF1/RF2
24 dBm
Hot Switching RF signal is present at RFC while
switching between RF1 and RF2
21 dBm
Case Temperature TCASE −40 +85 °C
Data Sheet ADRF5044
Rev. A | Page 5 of 14
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Supply Voltage
Positive −0.3 V to +3.6 V
Negative −3.6 V to +0.3 V
Digital Control Inputs1 −0.3 V to VDD + 0.3 V
or 3.3 mA, whichever
occurs first
RFx Input Power2 (f = 400 MHz to 30 GHz,
TCASE = 85°C)
Through Path 25 dBm
Terminated Path 25 dBm
Hot Switching 22 dBm
Temperature
Junction, TJ 135°C
Storage Range −65°C to +150°C
Reflow (Moisture Sensitivity Level 3
(MSL3) Rating)
260°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
RFC and RF1 to RF4 Pins 375 V
Other Pins 2000 V
1 Overvoltages at digital control inputs are clamped by internal diodes.
Current must be limited to the maximum rating given.
2 For power derating less than 400 MHz, see Figure 2 and Figure 3.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type θJC Unit
CC-24-4
Through Path 400 °C/W
Terminated Path 160 °C/W
POWER DERATING CURVES
4
–14
–12
–10
–8
–6
–4
–2
0
2
10k 100k 1M 10M 100M 1G 10G 100G
POWER DERATING (dB)
FREQUENCY (Hz)
16313-002
Figure 2. Power Derating for Through Path and Hot Switching vs. Frequency,
TCASE = 85°C
4
–14
–12
–10
–8
–6
–4
–2
0
2
10k 100k 1M 10M 100M 1G 10G 100G
POWER DERATING (dB)
FREQUENCY (Hz)
16313-003
Figure 3. Power Derating for Terminated Path vs. Frequency, TCASE = 85°C
ESD CAUTION
ADRF5044 Data Sheet
Rev. A | Page 6 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RF2
GND
GND
RF1
GND
GND
RF4
GND
GND
GND
RF3
GND
G
ND
G
ND
RFC
G
ND
G
ND
G
ND
V2
V1
VDD
GND
VSS
GND
1
2
3
4
5
6
7 8 9 101112
13
14
15
16
17
18
192021222324
ADRF5044
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF/DC GROUND
OF THE PCB.
16313-004
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 4 to 7, 9, 10, 12,
13, 18, 19, 21, 22, 24
GND Ground. These pins must be connected to the RF/dc ground of the PCB.
3 RFC
RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
8 RF4
RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
11 RF3
RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
14 VSS Negative Supply Voltage.
15 V2 Control Input 2. See Table 5 for the control voltage truth table.
16 V1 Control Input 1. See Table 5 for the control voltage truth table.
17 VDD Positive Supply Voltage.
20 RF2
RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
23 RF1
RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2,
RF3,
RF4
16313-005
Figure 5. RFx Pins (RFC and RF1 to RF4) Interface Schematic
V1, V2
16313-006
Figure 6. Digital Pins (V1 and V2) Interface Schematic
Data Sheet ADRF5044
Rev. A | Page 7 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
Insertion loss and return loss measured on the probe matrix board using ground signal ground (GSG) probes close to the RFx pins;
isolation measured on the evaluation board because signal coupling between the probes limits the isolation performance of the ADRF5044
on the probe matrix board.
0
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0 5 10 15 20 25 30 35 40
INSERTION LOSS (dB)
FREQUENCY (GHz)
RF1
RF2
RF3
RF4
16313-007
Figure 7. Insertion Loss vs. Frequency for RF1, RF2, RF3, and RF4
0
–40
–35
–30
–25
–20
–15
–10
–5
0 5 10 15 20 25 30 35 40
RETURN LOSS (dB)
FREQUENCY (GHz)
16313-008
Figure 8. Return Loss vs. Frequency for RFC
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RF2
RFC TO RF3
RFC TO RF4
16313-009
Figure 9. Isolation vs. Frequency, RFC to RF1 On
0
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0 5 10 15 20 25 30 35 40
INSERTION LOSS (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
16313-010
Figure 10. Insertion Loss vs. Frequency over Various Temperatures
Between RFC and RF1
0
–40
–35
–30
–25
–20
–15
–10
–5
0 5 10 15 20 25 30 35 40
RETURN LOSS (dB)
FREQUENCY (GHz)
ON
OFF
16313-011
Figure 11. Return Loss vs. Frequency for RF1, RF2, RF3, and RF4
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RF1
RFC TO RF3
RFC TO RF4
16313-012
Figure 12. Isolation vs. Frequency, RFC to RF2 On
ADRF5044 Data Sheet
Rev. A | Page 8 of 14
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF4
16313-013
Figure 13. Isolation vs. Frequency, RFC to RF3 On
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40
CHANNEL TO CHANNEL ISOLATION (dB)
FREQUENCY (GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF2 TO RF4
16313-014
Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF1 On
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF3
16313-015
Figure 15. Isolation vs. Frequency, RFC to RF4 On
Data Sheet ADRF5044
Rev. A | Page 9 of 14
INPUT 0.1 dB, 1 dB POWER COMPRESSION, AND THIRD-ORDER INTERCEPT
All large signal performance parameters were measured on the evaluation board.
32
10
12
14
16
18
20
22
24
26
28
30
0 5 10 15 20
INPUT P0.1dB (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
16313-016
Figure 16. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Various Temperatures
32
10
12
14
16
18
20
22
24
26
28
30
0 5 10 15 20
INPUT P1dB (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
16313-017
Figure 17. Input 1 dB Power Compression (P1dB) vs. Frequency over
Various Temperatures
60
20
25
30
35
40
45
50
55
0 5 10 15 3020 25
INPUT IP3 (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
16313-018
Figure 18. Input IP3 vs. Frequency over Various Temperatures
32
10
12
14
16
18
20
22
24
26
28
30
10k 100k 1M 10M 100M 1G
INPUT P0.1dB (dBm)
FREQUENCY (Hz)
+85°C
+25°C
–40°C
16313-019
Figure 19. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Various Temperatures (Low Frequency Detail)
32
10
12
14
16
18
20
22
24
26
28
30
10k 100k 1M 10M 100M 1G
INPUT P1dB (dBm)
FREQUENCY (Hz)
+85°C
+25°C
–40°C
16313-020
Figure 20. Input 1 dB Power Compression (P1dB) vs. Frequency over Various
Temperatures (Low Frequency Detail)
60
20
25
30
35
40
45
50
55
10k 100k 1M 10M 100M 1G
INPUT IP3 (dBm)
FREQUENCY (Hz)
+85°C
+25°C
–40°C
16313-021
Figure 21. Input IP3 vs. Frequency over Various Temperatures
(Low Frequency Detail)
ADRF5044 Data Sheet
Rev. A | Page 10 of 14
THEORY OF OPERATION
The ADRF5044 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
The ADRF5044 incorporates a driver to perform logic
functions internally and to provide the user with the advantage
of a simplified control interface. The driver features two digital
control input pins (V1 and V2) that control the state of the RF
paths. Depending on the logic level applied to the V1 and V2
pins, one RF path is in an insertion loss state, while the other
three paths are in an isolation state (see Table 5). The insertion
loss path conducts the RF signal equally well in both directions
between the RF throw port and the RF common port, and the
isolation paths provides high loss between the RF throw ports
terminated to internal 50 Ω resistors and the insertion loss
path.
The ideal power-up sequence for the ADRF5044 is as follows:
1. Connect GND.
2. Power up VDD and VSS. Powering up VSS after VDD
avoids current transients on VDD during ramp-up.
3. Apply digital control inputs, V1 and V2. Applying the digital
control inputs before the VDD supply may inadvertently
forward bias and damage the internal ESD protection
structures. In this case, use a series 1 k resistor to limit
the current flowing in to the control pin. If the control pins
are not driven to a valid logic state (for example, if the
controller output is in a high impedance state) after VDD
is powered up, it is recommended to use pull-up and pull-
down resistors.
4. Apply an RF input signal. The design is bidirectional. The
RF input signal can be applied to the RFC port, while the
RF throw ports are outputs, or vice versa. The RF ports are
dc-coupled to 0 V, and no dc blocking is required at the RF
ports when the RF line potential is equal to 0 V.
The ideal power-down sequence is the reverse order of the
power-up sequence.
Table 5. Control Voltage Truth Table
Digital Control Input RF Paths
V1 V2 RF1 to RFC RF2 to RFC RF3 to RFC RF4 to RFC
Low Low Insertion loss (on) Isolation (off) Isolation (off) Isolation (off)
High Low Isolation (off) Insertion loss (on) Isolation (off) Isolation (off)
Low High Isolation (off) Isolation (off) Insertion loss (on) Isolation (off)
High High Isolation (off) Isolation (off) Isolation (off) Insertion loss (on)
Data Sheet ADRF5044
Rev. A | Page 11 of 14
APPLICATIONS INFORMATION
EVALUATION BOARD
Figure 22 shows the top view of the ADRF5044-EVALZ, and
Figure 23 shows the cross sectional view of the ADRF5044-
EVALZ.
16313-022
Figure 22. Evaluation Board Layout, Top View
RO4003
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
W = 14mil G = 5mil
T = 0.7mil
H = 8mil
TOTAL THICKNESS ≈ 62 mil
16313-023
Figure 23. Evaluation Board (Cross Sectional View)
The ADRF5044-EVALZ is a 4-layer evaluation board. Each
copper layer is 0.7 mil (0.5 oz) and separated by dielectric
materials. All RF and dc traces are routed on the top copper
layer, and the inner and bottom layers are grounded planes that
provide a solid ground for the RF transmission lines. The top
dielectric material is 8 mil Rogers RO4003, offering optimal high
frequency performance. The middle and bottom dielectric
materials provide mechanical strength. The overall board
thickness is 62 mil, which allows 2.4 mm RF launchers to be
connected at the board edges.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with a trace width of 14 mil and a
ground clearance of 5 mil, to have a characteristic impedance
of 50 Ω. For optimal RF and thermal grounding, as many
plated through vias as possible are arranged around the
transmission lines and under the exposed pad of the package.
Figure 24 shows the actual ADRF5044 evaluation board with
component placement. Two power supply ports are connected
to the VDD and VSS test points (TP1 and TP4), control
voltages are connected to the V1 and V2 test points (TP2 and
TP3), and the ground reference is connected to the GND test
point (TP5).
16313-024
Figure 24. Evaluation Board Component Placement
On the control traces, V1 and V2, a 0 Ω resistor connects the
test points to the pins on the ADRF5044. On the supply traces,
VDD and VSS, a 100 pF bypass capacitor filters the high
frequency noise. Additionally, unpopulated components
positions are available for applying extra bypass capacitors.
The RF input and output ports (RFC, RF1, RF2, RF3, and RF4)
are connected through 50 transmission lines to the 2.4 mm
RF launchers (J1 to J5). These high frequency RF launchers are
by contact and not soldered onto the board. A thru calibration
line connects the unpopulated J6 and J7 launchers; this
transmission line is used to estimate the loss of the PCB over
the environmental conditions being evaluated.
The schematic of the ADRF5044-EVALZ is shown in Figure 25.
ADRF5044 Data Sheet
Rev. A | Page 12 of 14
RF2
GND
GND
RF1
GND
PAD
GND
RF4
GND
GND
GND
RF3
GND
GND
GND
1
1
RF2
RF1
J
1
J
2
RFC
GND
GND
AGND
AGND
R1
R2
0Ω
0Ω
VDD
VSS
V1
V2
AGND
TP1
TP5
TP2
TP3
TP4
GND
V2
V1
VDD
GND
VSS
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
C1
100pF
C7
0.1µF
DNI
AGND
C8
0.1µF
DNI
AGND
C5
10µF
DNI
AGND
C4
0.1µF
DNI
AGND
U1
ADRF5044
19
20
21
22
23
24
PAD
AGND AGND AGND
C2
100pF
C3
0.1µF
DNI
C6
10µF
DNI
11111
AGND
2345
AGND
2345
1RFC
J3
AGND
2345
1RF4
J4
AGND
2345
1RF3
J5
AGND
2345
1THRU_CAL
DNI DNI
J6
AGND
2345
1
J7
AGND
2543
16313-025
Figure 25. ADRF5044-EVALZ Schematic
Table 6. Evaluation Board Components
Component Default Value Description
C1, C2 100 pF Capacitors, C0402 package
C5, C6 10 μF Capacitors C3216 package, do not install (DNI)
C3, C4, C7, C8 0.1 μF Capacitors, C0402 package, DNI
J1 to J7 Not applicable 2.4 mm end launch connector (Southwest Microwave: 1492-04A-5)
R1, R2 0 Ω Resistors, 0402 package
TP1 to TP5 Not applicable Through-hole mount test point
U1 ADRF5044 ADRF5044 digital attenuator, Analog Devices, Inc.
PCB 08-042615-01 Evaluation PCB, Analog Devices
Data Sheet ADRF5044
Rev. A | Page 13 of 14
PROBE MATRIX BOARD
The probe matrix board is a 4-layer board that uses a 12 mil
Rogers RO4003 as the top dielectric material. The external
copper layer is 0.7 mil, and the internal copper layers are
1.4 mil. The RF transmission lines were designed using a
CPWG model, with a 16 mil width and a ground spacing of
6 mil, to have a characteristic impedance of 50 Ω.
Figure 26 shows the cross sectional view of the probe matrix
board, and Figure 27 shows the top view of the probe matrix
board. Measurements were made using 535 µm GSG probes at
close proximity to the RFx pins. Unlike the ADRF5044-EVALZ,
probing reduces reflections caused by mismatch arising from
connectors, cables, and board layout, resulting in a more
accurate measurement of the performance of the ADRF5044.
RO4003
1oz Cu (1.4mil)
1oz Cu (1.4mil)
0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
FR4
FR4
W = 16mil G = 6mil
T = 0.7mil
H = 12mil
TOTAL THICKNESS ≈ 62mil
16313-026
Figure 26. Probe Matrix Board (Cross Sectional View)
16313-027
Figure 27. Probe Board Layout (Top View)
RF traces for a through reflect line (TRL) calibration are
designed on the board itself. A nonzero line length
compensates for board loss at calibration. The actual board
duplicates the same layout in matrix form to assemble multiple
devices at once. Insertion loss and input and output return
losses were measured on this probe matrix board. Isolation
performance measured on the probe matrix board is limited
due to signal coupling between the RF probes that are in close
proximity. Therefore, RF port to port isolation was measured
on the ADRF5044-EVALZ.
ADRF5044 Data Sheet
Rev. A | Page 14 of 14
OUTLINE DIMENSIONS
08-11-2016-A
PKG-005263
4.10
4.00
3.90
PIN A1
CORNER AREA
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1
6
7
12
13
18
19
24
0.50
BSC
0.125
BSC
2.50 REF
SQ
0.35
0.30
0.25
0.30
0.25
0.20
0.37
0.33
0.28
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.96
MAX
0.53 REF
0.30 × 0.45°
PIN 1
INDIC
A
TOR
2.40 BSC
SQ
Figure 28. 24-Terminal Land Grid Array [LGA]
(CC-24-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADRF5044BCCZN −40°C to +85°C 24-Terminal Land Grid Array [LGA] CC-24-4
ADRF5044BCCZN-R7 −40°C to +85°C 24-Terminal Land Grid Array [LGA] CC-24-4
ADRF5044-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
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D16313-3/20(A)
