High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 Add 48CSP-6x8mm package outline Mar. 08, 2005 2.2 Revise 48CSP-8x10mm pkg code from W to K Oct. 25, 2005 2.3 Revised DC characteristics Nov. 23, 2006 2.4 Revised DC characteristics Jun. 20,2007 2.5 Change wafer process from 0.18um to 0.15um May. 19, 2008 2.6 Add CE2 description of 48BGA package Nov. 20, 2009 2.7 Modify Data Retention waveform May. 27.2010 1 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV81923 512k Word By 16 bit PRODUCT DESCRIPTION The CS16LV81923 is a high performance, high speed, low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced 0.15um CMOS technology and circuit techniques provide both high speed and low power features with a Typical CMOS standby current of 0.3uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable1 (/CE), active HIGH chip enable2 (CE2) for BGA product and active LOW output enable (/OE) and three-state output drivers. The CS16LV81923 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS16LV81923 is available in JEDEC standard 44L TSOP 2 and 48Ball Mini_BGA 8x10mm packages. FEATURES Low operation voltage: 2.7 ~ 3.6V Ultra low power consumption: Vcc = 3.0V: 25mA (Typ.) operating current, 0.3uA (Typ.) CMOS standby current High speed access time: 55/70ns (Max.) at Vcc = 3.0V. Automatic power down when chip is deselected. Three state outputs and TTL compatible. Data retention supply voltage as low as 1.5V. Easy expansion with /CE&CE2 and /OE options. PRODUCT FAMILY Product Family Operating Temp Vcc. Range Speed (ns) 2.7 ~ 3.6 -40 ~ 85oC Package Type 0.3 uA (VCC = 3.0V) 0 ~ 70oC CS16LV81923 Standby Current (Typ.) 44 TSOP 2-400mil 48 Mini_BGA 8x10mm 55/70 0.3 uA (VCC= 3.0V) 2 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM For single CE product of 44 TSOP 2-400mil 3 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV81923 512k Word By 16 bit For dual CE product of 48 Mini_BGA 8x10mm PIN DESCRIPTIONS Name Type A0 ~ A18 Input Function 19 address inputs for selecting one of the 524,288 x 16 bit words in the RAM /CE1 is active LOW and CE2 is active high. Chip enable must be active when /CE /CE1 & CE2 Input data read from or write to the device. If chip enable is not active, the device is deselected and in a standby power mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write operations. /WE Input With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the /OE Input chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. Lower byte and upper byte data input/output control pins. /LB and /UB Input DQ0~DQ15 I/O Vcc Power Power Supply Vss Power Ground These 16 bi-directional ports are used to read data from or write data into the RAM. 4 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV81923 512k Word By 16 bit TRUTH TABLE MODE (1) /CE (2) /CE1 (2) CE2 /WE /OE /LB /UB DQ0~7 DQ8~15 Vcc Current Fully H H X X X X X High Z High Z ICCSB, ICCSB1 Standby X X L X X X X High Z High Z ICCSB, ICCSB1 L L H H H X X High Z High Z ICC L L DOUT DOUT ICC H L High Z DOUT ICC L H DOUT High Z ICC L L DIN DIN ICC H L High Z DIN ICC L H DIN High-Z ICC Output Disabled Read Write L L L L H H H L L X Note: (1) /CE is used for 44 TSOP 2-400mil of single CE product only. (2) /CE1 and CE2 are used for 48 Mini_BGA 8x10mm dual CE product only. ABSOLUTE MAXIMUM RATINGS Symbol (1) Parameter Rating Unit -0.2 to Vcc+0.5 V VTERM Terminal Voltage with Respect to GND TBIAS Temperature Under Bias -40 to +125 O C TSTG Storage Temperature -60 to +150 O C PT Power Dissipation 1.0 W IOUT DC Output Current 35 mA 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 5 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV81923 512k Word By 16 bit o DC ELECTRICAL CHARACTERISTICS (TA = 0~+70 C / -400C~+850C ,VCC = 3.0V) Parameter Parameter Name Test Conduction Guaranteed Input Low VIL Voltage MIN -0.2 (2) Guaranteed Input High VIH Voltage Input Leakage Current IOL Output Leakage Current VOL Output Low Voltage VCC=MAX, IOL = 2 mA VOH Output High Voltage VCC=MIN, IOH = -1mA Operating Power Supply /CE=VIL, IDQ=0mA, Current F=FMAX Standby Supply -TTL /CE=VIH, IDQ=0mA, ICCSB (2) VCC=MAX, VIN=0 to VCC VCC=MAX, /CE=VIH, or /OE=VIH , VIO=0V to VCC MAX Unit 0.6 V (2) 2.2 (2) IIL ICC (1) TYP Vcc+0.2 V -1 1 uA -1 1 uA 0.4 V 2.4 V 25 (3) 35 mA 0.5 mA 6 uA /CEVCC-0.2V, ICCSB1 Standby Current-CMOS 0.3 VIN VCC-0.2V or VIN0.2V o 1. Typical characteristics are at TA = 25 C. 2. Overshoot: Vcc+2.0V in case of pulse width20ns. Undershoot: -2.0V in case of pulse width20ns. Overshoot and undershoot are sampled, not 100% tested. 3. Fmax = 1/tRC. OPERATING RANGE Range Ambient Temperature Commercial 0~70 C VCC o 2.7V ~ 3.6V o Industrial -40~85 C 2.7V ~ 3.6V CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit CIN Input Capacitance VIN=0V 8 pF CDQ Input/Output Capacitance VI/O=0V 10 pF 1. This parameter is guaranteed and not 100% tested. 6 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV81923 512k Word By 16 bit o DATA RETENTION CHARACTERISTICS ( TA = 0~+70 C / -400C~+850C ) Parameter Parameter Test Conduction MIN (1) TYP MAX Unit Name /CEVCC-0.2V, VINVCC-0.2V VDR VCC for Data Retention 1.5 V or VIN0.2V /CEVCC-0.2V, VCC=1.5V ICCDR Data Retention Current 0.1 3 uA VIN VCC-0.2V or VIN0.2V Chip Deselect to Data tSDR 0 ns Retention Time See Retention Waveform Operation Recovery tRDR tRC (2) ns Time o 1. VCC= 3.0V, TA = +25 C 2. tRC (2) = Read Cycle Time. LOW VCC DATA RETENTION WAVEFORM (1) ( /CE1 or /CE Controlled ) 7 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV81923 512k Word By 16 bit LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled-BGA only ) KEY TO SWITCHING WAVEFORMS WAVEFORMS INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE AC TEST LOADS 8 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV81923 512k Word By 16 bit o AC ELECTRICAL CHARACTERISTICS( TA = 0~+70 C / -400C~+850C , Vcc = 3.0V ) < READ CYCLE > JEDEC Parameter 55 70 Description Name Name Unit MIN MAX MIN MAX tAVAX tRC Read Cycle Time 55 70 tAVQV tAA Address Access Time 55 70 ns tELQV tCO Chip Select Access Time (/CE) 55 70 ns tBA tBA Data Byte Control Access Time (/LB, /UB) 55 70 ns tGLQV tOE Output Enable to Output Valid 30 35 ns tELQX tLZ Chip Select to Output Low Z (/CE) 5 5 ns tBE tBLZ Data Byte Control to Output Low Z (/LB, /UB) 10 10 ns tGLQX tOLZ Output Enable to Output in Low Z 5 5 ns tEHQZ tHZ Chip Deselect to Output in High Z (/CE) 0 20 0 20 ns tBDO tBHZ Data Byte Control to Output High Z (/LB, /UB) 0 20 0 20 ns tGHQZ tOHZ Output Disable to Output in High Z 0 20 0 20 ns tAXOX tOH Out Disable to Address Change 10 10 ns ns SWITCHING WAVEFORMS (READ CYCLE) For single CE product of 44 TSOP 2- 400mil 9 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 NOTES: 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. For dual CE product of 48 Mini_BGA 8x10mm 10 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 NOTES: 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 11 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV81923 512k Word By 16 bit o AC ELECTRICAL CHARACTERISTICS ( TA = 0~+70 C / -400C~+850C , Vcc = 3.0V ) < WRITE CYCLE > JEDEC Parameter Name Name Description 55 70 Unit MIN MAX MIN MAX tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 45 60 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 45 60 ns tWLWH tWP Write Pulse Width 45 55 ns tWHAX tWR Write Recovery Time (/CE, /WE) 0 0 ns tBW tBW Data Byte Control to End of Write(/LB, /UB) 55 70 ns tWLQZ tWHZ Write to Output in High Z 0 tDVWH tDW Data to Write Time Overlap 30 30 ns tWHDX tDH Data Hold from Write Time 0 0 ns tWHOX tOW End of Write to Output Active 5 5 ns 20 0 20 ns 12 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 SWITCHING WAVEFORMS (WRITE CYCLE) For single CE product of 44 TSOP 2- 400mil 13 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 NOTES: 1. A write occurs during the overlap(tWP) of low /CE and low /WE. A write begins when /CE goes low and /WE goes low with asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CE goes high and /WE goes high. The tWP is measured from the beginning of the write to the end of write. 2. tCW is measured from the /CE going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. TWR applied in case a write ends as /CE or /WE going high. 14 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 For dual CE product of 48 Mini_BGA 8x10mm 15 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 NOTES: 1. A write occurs during the overlap(tWP) of low /CE1, high CE2and low /WE. A write begins when /CE1 goes low, CE2 goes high and /WE goes low with asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CE1 goes high, CE2 goes low and /WE goes high. The tWP is measured from the beginning of the write to the end of write. 2. tCW is measured from the /CE1 going low or CE2 going high to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. TWR applied in case a write ends as /CE1 going high, CE2 going low or /WE going high. 16 Rev. 2.7 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512k Word By 16 bit CS16LV81923 ORDER INFORMATION Note: Package material code "P" & "R" comply with RoHS. 17 Rev. 2.7 Chiplus reserves the right to change product or specification without notice.