TMS320C25FNLR50 - Texas Instruments

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 1

ADVANCE INFORMATION concerns new products in the

sampling or preproduction phase of development.

Characteristic data and other specifications are subject to

change without notice.

80-ns Instruction Cycle Time

544 Words of On-Chip Data RAM

4K Words of On-Chip Secure Program

EPROM (TMS320E25)

4K Words of On-Chip Program ROM

(TMS320C25)

128K Words of Data/Program Space

32-Bit ALU/Accumulator

16 16-Bit Multiplier With a 32-Bit Product

Block Moves for Data/Program

Management

Repeat Instructions for Efficient Use of

Program Space

Serial Port for Direct Codec Interface

Synchronization Input for Synchronous

Multiprocessor Configurations

Wait States for Communication to Slow

Off-Chip Memories/Peripherals

On-Chip Timer for Control Operations

Single 5-V Supply

Packaging: 68-Pin PGA, PLCC, and

CER-QUAD

68-to-28 Pin Conversion Adapter Socket for

EPROM Programming

Commercial and Military Versions Available

NMOS Technology:

— TMS32020 200-ns cycle time.........

CMOS Technology:

— TMS320C25 100-ns cycle time........

— TMS320E25 100-ns cycle time........

— TMS320C25-50 80-ns cycle time......

description

This data sheet provides complete design documentation for the second-generation devices of the TMS320

family. This facilitates the selection of the devices best suited for user applications by providing all specifications

and special features for each TMS320 member. This data sheet is divided into four major sections: architecture,

electrical specifications (NMOS and CMOS), timing diagrams, and mechanical data. In each of these sections,

generic information is presented first, followed by specific device information. An index is provided for quick

reference to specific information about a device.

1234567891011

68-Pin GB Package†

(Top View)

IACK

MSC

CLKOUT1

CLKOUT2

HOLDA

FSX

X2 CLKIN

D10

D11

D12

D13

D14

D15

READY

CLKR

CLKX

STRB

R/W

VSS

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

9876543216867666564636261

VSS

SYNC

INT0

INT1

INT2

VCC

FSR

A10

A11

A12

A13

A14

A15

VSS

VCC

68-Pin FN and FZ Packages†

(Top View)

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS

FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN

A0 K1/26 A12 K8/40 D2 E1/16 D14 A5/3 INT2 H1/22 VCC H2/23

A1 K2/28 A13 L9/41 D3 D2/15 D15 B6/2 IS J11/46 VCC L6/35

A2 L3/29 A14 K9/42 D4 D1/14 DR J1/24 MP/MC†A6/1 VSS B1/10

A3 K3/30 A15 L10/43 D5 C2/13 DS K10/45 MSC C10/59 VSS K11/44

A4 L4/31 BIO B7/68 D6 C1/12 DX E11/54 PS J10/47 VSS L2/27

A5 K4/32 BR G11/50 D7 B2/11 FSR J2/25 READY B8/66 XF D11/56

A6 L5/33 CLKOUT1 C11/58 D8 A2/9 FSX F10/53 RS A8/65 X1 G10/51

A7 K5/34 CLKOUT2 D10/57 D9 B3/8 HOLD A7/67 R/W H11/48 X2/CLKIN F11/52

A8 K6/36 CLKR B9/64 D10 A3/7 HOLDA E10/55 STRB H10/49

A9 L7/37 CLKX A9/63 D11 B4/6 IACK B11/60 SYNC F2/19

A10 K7/38 D0 F1/18 D12 A4/5 INT0 G1/20 VCC A10/61

A11 L8/39 D1 E2/17 D13 B5/4 INT1 G2/21 VCC B10/62

†On the TMS32020, MP/MC must be connected to VCC.

SIGNALS I/O/Z‡DEFINITION

VCC

VSS

X2/CLKIN

CLKOUT1

CLKOUT2

D15-D0

A15-A0

PS,DS,IS

R/W

STRB

INT2-INT0

MP/MC

MSC

IACK

READY

HOLD

HOLDA

SYNC

BIO

CLKR

FSR

CLKX

FSX

I/O/Z

O/Z

I/O/Z

5-V supply pins

Ground pins

Output from internal oscillator for crystal

Input to internal oscillator from crystal or external clock

Master clock output (crystal or CLKIN frequency/4)

A second clock output signal

16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/O spaces.

16-bit address bus A15 (MSB) through A0 (LSB)

Program, data, and I/O space select signals

Read/write signal

Strobe signal

Reset input

External user interrupt inputs

Microprocessor/microcomputer mode select pin

Microstate complete signal

Interrupt acknowledge signal

Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction

is complete.

Bus request signal. Asserted when the TMS320C2x requires access to an external global data memory space.

External flag output (latched software-programmable signal)

Hold input. When asserted, TMS320C2x goes into an idle mode and places the data, address, and control lines in

the high impedance state.

Hold acknowledge signal

Synchronization input

Branch control input. Polled by BIOZ instruction.

Serial data receive input

Clock for receive input for serial port

Frame synchronization pulse for receive input

Serial data transmit output

Clock for transmit output for serial port

Frame synchronization pulse for transmit. Configuration as either an input or an output.

‡I/O/Z denotes input/output/high-impedance state.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 3

description

The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed

controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to

multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and

flexibility to produce a MOS microprocessor family that is capable of executing more than 12.5 MIPS (million

instructions per section). The TMS320 family optimizes speed by implementing functions in hardware that other

processors implement through microcode or software. This hardware-intensive approach provides the design

engineer with processing power previously unavailable on a single chip.

The TMS320 family consists of three generations of digital signal processors. The first generation contains the

TMS32010 and its spinoffs. The second generation includes the TMS32020, TMS320C25, and TMS320E25,

which are described in this data sheet. The TMS320C30 is a floating-point DSP device designed for even higher

performance. Many features are common among the TMS320 processors. Specific features are added in each

processor to provide different cost/performance tradeoffs. Software compatibility is maintained throughout the

family to protect the user’s investment in architecture. Each processor has software and hardware tools to

facilitate rapid design.

introduction

The TMS32010, the first NMOS digital signal processor in the TMS320 family, was introduced in 1983. Its

powerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovative

architecture have made this high-performance, cost-effective processor the ideal solution to many

telecommunications, computer, commercial, industrial, and military applications. Since that time, the

TMS320C10, a low-power CMOS version of the industry-standard TMS32010, and other spinoff devices have

been added to the first generation of the TMS320 family.

The second generation of the TMS320 family (referred to as TMS320C2x) includes four members, the

TMS32020, TMS320C25, TMS320C25-50, and TMS320E25. The architecture of these devices is based upon

that of the TMS32010.

The TMS32020, processed in NMOS technology, is source-code compatible with he TMS32010 and in many

applications is capable of two times the throughput of the first-generation devices. Its enhanced instruction set

(109 instructions), large on-chip data memory (544 words), large memory spaces, on-chip serial port, and

hardware timer make the TMS32020 a powerful addition to the TMS320 family.

The TMS320C25 is the second member of the TMS320 second generation. It is processed in CMOS technology,

is capable of an instruction cycle time of 100 ns, and is pin-for-pin and object-code compatible with the

TMS32020. The TMS320C25’s enhanced feature set greatly increases the functionality of the device over the

TMS32020. Enhancements included 24 additional instructions (133 total), eight auxiliary registers, an

eight-level hardware stack, 4K words of on-chip program ROM, a bit-reversed indexed-addressing mode, and

the low-power dissipation inherent to the CMOS process. An extended-temperature range version

(TMS320C25GBA) is also available.

The TMS320C25-50 is a high-speed version of the TMS320C25. It is capable of an instruction cycle time of less

than 80 ns. It is architecturally identical to the original 40-MHz version of the TMS320C25 and, thus, is pin-for-pin

and object-code compatible with the TMS320C25.

The TMS320E25 is identical to the TMS320C25, with the exception that the on-chip 4K-word program ROM is

replaced with a 4K-word on-chip program EPROM. On-chip EPROM allows realtime code development and

modification for immediate evaluation of system performance.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

Key Features: TMS32020

200-ns Instruction Cycle Time

544 Words of On-Chip Data RAM

128K Words of Total Data/Program

Memory Space

Wait States for Communication to Slower Off-Chip

Memories

Source Code Compatible With the TMS320C1x

Single-Cycle Multiply/Accumulate Instructions

Repeat Instructions

Global Data Memory Interface

Block Moves for Data/Program Management

Five Auxiliary Registers With Dedicated

Arithmetic Unit

Serial Port for Multiprocessing or Interfacing

to Codecs, Serial Analog-to-Digital

Converters, etc.

Key Features: TMS320C25, TMS320C25-50, TMS320E25

80-ns Instruction Cycle Time (TMS320C25-50)

100-ns Instruction Cycle Time (TMS320C25)

4K Words of On-Chip Secure Program EPROM

(TMS320E25)

4K Words of On-Chip Program

ROM (TMS320C25)

544 Words of On-Chip RAM

128K Words of Total Program/Data

Memory Space

Wait States for Communications to

Slower Off-Chip Memories

Object-Code Compatible With the TMS32020

Source-Code Compatible With TMS320C1x

24 Additional Instructions to Support

Adaptive Filtering, FFTs, and

Extended-Precision Arithmetic

Block Moves for Data/Program Management

Single-Cycle Multiply/Accumulate Instructions

Eight Auxiliary Registers With Dedicated

Arithmetic Unit

Bit-Reversed Indexed-Addressing Mode for

Radix-2 FFTS

Double-Buffered Serial Port

On-Chip Clock Generator

Single 5-V Supply

NMOS Technology

68-Pin Grid Array (PGA) Package

On-Chip Clock Generator

Single 5-V Supply

Internal Security Mechanism (TMS320E25)

68-to-28 Pin Conversion Adapter Socket

CMOS Technology

68-Pin Grid Array (PGA) Package

(TMS320C25)

68-Lead Plastic Leaded Chip Carrier (PLCC)

Package (TMS320C25, TMS320C25-50)

68-Lead CER-QUAD Package (TMS320E25)

Multiplier

32-BIT ALU/ACC

Shifters

Timer

Interrupts Data (16)

Address (16)

+5 V GND

32-Bit ALU/ACC

Shifters

Timer

MP/MC

Data (16)

Address (16)

+5 V GND

4K-Words

ROM/EPROM

Multiplier

256-Word

Data/Prog

RAM

288-Word

Data

RAM

Interrupts

Serial

Interface

Multi-

Processor

Interface

Serial

Interface

Multi-

Processor

Interface

256-Word

Data/Prog

RAM

288-Word

Data

RAM

DEVICE

RAM ROM/EPROM PROG DATA

TIMER

CYCLE

TIME

(ns)

TYP

POWER

(mW)

PACKAGE

TYPE

I/O†

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 5

Table 1 provides an overview of the second-generation TMS320 processors with comparisons of memory, I/O,

cycle timing, power, package type, technology, and military support. For specific availability, contact the nearest

TI Field Sales Office.

Table 1. TMS320 Second-Generation Device Overview

MEMORY

ON-CHIP OFF-CHIP

SER PAR DMA PGA PLCC CER-QUAD

TMS32020‡(NMOS) 544 —64K 64K YES 16 16 YES YES 200 1250 68 — —

TMS320C25‡(CMOS) 544 4K 64K 64K YES 16 16 CON YES 100 500 68 68 —

TMS320C25-50§(CMOS) 544 4K 64K 64K YES 16 16 CON YES 80 500 —68 —

TMS320E25§(CMOS) 544 4K 64K 64K YES 16 16 CON YES 100 500 — — 68

†SER = serial; PAR = parallel; DMA = direct memory access; CON = concurrent DMA.

‡Military version available; contact nearest TI Field Sales Office for availability.

§Military version planned; contact nearest TI Field Sales Office for details.

architecture

The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard

architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch

and execution. The TMS320 family’s modification of the Harvard architecture allows transfers between program

and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored

in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes

available immediate instructions and subroutines based on computed values.

Increased throughput on the TMS320C2x devices for many DSP applications is accomplished by means of

single-cycle multiply/accumulate instructions with a data move option, up to eight auxiliary registers with a

dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.

The architectural design of the TMS320C2x emphasizes overall speed, communication, and flexibility in

processor configuration. Control signals and instructions provide floating-point support, block-memory

transfers, communication to slower off-chip devices, and multiprocessing implementations.

32-bit ALU/accumulator

The 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and logical

instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch

instructions dependent on the status of the ALU or a single bit ina word. These instructions provide the following

capabilities:

Branch to an address specified by the accumulator

Normalize fixed-point numbers contained in the accumulator

Test a specified bit of a word in data memory

One input to the ALU is always provided from the accumulator, and the other input may be provided from the

Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the

data bus. After the ALU has performed the arithmetic or logical operations,the resultis stored in the accumulator.

The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the

output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The

contents of the accumulator remain unchanged.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

functional block diagram (TMS320C2x)

Data Bus

16 16 16

Shifters (0-7)†

ACCL(16)

ACCH(16)

ALU(32)

Shifter(-6, 0, 1, 4)

Shifter(0-16)

7LSB

From IR

TR(16)

Multiplier

PR(32)

DATA/PROG

RAM (256 16)

Block B0

16 16

Data RAM

Block B1

(256 16)

Block B2

(32 16)

ARB(3)

ARP(3)

ARAU(16)

AR4(16)

AR3(16)

AR2(16)

AR1(16)

AR0(16)

DP(9)

FSX

CLKX

FSR

CLKR

DRR(16)

DXR(16)

PRD(16)

TIM(16)

IMR(6)

GREG(8)

16 16

IFR(6)

RPTC(8)

STO(16)

ST1(16)

IR(16)

D15-D0

A15-A0

INT(2-0)

MP/MC

Instruction

(8 x 16)

16 16 16

Stack

PC(16)

IACK

BIO

MSC

HOLDA

HOLD

STRB

R/W

Program Bus

Program

ROM/

EPROM

(4096 16)

QIR(16)

16 16

X2/CLKIN

CLKOUT1

CLKOUT2

Controller

PFC(16)

MCS(16)

SYNC

MUX

MUXMUX

READY

Address

AR5(16)

AR6(16)

AR7(16)

RSR(16)

XSR(16)

LEGEND:

ACCH = Accumulator high IFR = Interrupt flag register PC = Program counter

ACCL = Accumulator low IMR = Interrupt mask register PFC = Prefetch counter

ALU = Arithmetic logic unit IR = Instruction register RPTC = Repeat instruction counter

ARAU = Auxiliary register arithmetic unitMCS = Microcall stack GREG = Global memory allocation register

ARB = Auxiliary register pointer buffer QIR = Queue instruction register RSR = Serial port receive shift register

ARP = Auxiliary register pointer PR = Product register XSR = Serial port transmit shift register

DP = Data memory page pointer PRD = Period register for timer AR0-AR7 = Auxiliary registers

DRR = Serial port data receive registerTIM = Timer ST0, ST1 = Status registers

DXR = Serial port data transmit register TR = Temporary register C = Carry bit

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 7

scaling shifter

The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to the

ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction.

The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign-extended,

depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1.

16 16-bit parallel multiplier

The 16 16-bit hardware multiplier is capable of computing a signed or unsigned 32-bit product in a single

machine cycle. The multiplier has the following two associated registers.

A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and

A 32-bit Product Register (PR) that holds the product.

Incorporated into the instruction set are single-cycle multiply/accumulate instructions that allow both operands

to be processed simultaneously. The data for these operations may reside anywhere in internal or external

memory, and can be transferred to the multiplier each cycle via the program and data buses.

Four product shift modes are available at the Product Register (PR) output that are useful when performing

multiply/accumulate operations, fractional arithmetic, or justifying fractional products.

timer

The TMS320C2x provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM)

by CLKOUT1/4 on the TMS32020. A timer interrupt (TINT)is generated every time the timer decrements to zero.

The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches

zero so that interrupts may be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT 1 on the

TMS320C25 or 4 PRD CLKOUT 1 cycles on the TMS32020.

memory control

The TMS320C2x provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks

(B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words

(block B0) are programmable as either data or program memory. A data memory size of 544 words allows the

TMS320C2x to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while

still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can

be downloaded from external program memory into on-chip RAM and then executed.

When using on-chip program RAM, ROM, EPROM, or high-speed external program memory, the TMS320C2x

runs at full speed without wait states. However, the READY line can be used to interface the TMS320C2x to

slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program

RAM speeds processing while cutting system costs.

The TMS320C2x provides three separate address spaces for program memory, data memory, and I/O. The

on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon

the memory configuration (see Figure 1). The CNFD (configure block B0 as data memory) and CNFP (configure

block B0 as program memory) instructions allow dynamic configuration of the memory maps through software.

Regardless of the configuration, the user may still execute from external program memory.

The TMS320C2x has six registers that are mapped into the data memory space: a serial port data receive

memory allocation register.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

Pages 8 -511

Interrupts

and Reserved

(External)

External

Interrupts

and Reserved

(On-Chip

ROM/EPROM)

On-Chip

Memory-Mapped

Registers

On-Chip

ROM/EPROM

Reserved

On-Chip

Block B2

Reserved

External

If MP/MC =1

(Microprocessor Mode)

If MP/MC =0

(Microcomputer Mode on TMS320C25)

(a) Memory Maps After a CNFD Instruction

Pages 4-5

Pages 1-3

Program Program Data

Pages 6 -7

Interrupts

and Reserved

(External)

External

Interrupts

and Reserved

(On-Chip

ROM/EPROM)

On-Chip

Memory-Mapped

Registers

On-Chip

ROM/EPROM Reserved

On-Chip

Block B2

Reserved

External

If MP/MC =1

(Microprocessor Mode)

(b) Memory Maps After a CNFP Instruction

Program Program Data

On-Chip

Block B0

On-Chip

Block B0

Page 0

0(0000h)

31(001Fh)

32(0020h )

65,535(FFFFh)

0(0000h)

31(001Fh)

32(0020h )

65,535(0FFFFh)

0(0000h)0(0000h)

31(001Fh)

32(0020h )

65,279(0FEFFh)

65,280(0FF00h)

5(0005h)

6(0006h)

95(005Fh)

96(0060h )

External

Reserved

4015(0FAFh)

4016(0FB0h)

4095(0FFFh)

4096(1000h)

65,535(0FFFFh)

On-Chip

Block B0

On-Chip

Block B1

127(007Fh)

128(0080h)

511(01FFh)

512(0200h)

767(02FFh)

768(0300h)

1023(03FFh)

1024(0400h)

65,535(0FFFFh)

0(0000h)

31(001Fh)

32(0020h )

4015(0FAFh)

4016(0FB0h)

4095(0FFFh)

4096(1000h)

65,535(0FFFFh)

65,279(0FEFFh)

65,280(0FF00h)

0(0000h)

5(0005h)

6(0006h)

95(005Fh)

96(0060h )

127(007Fh)

128(0080h)

511(01FFh)

512(0200h)

767(02FFh)

768(0300h)

1023(03FFh)

1024(0400h)

65,535(0FFFFh)

Pages 8 -511

Pages 4-5

Pages 1-3

Pages 6 -7

Page 0

On-Chip

Block B1

If MP/MC =0

(Microcomputer Mode on TMS320C25)

Does Not

Exist

Figure 1. Memory Maps

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 9

interrupts and subroutines

The TMS320C2x has three external maskable user interrupts INT2-INT0, available for external devices that

interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),

and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest

priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on

two-word boundaries so that branch instructions can be accommodated in those locations if desired.

A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle

instruction, the interrupt is not processed until the instruction is completed. This mechanism applies to

instructions that are repeated and to instructions that become multicycle due to the READY signal.

external interface

The TMS320C2x supports a wide range of system interfacing requirements. Program, data, and I/O address

spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by

having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the

processor’s external address and data buses in the same manner as memory-mapped devices. Interface to

memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are

made with slower devices, the TMS320C2x processor waits until the other device completes its function and

signals the processor via the READY line. Then, the TMS320C2x continues execution.

A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and

other serial systems. The interface signals are compatible with codecs and many other serial devices with a

minimum of external hardware. The serial port may also be used for intercommunication between processors

in multiprocessing applications.

The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register

(DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same

manner as any other data memory location. Each register has an external clock, a framing synchronization

pulse, and associated shift registers. One method of multiprocessing may be implemented by programming one

device to transmit while the others are in the receive mode. The serial porton the TMS320C25 is double-buffered

and fully static.

multiprocessing

The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements and can

be used as follows:

A standalone processor

A multiprocessor with devices in parallel

A slave/host multiprocessor with global memory space

A peripheral processor interfaced via processor-controlled signals to another device.

For multiprocessing applications, the TMS320C2x has the capability of allocating global data memory space

and communicating with that space via the BR (bus request) and READY control signals. Global memory is data

memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit

memory-mapped GREG (global memory allocation register) specifies part of the TMS320C2x’s data memory

as global external memory. The contents of the register determine the size of the global memory space. If the

current instruction addresses an operand within that space, BR is asserted to request control of the bus. The

length of the memory cycle is controlled by the READY line.

The TMS320C2x supports DMA (direct memory access) to its external program/data memory using the HOLD

and HOLDA signals. Another processor can take complete control of the TMS320C2x’s external memory by

asserting HOLD low. This causes the TMS320C2x to place its address data and control lines in a

high-impedance state, and assert HOLDA. On the TMS320C2x, program execution from on-chip ROM may

proceed concurrently when the device is in the hold mode.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

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POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

instruction set

The TMS320C2x microprocessor implements a comprehensive instruction set that supports both

numeric-intensive signal processing operations as well as general-purpose applications, such as

multiprocessing and high-speed control. The TMS32020 source code is upward-compatible with TMS320C25

source code. TMS32020 object code runs directly on the TMS320C25.

For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the

same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary

depending upon whether the next data operand fetch is from internal or external memory. Highest throughput

is achieved by maintaining data memory on-chip and using either internal or fast external program memory.

addressing modes

The TMS320C2x instruction set provides three memory addressing modes: direct, indirect, and immediate

addressing.

Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the

instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data

memory address. Indirect addressing accesses data memory through the auxiliary registers. In immediate

addressing, the data is based on a portion of the instruction word(s).

In direct memory addressing, the instruction word contains the lower seven bits of the data memory address.

This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus,

memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.

Up to eight auxiliary registers (AR0-AR7) provide flexible and powerful indirect addressing (five on the

TMS32020, eight on the TMS320C25). To select a specific auxiliary register, the Auxiliary Register Pointer

(ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.

There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding

or subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversal

addressing (used in FFTs on the TMS320C25 only) with increment or decrement. All operations are performed

on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary

repeat feature

A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table

read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded

with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this

operand is one less than the number of times that the next instruction is executed. Those instructions that are

normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle

instructions.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

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instruction set summary

Table 2 lists the symbols and abbreviations used in Table 3, the TMS320C25 instruction set summary. Table 3

consists primarily of single-cycle, single-word instructions. Infrequently used branch, I/O, and CALL instructions

are multicycle. The instruction set summary is arranged according to function and alphabetized within each

functional grouping. The symbol (†) indicates those instructions that are not included in the TMS320C1x

instruction set. The symbol (‡) indicates instructions that are not included in the TMS32020 instruction set.

Table 2. Instruction Symbols

SYMBOL DEFINITION

4-bit field specifying a bit code

2-bit field specifying compare mode

Data memory address field

Format status bit

Addressing mode bit

Immediate operand field

Port address (PA0 through PA15 are predefined assembler symbols

equal to 0 through 15, respectively.)

2-bit field specifying P register output shift code

3-bit operand field specifying auxiliary register

4-bit left-shift code

3-bit accumulator left-shift field

NO.

WORDS

DESCRIPTION

X D

S D

MNEMONIC

INSTRUCTION BIT CODE

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

Table 3. TMS320C25 Instruction Set Summary

ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ABS Absolute value of accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1

ADD Addtoaccumulatorwithshift 1 0000 I

ADDC‡Addtoaccumulatorwithcarry 1 01000011I

ADDH Addtohighaccumulator 1 01001000I

ADDK‡Add to accumulator short immediate 1 11001100

ADDS Addtolowaccumulatorwithsign

extension suppressed 101001001I

ADDT Add to accumulator with shift specified by

T register 101001010I

ADLK†Add to accumulator long immediate with shift 2 11 0 1 00000010

AND AND with accumulator 1 01001110I

ANDK†AND immediate with accumulator with shift 2 11 0 1 00000100

CMPL†Complement accumulator 1 1100111000100111

LAC Load accumulator with shift 1 0010 I

LACK Load accumulator immediate short 1 11001010

LACT†Load accumulator with shift specified by

T register 101000010I

LALK†Load accumulator long immediate with shift 2 11 0 1 00000001

NEG†Negate accumulator 1 1100111000100011

NORM†Normalize contents of accumulator 1 110011101XXX0010

OR OR with accumulator 1 01001101I

ORK†OR immediate with accumulator with shift 2 11 0 1 00000101

ROL‡Rotate accumulator left 1 1100111000110100

ROR‡Rotate accumulator right 1 1100111000110101

SACH Store high accumulator with shift 1 01101 I

SACL Store low-order accumulator with shift 1 01100 I

SBLK† Subtract from accumulator long immediate

with shift 211 0 1 00000011

SFL†Shift accumulator left 1 1100111000011000

SFR†Shift accumulator right 1 1100111000011001

SUB Subtract from accumulator with shift 1 0001 I

SUBB‡Subtract from accumulator with borrow 1 01001111I

SUBC Conditional subtract 1 01000111I

SUBH Subtract from high accumulator 1 01000100I

SUBK‡Subtract from accumulator short immediate 1 11001101

SUBS Subtract from low accumulator with sign

extension suppressed 1 0 1 0 0 0 1 0 1 I

†These instructions are not included in the TMS320C1x instruction set.

‡These instructions are not included in the TMS32020 instruction set.

NO.

WORDS

DESCRIPTION INSTRUCTION BIT CODE

MNEMONIC

NO.

WORDS

DESCRIPTION INSTRUCTION BIT CODE

MNEMONIC

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 13

Table 3. TMS320C25 Instruction Set Summary (continued)

ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SUBT†Subtract from accumulator with shift specified by

T register 1 0 1 0 0 0 1 1 0 I

XOR Exclusive-OR with accumulator 1 01001100I

XORK†Exclusive-OR immediate with accumulator with

shift 211 0 1 00000110

ZAC Zero accumulator 1 1100101000000000

ZALH Zero low accumulator and load high accumulator 1 01000000I

ZALR‡Zero low accumulator and load high accumulator

with rounding 101111011I

ZALS Zero accumulator and load low accumulator with

sign extension suppressed 101000001I

AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADRK‡Add to auxiliary register short immediate 1 0 1 1 1 1 1 1 0

CMPR†Compare auxiliary register with auxiliary

LAR Load auxiliary register 1 00110 I

LARK Load auxilliary register short immediate 1 11000

LARP Load auxilliary register pointer 1 0101010110001

LDP Load data memory page pointer 1 01010010I

LDPK Load data memory page pointer immediate 1 1100100

LRLK†Load auxiliary register long immediate 2 11010 00000000

MAR Modify auxiliary register 1 01010101I

SAR Store auxiliary register 1 01110 I

SBRK‡Subtract from auxiliary register short immediate 1 0 1 1 1 1 1 1 1

†These instructions are not included in the TMS320C1x instruction set.

‡These instructions are not included in the TMS32020 instruction set.

NO.

WORDS

DESCRIPTION INSTRUCTION BIT CODE

MNEMONIC

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

Table 3. TMS320C25 Instruction Set Summary (continued)

T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

APAC Add P register to accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1

LPH†Load high P register 1 01010011I

LT Load T register 1 00111100I

LTA Load T register and accumulate previous product 1 00111101I

LTD Load T register, accumulate previous product,

and move data 100111111I

LTP†Load T register and store P register in

accumulator 100111110I

LTS†Load T register and subtract previous product 1 01011011I

MAC†Multiply and accumulate 2 01011101I

MACD†Multiply and accumulate with data move 2 01011100I

MPY Multiply (with T register, store product in

P register) 100111000I

MPYA‡Multiply and accumulate previous product 1 00111010I

MPYK Multiply immediate 1 101

MPYS‡ Multiply and subtract previous product 1 00111011I

MPYU‡ Multiply unsigned 1 11001111I

PAC Load accumulator with P register 1 1100111000010100

SPAC Subtract P register from accumulator 1 1100111000010110

SPH‡Store high P register 1 01111101I

SPL‡Store low P register 1 01111100I

SPM†Set P register output shift mode 1 11001110000010

SQRA†Square and accumulate 1 00111001I

SQRS†Square and subtract previous product 1 0 1 0 1 1 0 1 0 I

†These instructions are not included in the TMS320C1x instruction set.

‡These instructions are not included in the TMS32020 instruction set.

NO.

WORDS

DESCRIPTION

INSTRUCTION BIT CODE

MNEMONIC

NO.

WORDS

DESCRIPTION INSTRUCTION BIT CODE

MNEMONIC

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 15

Table 3. TMS320C25 Instruction Set Summary (continued)

BRANCH/CALL INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BBranch unconditionally 2 1 1 1 1 1 1 1 1 1

BACC†Branch to address specified by accumulator 1 1100111000100101

BANZ Branch on auxiliary register not zero 2 111110111

BBNZ†Branch if TC bit 02111110011

BBZ†Branch if TC bit = 0 2 111110001

BC‡Branchoncarry 2 010111101

BGEZ Branch if accumulator 02111101001

BGZ Branch if accumulator > 0 2 111100011

BIOZ Branch on I/O status = 0 2 111110101

BLEZ Branch if accumulator 02111100101

BLZ Branch if accumulator < 0 2 111100111

BNC‡Branchonnocarry 2 010111111

BNV†Branchifnooverflow 2 111101111

BNZ Branch if accumulator 02111101011

BV Branchonoverflow 2 111100001

BZ Branch if accumulator = 0 2 111101101

CALA Call subroutine indirect 1 1100111000100100

CALL Call subroutine 2 111111101

RET Return from subroutine 1 1100111000100110

I/O AND DATA MEMORY OPERATIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLKD†Block move from data memory to data memory 2 1 1 1 0 1 1 0 1 I

BLKP†Block move from program memory to data

memory 211111100I

DMOV Data move in data memory 1 01010110I

FORT†Format serial port registers 1 110011100000111FO

IN Input data from port 1 1000 I

OUT Output data to port 1 1110 I

RFSM‡Reset serial port frame synchronization mode 1 1100111000110110

RTXM†Reset serial port transmit mode 1 1100111000100000

RXF†Reset external flag 1 1100111000001100

SFSM‡Set serial port frame synchronization mode 1 1100111000110111

STXM†Set serial port transmit mode 1 1100111000100001

SXF†Set external flag 1 1100111000001101

TBLR Table read 1 01011000I

TBLW Table write 1 0 1 0 1 1 0 0 1 I

†These instructions are not included in the TMS320C1x instruction set.

‡These instructions are not included in the TMS32020 instruction set.

NO.

WORDS

DESCRIPTION INSTRUCTION BIT CODE

MNEMONIC

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

Table 3. TMS320C25 Instruction Set Summary (concluded)

CONTROL INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT†Test bit 1 1 0 0 1 I

BITT†Test bit specified by T register 1 01010111I

CNFD†Configure block as data memory 1 1100111000000100

CNFP†Configure block as program memory 1 1100111000000101

DINT Disable interrupt 1 1100111000000001

EINT Enable interrupt 1 1100111000000000

IDLE†Idle until interrupt 1 1100111000011111

LST Load status register STO 1 01010000I

LST1†Load status register ST1 1 01010001I

NOP No operation 1 0101010100000000

POP Pop top of stack to low accumulator 1 1100111000011101

POPD†Pop top of stack to data memory 1 01111010I

PSHD†Push data memory value onto stack 1 01010100I

PUSH Push low accumulator onto stack 1 1100111000011100

RC‡Reset carry bit 1 1100111000110000

RHM‡Reset hold mode 1 1100111000111000

ROVM Reset overflow mode 1 1100111000000010

RPT†Repeat instruction as specified by data

memory value 101001011I

RPTK†Repeat instruction as specified by immediate

value 111001011

RSXM†Reset sign-extension mode 1 1100111000000110

RTC‡Reset test/control flag 1 1100111000110010

SC‡Set carry bit 1 1100111000110001

SHM‡Set hold mode 1 1100111000111001

SOVM Set overflow mode 1 1100111000000011

SST Store status register ST0 1 01111000I

SST1†Store status register ST1 1 01111001I

SSXM†Set sign-extension mode 1 1100111000000111

STC‡Set test/control flag 1 1100111000110011

TRAP†Software interrupt 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0

†These instructions are not included in the TMS320C1x instruction set.

‡These instructions are not included in the TMS32020 instruction set.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 17

TMS32020 PRODUCT NOTIFICATION

Texas Instruments has identified an unusual set of circumstances that will cause the BIT (Test Bit) instruction

on the TMS32020 to affect the contents of the accumulator; ideally, the BIT instruction should not affect the

accumulator. This set of conditions is:

1. The overflow mode is set (the OVM status register bit is set to one.)

2. And, the two LSBs of the BIT instruction opcode word are zero.

a. When direct memory addressing is used, every fourth data word is affected; all other locations are not

affected.

b. When indirect addressing is used, the two LSBs will be zero if a new ARP is not selected or if a new

ARP is selected and that ARP is 0 or 4.

3. And, adding the contents of the accumulator with the contents of the addressed data memory location,

shifted by 2 (bit code), causes an overflow of the accumulator.

If all of these conditions are met, the contents of the accumulator will be replaced by the positive or negative

saturation value, depending on the polarity of the overflow.

Various methods for avoiding this phenomenon are available:

If the TMS32020 is not in the saturation mode when the BIT instruction is executed, the device operates

properly and the accumulator is not affected.

Execute the Reset Overflow Mode (ROVM) instruction immediately prior to the BIT instruction and the Set

Overflow Mode (SOVM) instruction immediately following the BIT instruction.

If direct memory addressing is being used during the BIT instructions, reorganize memory so that the page

relativelocations0,4,8,C,10...arenotused.

If indirect addressing is being used during the Bit instruction, select a new ARP which is not AR0 or AR4.

If necessary, follow the instruction with a LARP AR0 or LARP AR4 to restore the code.

Use the Test Bit Specified by T Register (BITT) instruction instead of the BIT instruction. The BITT instruction

operates correctly and will not affect the accumulator under any circumstances.

Replace TMS32020 with TMS320C25 for ideal pin-to-pIn and object-code compatibility. The BIT instruction

on the TMS320C25 executes properly and will not affect the accumulator under any circumstances.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

development support

Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development

support products to assist the user in all aspects of TMS320 second-generation-based design and

development. These products range from development and application software to complete hardware

development and evaluation systems. Table 4 lists the development support products for the second-generation

TMS320 devices.

System development may begin with the use of the simulator, Software Development System (SWDS), or

emulator (XDS) along with an assembler/linker. These tools give the TMS320 user various means of evaluation,

from software simulation of the second-generation TMS320s (simulator) to full-speed in-circuit emulation with

hardware and software breakpoint trace and timing capabilities (XDS).

Software and hardware can be developed simultaneously by using the macro assembler/linker, C compiler, and

simulator for software development, the XDS for hardware development, and the Software Development

System for both software development and limited hardware development.

Many third-party vendors offer additional development support for the second-generation TMS320s, including

assembler/linkers, simulators, high-level languages, applications software, algorithm development tools,

application boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family

Development Support Reference Guide (SPRU011A) for further information about TMS320 development

support products offered by both Texas Instruments and its third-party suppliers.

Additional support for the TMS320 products consists of an extensive library or product and applications

documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs).

These workshops provide insight into the architecture and the instruction set of the second-generation

TMS320s as well as hands-on training with the TMS320 development tools. When technical questions arise

regarding the TMS320 family, contact the Texas Instruments TMS320 Hotline at (713) 274-2320. Or, keep

informed on the latest TI and third-party development support tools by accessing the DSP Bulletin Board Service

(BBS) at (713) 274-2323. The BBS serves 2400-, 1200- and 300-bps modems. Also, TMS320 application

source code may be downloaded from the BBS.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 19

Table 4. TMS320 Second-Generation Software and Hardware Support

SOFTWARE TOOLS PART NUMBER

Macro Assembler/Linker

IBM MS/PC-DOS TMDS3242850-02

VAX/VMS TMDS3242250-08

VAX ULTRIX TMDS3242260-08

SUN UNIX TMDS3242550-08

Simulator

IBM MS/PC-DOS TMDS3242851-02

VAX/VMS TMDS3242251-08

C Compiler

IBM MS/PC-DOS TMDX3242855-02

VAX/VMS TMDX3242255-08

VAX ULTRIX TMDX3242265-08

SUN UNIX TMDX3242555-08

Digital Filter Design Package (DFDP)

IBM PC-DOS DFDP-IBM002

DSP Software Library

IBM MS/PC-DOS TMDC3240812-12

VAX/VMS TMDC3204212-18

HARDWARE TOOLS PART NUMBER

Analog Interface Board 2 (AIB2) RTC/AIB320A-06

Analog Interface Board Adaptor RTC/ADP320A-06

EPROM Programmer Adaptor Socket

(68to28-pin) TMDX3270120

Software Development System (SWDS) TMDX3268821

XDS/22 Emulator (see Note) TMDS3262221

XDS/22 Upgrade (TMS32020 to TMS320C2x) TMDX3282226

NOTE: Emulation support for the TMS320C25-50 is available from Macrochip

Research, Inc.; refer to the TMS320 Family Development Support Reference

Guide (SPRU011A) for the mailing address.

IBM is a trademark of International Business Machines Corporation.

PC-DOS is a trademark of International Business Machines Corporation.

VAX and VMS are trademarks of Digital Equipment Corporation.

XDS is a trademark of Texas Instruments Incorporated.

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

documentation support

Extensive documentation supports the second-generation TMS320 devices from product announcement

through applications development. The types of documentation include data sheets with design specifications,

complete user’s guides, and 750 pages of application reports published in the book, Digital Signal Processing

Applications with the TMS320 Family (SPRA012A). An application report, Hardware Interfacing to the

TMS320C25 (SPRA014A), is available for that device.

A series of DSP textbooks is being published by Prentice-Hall and John Wiley & Sons to support digital signal

processing research and education. The TMS320 newsletter, Details on Signal Processing, is published

quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board

service provides access to large amounts of information pertaining to the TMS320 family.

Refer to the TMS320 Family Development Support Reference Guide (SPRU011A) for further information about

TMS320 documentation. To receive copies of second-generation TMS320 literature, call the Customer

Response Center at 1-800-232-3200.

specification overview

The electrical specifications for the TMS32020, TMS320C25, TMS320E25, and TMS320C25-50 are given in

the following pages. Note that the electrical specifications for the TMS320E25 are identical to those for the

TMS320C25, with the addition of EPROM-related specifications. A summary of differences between

TMS320C25 and TMS320C25-50 specifications immediately follows the TMS320C25-50 specification.

High-level input voltage

Low-level input voltageVIL

VIH

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 21

absolute maximum ratings over specified temperature range (unless otherwise noted)†

Supply voltage range, VCC‡--0.3Vto7V.......................................................

Input voltage range --0.3Vto7V................................................................

Output voltage range --0.3Vto7V..............................................................

Continuous power dissipation 2W...............................................................

Operating free-air temperature range 0Cto70C.................................................

Storage temperature range -- 55C to 150C......................................................

†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

VCC Supply voltage 4.75 55.25 V

VSS Supply voltage 0 V

All inputs except CLKIN 2 VCC +0.3 V

CLKIN 2.4 VCC +0.3 V

All inputs except CLKIN -- 0 . 3 0.8 V

CLKIN -- 0 . 3 0.8 V

IOH High-level output current 300 A

IOL Low-level output current 2mA

TAOperating free-air temperature (see Notes 1 and 2) 070 C

NOTES: 1. Case temperature (TC) must be maintained below 90C.

2. RJA =36C/Watt, RJC =6C/Watt.

electrical characteristics over specified free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT

VOH High-level output voltage VCC =MIN,I

OH =MAX 2.4 3 V

VOL Low-level output voltage VCC =MIN,I

OL =MAX 0.3 0.6 V

IZThree-state current VCC =MAX -- 2 0 20 A

IIInput current VI=V

SS to VCC -- 1 0 10 A

TA=0C, VCC = MAX, fx=MAX 360 mA

ICC Supply current TA=25C, VCC = MAX, fx=MAX 250 mA

TC=90C, VCC = MAX, fx=MAX 285 mA

CIInput capacitance 15 pF

COOutput capacitance 15 pF

§All typical values for ICC are at VCC =5V,T

A=25C.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These

circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,

Method 3015; however, it is advised that precautions should be taken to avoid application of any voltage higher than maximum-rated

voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device

should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either

VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling

Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

CLOCK CHARACTERISTICS AND TIMING

The TMS32020 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency

of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be fundamental

mode, and parallel resonant, with an effective series resistance of 30 , a power dissipation of 1 mW,

and be specified at a load capacitance of 20 pF.

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

fxInput clock frequency TA=0Cto70C6.7 20.5 MHz

fxs Serial port frequency TA=0Cto70C50†2563 MHz

C1, C2 TA=0Cto70C10 pF

†Value derived from characterization data; minimum fsx at test = 825 kHz.

X2/CLKIN

C2C1

Crystal

Figure 2. Internal Clock Option

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected. The external frequency injected must conform to the specifications listed in the following table.

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN NOM MAX UNIT

tc(C) CLKOUT1/CLKOUT2 cycle time 195 597 ns

td(CIH-C) CLKIN high to CLKOUT1/CLKOUT2/STRB high/low 25 60 ns

tf(C) CLKOUT1/CLKOUT2/STRB fall time 10 ns

tr(C) CLKOUT1/CLKOUT2/STRB rise time 10 ns

tw(CL) CLKOUT1/CLKOUT2 low pulse duration 2Q -- 15 2Q 2Q + 15 ns

tw(CH) CLKOUT1/CLKOUT2 high pulse duration 2Q -- 15 2Q 2Q + 15 ns

td(C1-C2) CLKOUT1hightoCLKOUT2low,CLKOUT2hightoCLKOUT1high,etc. Q--10 QQ+10 ns

NOTE 3: Q = 1/4tc(C).

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 23

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

tc(C) CLKIN cycle time 195 597 ns

tf(CI) CLKIN fall time 10†ns

tr(CI) CLKIN rise time 10†ns

tw(CIL) CLKIN low pulse duration, tc(CI) =50ns(seeNote4) 40 ns

tw(CIH) CLKIN high pulse duration, tc(CI) =50ns(seeNote4) 40 ns

tsu(S) SYNC setup time before CLKIN low 10 Q--10 ns

th(S) SYNC hold time from CLKIN low 15 ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

4. CLKIN duty cycle [tr(CI) +t

w(CIH)] /t

c(CI) must be within 40-60%.

CL= 100 pF

2.15 V

RL= 825 

Test

Point

From Output

Under Test

Figure 3. Test Load Circuit

0.80 V

0.92 V

1.88 V

2.0 V

VIH (Min)

VIL (Max)

(a) Input

0.6 V

0.8 V

2.2 V

2.4 V

VOH (Min)

VOL (Max)

(b) Output

Figure 4. Voltage Reference Levels

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT

td(C1-S) STRB from CLKOUT1 (if STRB is present) Q--15 QQ+15 ns

td(C2-S) CLKOUT2 to STRB (if STRB is present) -- 1 5 015 ns

tsu(A) Address setup hold time before STRB low(seeNote5) Q--30 ns

th(A) Address hold time after STRB high (see Note 5) Q--15 ns

tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q ns

tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q ns

tsu(D)W Data write setup time before STRB high (no wait states) 2Q -- 45 ns

th(D)W DatawriteholdtimefromSTRBhigh Q--15 Qns

ten(D) Data bus starts being driven after STRB low (write cycle) 0†ns

tdis(D) Data bus three-state after STRB high (write cycle) QQ+30

†ns

td(MSC) MSC valid from CLKOUT1 -- 2 5 025 ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

5. A15-A0, PS,DS,IS,R/W, and BR timings are all included in timings referenced as “address”.

6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with

no wait states.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

ta(A) Read data access time from address time (read cycle, see Notes 5 and 7) 3Q -- 70†ns

tsu(D)R Data read setup time before STRB high 40 ns

th(D)R Data read hold time from STRB high 0ns

td(SL-R) READY valid after STRB low (no wait states) Q--40 ns

td(C2H-R) READY valid after CLKOUT2 high Q--40 ns

th(SL-R) READYholdtimeafterSTRBlow (no wait states) Q--5 ns

th(C2H-R) READY hold after CLKOUT2 high Q--5 ns

td(M-R) READY valid after MSC valid 2Q -- 50 ns

th(M-R) READY hold time after MSC valid 0ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

5. A15-A0, PS,DS,IS,R/W, and BR timings are all included in timings referenced as “address”.

7. Read data access time is defined as ta(A) =t

su(A) +t

w(SL) -- t su(D)R.

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 25

RS,INT,BIO, AND XF TIMING

switching characteristics over recommended operating conditions (see Note 3 and 8)

PARAMETER MIN TYP MAX UNIT

td(RS) CLKOUT1 low to reset state entered 45 ns

td(IACK) CLKOUT1 to IACK valid -- 2 5 025 ns

td(XF) XF valid before falling edge of STRB Q--30 ns

NOTES: 3. Q = 1/4tc(C).

8. RS,INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met,

the exact sequence shown in the timing diagrams will occur.

timing requirements over recommended operating conditions (see Note 3 and 8)

MIN NOM MAX UNIT

tsu(IN) INT/BIO/RS setup before CLKOUT1 high 50 ns

th(IN) INT/BIO/RS hold after CLKOUT1 high 0ns

tf(IN) INT/BIO fall time 15†ns

tw(IN) INT/BIO low pulse duration tc(C) ns

tw(RS) RS low pulse duration 3tc(C) ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

8. RS,INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met,

the exact sequence shown in the timing diagrams will occur.

HOLD TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT

td(C1L-AL) HOLDA low after CLKOUT1 low -- 2 5 †25 ns

tdis(AL-A) HOLDA low to address three-state 15†ns

tdis(C1L-A) Address three-state after CLKOUT1 low (HOLD mode, see Note 9) 30†ns

td(HH-AH) HOLD high to HOLDA high 50 ns

ten(A-C1L) Address driven before CLKOUT1 low (HOLD mode, see Note 9) 10†ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

9. A15-A0, PS,DS,IS,STRB, and R/W timings are all included in timings referenced as “address.”

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

td(C2H-H) HOLD valid after CLKOUT2 high Q--45 ns

NOTE 3: Q = 1/4tc(C).

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

SERIAL PORT TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT

td(CH-DX) DX valid after CLKX rising edge (see Note 10) 100 ns

td(FL-DX) DX valid after FSX falling edge (TXM = 0, see Note 10) 50 ns

td(CH-FS) FSX valid after CLKX rising edge (TXM = 1) 60 ns

NOTES: 3. Q = 1/4tc(C).

10. The last occurrence of FSX falling and CLKX rising.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

tc(SCK) Serial port clock (CLKX/CLKR) cycle time 390 20 000†ns

tf(SCK) Serial port clock (CLKX/CLKR) fall time 50‡ns

tr(SCK) Serial port clock (CLKX/CLKR) rise time 50‡ns

tw(SCK) Serial port clock (CLKX/CLKR) low pulse duration (see Note 11) 150 12 000 ns

tw(SCK) Serial port clock (CLKX/CLKR) high pulse duration (see Note 11) 150 12 000 ns

tsu(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) 20 ns

th(FS) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) 20 ns

tsu(DR) DR setup time before CLKR falling edge 20 ns

th(DR) DR hold time after CLKR falling edge 20 ns

†Value derived from characterization data; minimum fsx at test = 825 kHz.

‡Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

11. The duty cycle of the serial port clock must be within 40-60%.

ADVANCE INFORMATION

VIL

Low-level input voltage

Operating free-air temperature

ICC Low-level input voltage TA=0C, VCC = MAX, fx=MAX mA

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 27

absolute maximum ratings over specified temperature range (unless otherwise noted)†

Supply voltage range, VCC‡--0.3Vto7V.......................................................

Input voltage range: TMS320E25 pins 24 and 25 -- 0.3 V to 15 V....................................

All other inputs -- 0.3 V to 7 V................................................

Output voltage range --0.3Vto7V..............................................................

Continuous power dissipation 1.5 W.............................................................

Operating free-air temperature range 0Cto70C.................................................

Storage temperature range -- 55C to 150C......................................................

†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

VCC Supply voltage 4.75 55.25 V

VSS Supply voltage 0 V

All inputs except CLKIN/CLKX/CLKR/INT (0-2) 2.35 VCC +0.3 V

VIH High-level input voltage INT (0-2) 2.5 VCC +0.3 V

CLKIN/CLKX/CLKR 3.5 VCC +0.3 V

All inputs except MP/MC -- 0 . 3 0.8 V

MP/MC -- 0 . 3 0.8 V

IOH High-level output current 300 A

IOL Low-level output current 2mA

TMS320C25, TMS320E25 070 C

TMS320C25GBA -- 4 0 85 C

electrical characteristics over specified free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT

VOH High-level output voltage VCC =MIN,I

OH =MAX 2.4 3 V

VOL Low-level output voltage VCC =MIN,I

OL =MAX 0.3 0.6 V

IZThree-state current VCC =MAX -- 2 0 20 A

IIInput current VI=V

SS to VCC -- 1 0 10 A

Normal 110 185

Idle/HOLD 50 100

CIInput capacitance 15 pF

COOutput capacitance 15 pF

§All typical values are at VCC =5V,T

A=25.

Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic

fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to

MIL-STD-883C, Method 3015; however, it is advised that precautions to be taken to avoid application of any voltage higher than

maximum rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together

or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level,

preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication “Guidelines for Handling

Electrostatic-Discharge Sensitive (ESDS) Devices and Assemblies” available from Texas Instruments

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

CLOCK CHARACTERISTICS AND TIMING

The TMS32025 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency

of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be either fundamental

or overtone mode, and parallel resonant, with an effective series resistance of 30 , a power dissipation

of 1 mW, and be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned

LC circuit; see the application report, Hardware Interfacing to the TMS320C25 (SPRA014A).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fxInput clock frequency TA=0Cto70C6.7 40.96 MHz

fxs Serial port frequency TA=0Cto70C 0†5120 MHz

C1, C2 TA=0Cto70C10 pF

†The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down

to fsx =0Hz.

X2/CLKIN

C2C1

Crystal

Figure 2. Internal Clock Option

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected. The external frequency injected must conform to the specifications listed in the following table.

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT

tc(C) CLKOUT1/CLKOUT2 cycle time 97.7 597 ns

td(CIH-C) CLKIN high to CLKOUT1/CLKOUT2/STRB high/low 530 ns

tf(C) CLKOUT1/CLKOUT2/STRB fall time 5ns

tr(C) CLKOUT1/CLKOUT2/STRB rise time 5ns

tw(CL) CLKOUT1/CLKOUT2 low pulse duration 2Q -- 8 2Q 2Q + 8 ns

tw(CH) CLKOUT1/CLKOUT2 high pulse duration 2Q -- 8 2Q 2Q + 8 ns

td(C1-C2)CLKOUT1hightoCLKOUT2low,CLKOUT2hightoCLKOUT1high,etc. Q--5 QQ+5 ns

NOTE 3: Q = 1/4tc(C).

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 29

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

tc(CI) CLKIN cycle time 24.4 150 ns

tf(CI) CLKIN fall time 5†ns

tr(CI) CLKIN rise time 5†ns

tw(CIL) CLKIN low pulse duration, tc(CI) =50ns(seeNote4) 20 ns

tw(CIH) CLKIN high pulse duration, tc(CI) =50ns(seeNote4) 20 ns

tsu(S) SYNC setup time before CLKIN low 5Q--5 ns

th(S) SYNC hold time from CLKIN low 8ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

4. CLKIN duty cycle [tr(CI) +t

w(CIH)]/tc(CI) must be within 40-60%.

+5 V fcrystal

4.7 k

10 k

74HC04

F11

CLKIN

47 pF 74AS04 10 k

C = 20 pF 0.1 F

TMS320C25

TMS320C25-50

TMS320E25

40.96

51.20

40.96

1.8

1.0

1.8

fcrystal, (MHz) L, (H)

Figure 3. External Clock Option

Shown above is a crystal oscillator circuit suitable for providing the input clock signal to the TMS320C25,

TMS320E25, and TMS320C25-50. Please refer to Hardware Interfacing to the TMS320C25 (document number

SPRA014A) for details on circuit operation.

CL= 100 pF

2.15 V

RL= 825 

Test

Point

From Output

Under Test

Figure 4. Test Load Circuit

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

0.80 V

0.92 V

1.88 V

2.0 V

VIH (Min)

VIL (Max)

(a) Input

0.6 V

0.8 V

2.2 V

2.4 V

VOH (Min)

VOL (Max)

(b) Output

Figure 5. Voltage Reference Levels

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT

td(C1-S) STRB from CLKOUT1 (if STRB is present) Q--6 QQ+6 ns

td(C2-S) CLKOUT2 to STRB (if STRB is present) -- 6 0 6 ns

tsu(A) Address setup time before STRB low(seeNote5) Q--12 ns

th(A) Address hold time after STRB high (see Note 5) Q--8 ns

tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q -- 5 2Q + 5 ns

tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q -- 5 2Q + 5 ns

tsu(D)W Data write setup time before STRB high (no wait states) 2Q -- 20 ns

th(D)W DatawriteholdtimefromSTRBhigh Q--10 Qns

ten(D) Data bus starts being driven after STRB low (write cycle) 0†ns

tdis(D) Data bus three-state after STRB high (write cycle) QQ+15

†ns

td(MSC) MSC valid from CLKOUT1 -- 1 2 012 ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

5. A15-A0, PS,DS,IS,R/W, and BR timings are all included in timings referenced as “address”.

6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait

states.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

ta(A) Read data access time from address time (read cycle, see Notes 5 and 7) 3Q -- 35 ns

tsu(D)R Data read setup time before STRB high 23 ns

th(D)R Data read hold time from STRB high 0ns

td(SL-R) READY valid after STRB low (no wait states) Q--20 ns

td(C2H-R) READY valid after CLKOUT2 high Q--20 ns

th(SL-R) READYholdtimeafterSTRBlow (no wait states) Q+3 ns

th(C2H-R) READY hold after CLKOUT2 high Q+3 ns

td(M-R) READY valid after MSC valid 2Q -- 25 ns

th(M-R) READY hold time after MSC valid 0ns

NOTES: 3. Q = 1/4tc(C).

5. A15-A0, PS,DS,IS,R/W, and BR timings are all included in timings referenced as “address”.

7. Read data access time is defines as ta(A) =t

su(A) +t

w(SL) -- t su(D)R.

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 31

RS,INT,BIO, AND XF TIMING

switching characteristics over recommended operating conditions (see Note 3 and 8)

PARAMETER MIN TYP MAX UNIT

td(RS) CLKOUT1 low to reset state entered 22†ns

td(IACK) CLKOUT1 to IACK valid -- 6 012 ns

td(XF) XF valid before falling edge of STRB Q--15 ns

NOTES: 3. Q = 1/4tc(C).

8. RS,INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is

met, the exact sequence shown in the timing diagrams will occur.

timing requirements over recommended operating conditions (see Note 3 and 8)

MIN NOM MAX UNIT

tsu(IN) INT/BIO/RS setup before CLKOUT1 high 32 ns

th(IN) INT/BIO/RS hold after CLKOUT1 high 0ns

tf(IN) INT/BIO fall time 8†ns

tw(IN) INT/BIO low pulse duration tc(C) ns

tw(RS) RS low pulse duration 3tc(C) ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

8. RS,INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is

met, the exact sequence shown in the timing diagrams will occur.

HOLD TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT

td(C1L-AL) HOLDA low after CLKOUT1 low 010 ns

tdis(AL-A) HOLDA low to address three-state 0†ns

tdis(C1L-A) Address three-state after CLKOUT1 low (HOLD mode, see Note 9) 20†ns

td(HH-AH) HOLD high to HOLDA high 25 ns

ten(A-C1L) Address driven before CLKOUT1 low (HOLD mode, see Note 9) 8†ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

9. A15-A0, PS,DS,IS,STRB, and R/W timings are all included in timings referenced as “address.”

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

td(C2H-H) HOLD valid after CLKOUT2 high Q--24 ns

NOTE 3: Q = 1/4tc(C).

ADVANCE INFORMATION

TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

SERIAL PORT TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT

td(CH-DX) DX valid after CLKX rising edge (see Note 10) 75 ns

td(FL-DX) DX valid after FSX falling edge (TXM = 0, see Note 10) 40 ns

td(CH-FS) FSX valid after CLKX rising edge (TXM = 1) 40 ns

NOTES: 3. Q = 1/4tc(C).

10. The last occurrence of FSX falling and CLKX rising.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

tc(SCK) Serial port clock (CLKX/CLKR) cycle time†200 ns

tf(SCK) Serial port clock (CLKX/CLKR) fall time 25‡ns

tr(SCK) Serial port clock (CLKX/CLKR) rise time 25‡ns

tw(SCK) Serial port clock (CLKX/CLKR) low pulse duration (see Note 11) 80 ns

tw(SCK) Serial port clock (CLKX/CLKR) high pulse duration (see Note 11) 80 ns

tsu(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) 18 ns

th(FS) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) 20 ns

tsu(DR) DR setup time before CLKR falling edge 10 ns

th(DR) DR hold time after CLKR falling edge 20 ns

†The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down

to fsx =0Hz.

‡Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

11. The duty cycle of the serial port clock must be within 40-60%.

ADVANCE INFORMATION

TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 33

EPROM PROGRAMMING

absolute maximum ratings over specified temperature range (unless otherwise noted)†

Supply voltage range, VPP‡-- 0.6 V to 15 V.......................................................

Input voltage range on pins 24 and 25 -- 0.3 V to 15 V.............................................

†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡All voltage values are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT

VCC Programming mode supply voltage (see Note 13) 6 V

VCC Read mode supply voltage 4.75 55.25 V

VPP Programming mode supply voltage 12 12.5 13 V

VPP Read mode supply voltage (see Note 12) VCC V

NOTES: 12. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC +I

.During

programming, VPP must be maintained at 12.5 V (0.25 V).

13. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP

. This device must not be

inserted into or removed from the board when VPP or VCC is applied.

electrical characteristics over specified temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT

IPP1 VPP supply current VPP =V

CC =5.25V 100 A

IPP2 VPP supply current (during program pulse) VPP =13V 30 50 mA

§All typical values for ICC are at VCC =5V,T

A=25C.

recommended timing requirements for programming, TA=25C, VCC =6V,V

PP = 12.5 V

(see Notes 14 and 15)

MIN NOM MAX UNIT

tw(IPGM) Initial program pulse duration 0.95 11.05 ms

tw(FPGM) Final pulse duration 2.85 78.75 ms

tsu(A) Address setup time 2s

tsu(E) Esetup time 2s

tsu(G) Gsetup time 2s

tdis(G) Output disable time from G 0 130¶ ns

ten(G) Output enable time from G150¶ ns

tsu(D) Data setup time 2s

tsu(VPP) VPP setup time 2s

tsu(VCC) VCC setup time 2s

th(A) Address hold time 0s

th(D) Data hold time 2s

¶Value derived from characterization data and not tested.

NOTES: 14. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V 0.5 V during

programming.

15. Common test conditions apply for tdis(G) except during programming.

ADVANCE INFORMATION

ICC TA=0C, VCC = MAX, fx=MAX mASupply current

TMS320C2550

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

absolute maximum ratings over specified temperature range (unless otherwise noted)†

Supply voltage range, VCC‡--0.3Vto7V........................................................