Product Specification PE42540 UltraCMOS(R) SP4T RF Switch 10 Hz-8 GHz Product Description Features The PE42540 is a HaRPTM technology-enhanced absorptive SP4T RF switch developed on UltraCMOS(R) process technology. This switch is designed specifically to support the requirements of the test equipment and ATE market. It comprises four symmetric RF ports and has very high isolation. An on-chip CMOS decode logic facilitates a two-pin low voltage CMOS control interface and an optional external VSS feature. High ESD tolerance and no blocking capacitor requirements make this the ultimate in integration and ruggedness. HaRPTM technology enhanced Fast settling time Eliminates gate and phase lag No drift in insertion loss and phase High linearity: 58 dBm IIP3 Low insertion loss: 0.8 dB @ 3 GHz, 1.0 dB @ 6 GHz and 1.2 dB @ 8 GHz High isolation: 45 dB @ 3 GHz, The PE42540 is manufactured on Peregrine's UltraCMOS process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. 39 dB @ 6 GHz and 31 dB @ 8 GHz Maximum power handling: 30 dBm @ 8 GHz High ESD tolerance of 2 kV HBM on RFC and 1 kV HBM on all other pins Figure 1. Functional Diagram Figure 2. Package Type 32-lead 5 x 5 mm LGA RFC RF1 RF2 ESD ESD 50 50 RF3 RF4 ESD 50 ESD 50 CMOS Control/ Driver and ESD 71-0067 VDD Document No. DOC-32914-3 | V1 V2 VssEXT www.psemi.com (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 12 PE42540 Product Specification Table 1. Electrical Specifications @ +25C, VDD = 3.3V, VSS_EXT = 0V (ZS = ZL = 50) Parameter Condition Min Typ 10 Hz1 Operating frequency Max Unit 8 GHz dB dB dB dB dB RFC-RFX insertion loss RFX-RFX isolation 10 Hz-9 kHz 3000 MHz 6000 MHz 7500 MHz 8000 MHz 70 40 34 27 25 80 45 39 32 31 dB dB dB dB dB RFC-RFX isolation 10 Hz-9 kHz 3000 MHz 6000 MHz 7500 MHz 8000 MHz 74 40 28 24 21 84 45 33 29 27 dB dB dB dB dB Return loss (RFC to active port) 10 Hz-9 kHz 3000 MHz 6000 MHz 7500 MHz 8000 MHz 24 23 18 14 13 dB dB dB dB dB Return loss (terminated port) 10 Hz-9 kHz 3000 MHz 6000 MHz 7500 MHz 8000 MHz 35 18 13 11 10 dB dB dB dB dB 50% CTRL to 0.05 dB final value (-40 to +85 C) rising edge 50% CTRL to 0.05 dB final value (-40 to +85 C) falling edge 14 15 18 45 s s 50% CTRL to 90% or 10% RF 5 8 s Settling time Switching time (TSW) 0.7 0.8 1.0 1.1 1.2 1.0 1.1 1.3 1.5 1.6 10 Hz-9 kHz 3000 MHz 6000 MHz 7500 MHz 8000 MHz 1 P1dB input 1 dB compression point RFX-RFC All bands @ 1:1 VSWR, 100% duty cycle 31 33 dBm Input IP3 8000 MHz 58 dBm Input IP2 8000 MHz 100 dBm Note 1: Maximum operating PIN (50) is shown in Table 3. Please refer to Figure 4, Figure 5 and Figure 6 when operating the part at low frequency. (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 12 Document No. DOC-32914-3 | UltraCMOS(R) RFIC Solutions PE42540 Product Specification GND VDD GND GND V1 V2 GND VSS_EXT Figure 3. Pin Configuration (Top View) Table 3. Operating Ranges Parameter Min Typ Max Unit Supply voltage, VDD 3.0 3.3 3.55 V Negative power supply voltage1, VSS_EXT -3.6 -3.3 -3.0 V Negative supply current, Iss -10 -40 A Power supply current, IDD VDD = 3.3V, VSS_EXT = 0V, Temp = +85 C 90 160 A 50 A Power supply current, IDD VDD = 3.6V, VSS_EXT used Control voltage high (V1, V2) 1.2 1.5 VDD V Control voltage low (V1, V2) 0 0 0.4 V 1 A Control current, ICTRL GND GND GND RFC GND GND GND GND 2 Table 2. Pin Descriptions Pin # Pin Name 1, 3-6, 8, 9-12, 14-17, 19-22, 24-26, 28, 32 GND 2 RF42 RF I/O 7 2 RF I/O 2 RF common 2 RF I/O 13 18 Description Ground Figures 4, 5, 6 Max power into termination (50) 9 kHz 6 MHz2,3 6 MHz-8 GHz2,3 Figures 4, 5, 6 20 dBm Max power, hot switching (50) 9 kHz 6 MHz2,3 6 MHz-8 GHz2,3 Figures 4, 5, 6 20 dBm Operating temperature range, TOP Notes: RF2 RFC RF1 2 23 RF3 RF I/O 27 VDD Supply 29 V1 Switch control input, CMOS logic level 30 V2 Switch control input, CMOS logic level 31 VSS_EXT1 Paddle GND Notes: PIN thru path (50, RF power in) 9 kHz - 8 GHz -40 +85 C 1. Applies only when external VSS power supply is used. Otherwise, VSS_EXT = 0. 2. 100% duty cycle (-40 to +85 C, 1:1 VSWR). 3. Do not exceed 20 dBm. External VSS negative voltage control Exposed solder pad: Ground for proper operation 1. Use VSS_EXT (pin 31, VSS_EXT = -VDD) to bypass and disable internal negative voltage generator. Connect VSS_EXT (pin 31) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. 2. All RF pins must be DC blocked with an external series capacitor or held at 0 VDC. Document No. DOC-32914-3 | www.psemi.com (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 12 PE42540 Product Specification Switching Frequency Table 4. Absolute Maximum Ratings Parameter Min Maximum junction temperature Max Unit +150 C Storage temperature range, TST -60 +150 C Supply voltage, VDD -0.3 4 V 4 V Control voltage (V1, V2) PIN thru path (50, RF power in) 9 kHz-8 GHz Figures 4, 5, 6 Max power into termination (50) 9 kHz 6 MHz1 6 MHz-8 GHz Figures 4, 5, 6 20 dBm ESD voltage HBM2 RFC All pins 2000 1000 V V ESD voltage CDM3, all pins 450 V 100 V 4 ESD voltage MM , all pins Optional External Vss Notes: 1. Do not exceed 20 dBm. 2. Human body model (MIL-STD 883 Method 3015). 3. Charged device model (JEDEC JESD22-C101). 4. Machine model (JEDEC JESD22-A115-A). Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 12 The PE42540 has a maximum 25 kHz switching rate when the internal negative voltage generator is used (pin 31 = GND). The rate at which the PE42540 can be switched is only limited to the switching time (Table 1) if an external negative supply is provided at (pin 31 = VSS_EXT). For proper operation, the VSS_EXT pin must be grounded or tied to the Vss voltage specified in Table 3. When the VSS_EXT pin is grounded, FETs in the switch are biased with an internal voltage generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied externally to bypass the internal negative voltage generator. Spurious Performance The typical spurious performance of the PE42540 is -144 dBm when VSS_EXT = 0V (pin 31 = GND). If further improvement is desired, the internal negative voltage generator can be disabled by setting VSS_EXT = -VDD. Table 5. Truth Table State V1 V2 RF1 on 0 0 RF2 on 1 0 RF3 on 0 1 RF4 on 1 1 Moisture Sensitivity Level The moisture sensitivity level rating for the PE42540 in the 32-lead 5 x 5 mm LGA package is MSL3. Document No. DOC-32914-3 | UltraCMOS(R) RFIC Solutions PE42540 Product Specification Low Frequency Operation Thermal Data Table 6 shows the minimum and maximum voltage limits when operating the device under various VDD and VSS_EXT voltage conditions below 9 kHz. Refer to Figures 4, 5 and 6 to determine the maximum operating power over the frequency range of the device. Psi-JT (JT), junction top-of-package, is a thermal metric to estimate junction temperature of a device on the customer application PCB (JEDEC JESD51-2). Table 6. Instantaneous RF Voltage Limits for Operation Below 9 kHz where JT = (TJ -TT)/P JT = junction-to-top of package characterization VDD VSS_EXT Minimum Peak Voltage at RF Port Maximum Peak Voltage at RF Port 3.0 0.0 -0.2 1.2 3.0 -3.0 -0.6 1.6 3.3 -3.3 -0.3 1.3 3.5 -3.5 -0.1 1.1 TT = package temperature (top surface, in the center), C 3.6 -3.6 0.0 1.0 P = power dissipated by device, Watts parameter, C/W TJ = die junction temperature, C Maximum Operating Power vs Frequency Figures 4, 5 and 6 show the power limit of the device will increase with frequency. As the frequency increases, the contours and maximum power limit will increase as shown in the curves. Document No. DOC-32914-3 | www.psemi.com Table 7. Thermal Data for PE42540 Parameter Typ Unit JT 79 C/W JA, junction-to-ambient thermal resistance 128 C/W (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 12 PE42540 Product Specification Figure 4. Maximum Operating Power vs Frequency (Tambient = +25 oC) 35 30 Input Power (dBm) 25 20 15 10 5 0 VssEXT = -3 .0V , VDD = +3.0 V -5 VssEXT = 0.0V, VDD +3.0V -10 VssEXT= -3.5V, VDD=+3.5V -15 0 1 10 100 1,000 10,000 100 ,00 0 1,000,000 Frequency (kHz) Figure 5. Maximum Operating Power vs Frequency (Tambient = +50 oC) 35 30 Input Power (dBm) 25 20 15 10 5 0 VssEXT = -3 .0V , VDD = +3.0 V -5 VssEXT = 0.0V, VDD +3.0V -10 VssEXT= -3.5V, VDD=+3.5V -15 0 1 10 100 1,000 10,000 100 ,00 0 1,000,000 Frequency (kHz) Figure 6. Maximum Operating Power vs Frequency (Tambient = +85 oC) 35 30 25 Input Power (dBm) 20 15 10 5 0 VssEXT = -3 .0V , VDD = +3.0 V -5 VssEXT = 0.0V, VDD +3.0V -10 VssEXT= -3.5V, VDD=+3.5V -15 0 1 10 100 1,000 10,000 100 ,00 0 1,000,000 Frequency (kHz) (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 12 Document No. DOC-32914-3 | UltraCMOS(R) RFIC Solutions PE42540 Product Specification Figure 7. Insertion Loss vs VDD (Temp = +25C, VSS_EXT = 0) Frequency (Hz) Figure 9. Insertion Loss (Temp = +25 C, VDD = 3.3V, VSS_EXT = 0) Frequency (Hz) Figure 11. Isolation: RFX-RFX vs Temp (VDD = 3.3V, VSS_EXT = 0) Frequency (Hz) Document No. DOC-32914-3 | www.psemi.com Figure 8. Insertion Loss vs Temp (VDD = 3.3V, VSS_EXT = 0) Frequency (Hz) Figure 10. Isolation: RFX-RFX vs VDD (Temp = +25 C, VSS_EXT = 0) Frequency (Hz) Figure 12. Isolation: RFX-RFC vs VDD (Temp = +25 C, VSS_EXT = 0) Frequency (Hz) (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 12 PE42540 Product Specification Figure 13. Isolation: RFX-RFC vs Temp (VDD = 3.3V, VSS_EXT = 0) Frequency (Hz) Figure 15. Active Port Return Loss vs Temp (VDD = 3.3V, VSS_EXT = 0) Frequency (Hz) Figure 17. Terminated Port Return Loss vs Temp (VDD = 3.3V, VSS_EXT = 0) Frequency (Hz) (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 12 Figure 14. Active Port Return Loss vs VDD (Temp = +25 C, VSS_EXT = 0) Frequency (Hz) Figure 16. Terminated Port Return Loss vs VDD (Temp = +25 C, VSS_EXT = 0) Frequency (Hz) Figure 18. RFC Port Return Loss vs VDD (Temp = +25 C, VSS_EXT = 0) Frequency (Hz) Document No. DOC-32914-3 | UltraCMOS(R) RFIC Solutions PE42540 Product Specification Figure 19. RFC Port Return Loss vs Temp (VDD = 3.3V, VSS_EXT = 0) Frequency (Hz) Figure 20. Linearity Performance (Temp = +25 C, VDD = 3.3V, VSS_EXT = 0) 120 Linearity [dBm] Linearity (dBm) 100 80 60 40 Nominal IIP3 [dBm] Nominal IIP2 [dBm] 20 0 10.0E+3 100.0E+3 1.0E+6 10.0E+6 100.0E+6 1.0E+9 10.0E+ 1.0E+10 Frequency (Hz) Frequency [Hz] Document No. DOC-32914-3 | www.psemi.com (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 12 PE42540 Product Specification Evaluation Kit Figure 21. Evaluation Board Layout The SP4T switch evaluation board was designed to ease customer evaluation of Peregrine's PE42540. The RF common port is connected through a 50 transmission line via the top SMA connector, J1. RF1, RF2, RF3 and RF4 are connected through 50 transmission lines via SMA connectors J2, J4, J3 and J5, respectively. A through 50 transmission is available via SMA connectors J6 and J7. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. PRT-28605 Figure 22. Evaluation Board Schematic R1 1M 0603 1M 0603 R2 J1 142-0761-881 R5 2 R3 1 R4 R6 C3 22 pF 0402 C6 0.1 F 0402 1 3 5 7 9 11 13 2 4 6 8 10 12 14 2 4 6 8 10 12 14 C5 0.1 F 0402 RF4 1 2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND J6 142-0761-881 1 1 J7 142-0761-881 1 3 4 5 6 8 9 10 11 12 14 15 16 17 19 20 21 22 24 25 26 28 32 J5 142-0761-881 2 RF4 7 J4 142-0761-881 2 RF3 1 2 RF2 RF2 2 2 23 RF1 RF3 2 J3 142-0761-881 1 C1 22 pF 0402 J8 PZC36DABN HEADER14 27 29 30 31 RF1 18 C2 22 pF 0402 VDD V1 V2 VSS RFC U1 PE42540 J2 142-0761-881 1 13 C4 22 pF 0402 0 0402 0 0402 0 0402 0 0402 1 3 5 7 9 11 13 DOC-32927 (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 12 Document No. DOC-32914-3 | UltraCMOS(R) RFIC Solutions PE42540 Product Specification Figure 23. Package Drawing 0.10 C 5.00 A (2X) 3.030.05 0.485 (x32) DETAIL A B 17 24 0.50 (x28) 5.00 0.34 (x32) 0.50 (x28) 25 16 3.50 3.030.05 4.90 3.08 0.34 (x32) 0.260.05 (x32) 0.10 C 32 9 8 1 (2X) 3.50 Pin #1 Corner TOP VIEW BOTTOM VIEW 1.01 MAX 0.10 C 0.70 0.05 C SEATING PLANE SIDE VIEW 0.24 0.4350.050 (x32) DETAIL B 3.08 4.90 RECOMMENDED LAND PATTERN DOC-01877 0.10 C A B 0.05 C ALL FEATURES C 0.10 0.15 0.535 0.04 0.424 45 CHAMFER 0.11 0.10 DETAIL A DETAIL B Figure 24. Marking Specifications 42540 YYWW ZZZZZZZ YYWW = Date Code ZZZZZZZ = Assembly lot code (maximum seven characters) DOC-65743 Document No. DOC-32914-3 | www.psemi.com (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 12 PE42540 Product Specification Figure 25. Tape and Reel Drawing Tape Feed Direction Notes: 1. 10 sprocket hole pitch cumulative tolerance 0.02 2. Camber not to exceed 1 mm in 100 mm 3. Material: PS + C 4. Ao and Bo measured as indicated 5. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier 6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole Ao = 5.25 0.05 mm Bo = 5.25 0.05 mm Ko = 1.1 0.05 mm Table 8. Ordering Codes for PE42540 Order Code Description Package Shipping Method PE42540D-Z PE42540 SP4T RF switch Green 32-lead 5 x 5 mm LGA 3000 units/T&R EK42540-05 PE42540 Evaluation kit Evaluation kit 1/Box Sales Contact and Information For sales and contact information please visit www.psemi.com. Advance Inf ormat ion: Th e p ro d u ct i s i n a f o rm a ti ve o r d e si g n st a g e . Th e d at a sh e e t co n t ai n s d e si g n t a rg et sp e cifi ca ti o n s f o r p ro d u ct d e vel o p m e n t . S p e ci fi ca ti o n s a n d f e at u re s m a y ch a n g e i n a n y m a n n e r w it h o u t n oti ce . Prelimina ry S pecif ication: Th e d at a sh e e t co n tai n s p reli m i n a ry d a t a. A d di ti o n al d at a m a y b e a d d e d at a l at e r d at e . P e re g ri n e re se rve s t h e ri g h t t o ch a n g e sp e cifi ca ti o n s a t a n y ti m e w it h o u t n o ti ce i n o rd e r t o su p p l y t h e b e st p o ssi bl e p ro d u ct. P roduct Spec ificat ion: Th e d a t a sh e et co n t ai n s fi n al d at a . I n t h e e ve n t P e re g ri n e d e ci d e s t o ch a n g e t h e sp e ci fi ca ti o n s, P e re g ri n e w ill n o tif y cu st o m e r s o f t h e i nt e n d e d ch a n g e s b y i ssu i n g a C N F (C u st o m e r N o tifi ca ti o n Fo rm ). Th e i n f o rm a ti o n i n t hi s d a t a sh e e t i s b e li e ve d t o b e reli a bl e . H o w e ve r, P e re g ri n e a ssu m e s n o li a bili t y f o r t h e u se of t hi s i n f o rm a ti o n. U se sh a ll b e e nti rel y a t t h e u se r' s o w n ri sk. (c)2010-2017 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 12 N o p at e n t ri g h t s o r li ce n se s t o a n y ci rcui t s d e scri b e d i n t hi s d a t a sh e e t a re i m pli e d o r g ra n t e d t o a n y t hi rd p a rt y. P e re g ri n e' s p ro d u ct s a re n o t d e si g n e d o r i nt e n d e d f o r u se i n d e vi ce s o r sy st e m s i n t e n d e d f o r su rgi ca l i m pl a n t, o r i n o t h e r a p pli ca ti o n s i nt e n d e d t o su p p o rt o r su st ai n li f e, o r i n a n y a p pli ca ti o n i n w h i ch t h e f ail u re of t h e P e re g ri n e p ro d u ct co u l d cre a t e a si t u ati o n i n w hi ch p e rso n a l i nj u ry o r d e at h mi g h t o ccu r. P e re g ri n e a ssu m e s n o lia bilit y f o r d a m a g e s, i n cl u di n g co n se q u e n ti al o r i n ci d e n tal d a m a g e s, a ri si n g o ut o f t h e u se of i t s p ro d u ct s i n su ch a p pli ca ti o n s. Th e P e re g ri n e n a m e , l o g o , Ul t ra C M OS a n d U TS i a re re gi st e re d t ra d e m a rks a n d H a R P , M u l ti S wi t ch a n d D u N E a re t ra d e m a rks o f P e re g ri n e S e m i co n d u ct o r C o rp. P e re g ri n e p ro d u ct s a re p rot e ct e d u n d e r o n e o r m o re of t h e foll o w i n g U . S . P a t e nt s: h tt p :/ / p at e n t s. p se m i. co m . Document No. DOC-32914-3 | UltraCMOS(R) RFIC Solutions