Features * Utilizes the ARM7TDMITM ARM(R) Thumb(R) Processor Core * * * * * * * * * * * * * * * * * * - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE (In-circuit Emulation) 8K Bytes Internal RAM Fully-programmable External Bus Interface (EBI) - 128 M Bytes of Maximum External Address Space - Up to 8 Chip Selects - Software Programmable 8-/16-bit External Databus 8-channel Peripheral Data Controller 8-level Priority, Individually Maskable, Vectored Interrupt Controller - Five External Interrupts, Including a High-priority, Low-latency Interrupt Request 54 Programmable I/O Lines 6-channel 16-bit Timer/Counter - Six External Clock Inputs, Two Multi-purpose I/O Pins per Channel 2 USARTs - Two Dedicated Peripheral Data Controller (PDC) Channels per USART - Support for up to 9-bit Data Transfers 2 Master/Slave SPI Interfaces - Two Dedicated Peripheral Data Controller (PDC) Channels per SPI - 8-bit to 16-bit Programmable Data Length - Four External Slave Chip Selects per SPI 3 System Timers - Period Interval Timer (PIT), Real-time Timer (RTT) and Watchdog Timer (WDT) Power Management Controller (PMC) - Individual Deactivation of CPU and Peripherals Clock Generator with 32.768 kHz Low-power Oscillator and PLL - Support for 38.4 kHz Crystals - Software Programmable System Clock (up to 33 MHz) IEEE 1149.1 JTAG Boundary-scan on All Active Pins Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at VDDCORE = 3.0 V, 85C 2.7V to 3.6V Core Operating Range 2.7V to 5.5V I/O Operating Range 2.7V to 3.6V Oscillator and PLL Operating Range -40C to +85C Temperature Range Available in a 144-lead TQFP or 144-ball BGA Package AT91 ARM(R) Thumb(R) Microcontroller s AT91M42800A Electrical Characteristics Description The AT91M42800A is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very lowpower consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91M42800A has a direct connection to off-chip memory, including Flash, through the External Bus Interface. The Power Management Controller allows the user to adjust the device activity according to system requirements, and, with the 32.768 kHz low-power oscillator, enables the AT91M42800A to reduce power requirements to an absolute minimum. The AT91M42800A is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip RAM and a wide range of peripheral functions, including timers, serial communication controllers and a versatile clock generator on a monolithic chip, the Atmel AT91M42800A provides a highly-flexible and cost-effective solution to many compute-intensive applications. Rev. 1776A-01/02 1 Absolute Maximum Ratings* Operating Temperature (Industrial).........-40C to + 85C *NOTICE: Storage Temperature............................-60C to + 150C Voltage on Input Pin with Respect to Ground....................................-0.3V to +5.5V Maximum Operating Voltage (VDDCORE and VDDPLL)................................................3.6V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage (VDDIO)........................5.5V DC Output Current (VDDIO).......................................6 mA DC Characteristics The following characteristics are applicable over the Operating Temperature range: TA = -40C to +85C, unless otherwise specified and are certified for a Junction Temperature up to TJ = 100C. Table 1. DC Characteristics Symbol Parameter VDDCORE DC Supply Core VDDPLL Max Units 2.7 3.6 V DC Supply Oscillator and PLL VDDCORE 3.6 V VDDIO DC Supply Digital I/Os VDDCORE VDDCORE + 2.0 or 5.5 V VIL Input Low-level Voltage -0.3 0.8 V VIH Input High-level Voltage VOL Output Low-level Voltage Conditions Min 2 Output High-level Voltage ILEAK Input Leakage Current VDD + 0.3 IOL = 8 mA(2) IOL = 0 mA(2) (2) VOH Typ IOH = 8 mA IOH = 0 mA V 0.2 V (1) V (1) V VDD - 0.2 (1) V 0.4 VDD - 0.4 (2) (1) 4 A IPULL Input Pull-up Current VDD = 3.6V , VIN = 0 280 A CIN Input Capacitance 144-TQFP Package 8 pF (1) VDD = VDDCORE = 3.6V, MCK = 0 Hz ISC Notes: 2 TA = 25C Static Current All inputs driven TMS, TDI, TCK, NRST = 1 TA = 85C 20 400 A 1. VDD is applicable to VDDIO and VDDPLL. 2. IO = Output Current. AT91M42800A 1776A-01/02 AT91M42800A Power Consumption The values in the following tables are measured values in the operating conditions indicated (i.e., VDDIO = 3.3V, VDDCORE = 3.3V, TA = 25C) on the AT91EB42 Evaluation Board. They represent the power consumption on the VDDCORE power supply, unless otherwise specified. Table 2. Power Consumption Mode Conditions Consumption Fetch in ARM mode out of internal SRAM All peripheral clocks activated 6.47 Fetch in ARM mode out of internal SRAM All peripheral clocks deactivated 4.51 All peripheral clocks activated 3.74 All peripheral clocks deactivated 1.67 Unit Normal mW/MHz Idle Table 3. Power Consumption per Peripheral Peripheral Consumption PIO Controller 0.77 Timer/Counter Channel 0.12 Timer/Counter Block (3 Channels) 0.33 USART 0.36 SPI 0.42 PLLA(1) FOUT = 3 MHz 0.812 PLLA(1) FOUT = 8 MHz 1.33 (1) FOUT = 16 MHz 2.1 (1) PLLA FOUT = 20 MHz 2.2 PLLB(2) FOUT = 20 MHz 1.31 PLLB(2) FOUT = 32.7 MHz 1.81 PLLA Notes: Unit mW/MHz mW 1. Power consumption on the VDDPLL power supply. FOSC = 32.768 kHz and the loop filter values are R = 1.5 k,=C1 = 100 nF, C2 = 10 nF 2. Power consumption on the VDDPLL power supply. FOSC = 32.768 kHz and the loop filter values are R = 680,=C1 = 1F, C2 = 100 nF 3 1776A-01/02 Thermal and Reliability Considerations Thermal Data In Table 4, the device lifetime is estimated with the MIL-217 standard in the "moderately controlled" environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section "Junction Temperature" on page 5.) Note that the user must be extremely cautious with this MTBF calculation: as the MIL-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 4. MTBF Versus Junction Temperature Junction Temperature (TJ) (C) Estimated Lifetime (MTBF) (Year) 100 31 125 17 150 10 175 6 Table 5 summarizes the thermal resistance data related to the package of interest. Table 5. Thermal Resistance Data Symbol Parameter JA= Junction-to-ambient thermal resistance Condition Package Typ Unit TQFP144 37 PBGA144 57 TQFP144 10.9 PBGA144 19.9 Still Air C/W JC Reliability Data Junction-to-case thermal resistance The number of gates and the device die size are provided for the user to calculate reliability data with another standard and/or in another environmental model. Table 6. Reliability Data 4 Parameter Data Unit Number of Logic Gates 516 K gates Number of Memory Gates 400 K gates Device Die Size 22.9 mm2 AT91M42800A 1776A-01/02 AT91M42800A Junction Temperature The average chip-junction temperature TJ in C can be obtained from the following: 1. T J = T A + ( P D x JA ) 2. T J = T A + ( P D x ( HEATSINK + JC ) ) Where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 5 on page 4. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 5 on page 4. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section "Power Consumption" on page 3. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C. 5 1776A-01/02 Conditions Timing Results The delays are given as typical values in the following conditions: * VDDIO = VDDCORE = 3.3V * Ambient Temperature = 25C * Load Capacitance = 0 pF * The output level change detection is 0.5 x VDDIO * The input level is 0.3 x VDDIO for a low-level detection and is 0.7 x VDDIO for a high level detection. The minimum and maximum values given in the AC characteristics tables of this datasheet take into account the process variation and the design. In order to obtain the timing for other conditions, the following equation should be used: t = T x ( ( VDDCORE x t DATASHEET ) + ( VDDIO x ( C SIGNAL x CSIGNAL ) ) ) Where: * * * * * * T is the derating factor in temperature given in Figure 1. VDDCORE is the derating factor for the Core Power Supply given in Figure 2. tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. VDDIO is the derating factor for the IO Power Supply given in Figure 3. CSIGNAL is the capacitance load on the considered output pin.(1) CSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max values in this datasheet. The input delays are given as typical values. Note: Temperature Derating Factor 1. The user must take into account the package capacitance load contribution (CIN) described in Table 1 on page 2. Figure 1. Derating Curve for Different Operating Temperatures 1.3 Derating Factor 1.2 1.1 1 Derating Factor for Typ Case is 1 0.9 0.8 -60 -40 -20 0 20 40 60 80 100 120 140 160 Operating Temperature (C) 6 AT91M42800A 1776A-01/02 AT91M42800A Core Voltage Derating Factor Figure 2. Derating Curve for Different Core Supply Voltages 3 Derating Factor 2.5 Derating Factor for Typ Case is 1 2 1.5 1 0.5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Core Supply Voltage (V) IO Voltage Derating Factor Figure 3. Derating Curve for Different VDDIO Power Supply Levels 1.15 Derating Factor for Typ Case is 1 Derating Factor 1.05 0.95 0.85 0.75 0.65 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 VDDIO Voltage Level (V) 7 1776A-01/02 Crystal Oscillator Characteristics Table 7. Oscillator Characteristics Symbol Parameter 1/(tCPOSC) Crystal Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) CL Equivalent Load Capacitance CL1 = CL2 = 20 pF Duty Cycle Measured at the MCKO output pin Startup Time VDDBU = 2.7V; without any capacitor connected to the oscillator pins (XIN and XOUT) tST Conditions Min 45 Typ Max Unit 32.768 kHz 20 pF 10 pF 50 55 % 1.5 s Clock Waveforms Table 8. Master Clock Waveform Parameters Symbol Parameter 1/(tCPMCK) Master Clock Frequency tCPMCK Master Clock Period tCHMCK Master Clock High Half-period 0.45 x tCPMCK 0.55 x tCPMCK ns tCLMCK Master Clock Low Half-period 0.45 x tCPMCK 0.55 x tCPMCK ns 8 Conditions Min Max Units 38.1 MHz 26.2 ns AT91M42800A 1776A-01/02 AT91M42800A Table 9. Clock Propagation Times Symbol Parameter tCDEH(1) MCK Edge to MCKO Rising Edge tCDEL(1) MCK Edge to MCKO Falling Edge Note: Conditions Min Max Units CMCKO = 0 pF 7.8 12.3 ns 0.024 0.037 ns/pF 8.2 12.8 ns 0.027 0.042 ns/pF CMCKO derating CMCKO = 0 pF CMCKO derating 1. Applicable only when MCKO outputs Master Clock or inverted Master Clock. Figure 4. Clock Waveform MCK tCHMCK tCLMCK tCPMCK 0.5 VDDIO MCKO 0.5 VDDIO tCDEL tCDEH PMC Characteristics Table 10. Master Clock Source Switch Times MCK Source Switch Time From To Min Typ Oscillator Output PLL Output 3 x tCPSLCK + 2.5 x tCPPLL PLL Output Oscillator Output 3.5 x tCPSLCK + 2.5 x tCPPLL Max 9 1776A-01/02 AC Characteristics EBI Signals Relative to MCK The following tables show timings relative to operating condition limits defined in the section "Timing Results" on page 6. Table 11. General-purpose EBI Signals Symbol Parameter EBI1 MCK Falling to NUB Valid EBI2 MCK Falling to NLB/A0 Valid EBI3 MCK Falling to A1 - A23 Valid EBI4 MCK Falling to Chip Select Change EBI5 NWAIT Setup before MCK Rising 2.1 ns EBI6 NWAIT Hold after MCK Rising 5.2 ns 10 Conditions Min Max Units CNUB = 0 pF 8.3 18.8 ns 0.022 0.045 ns/pF 7 14.8 ns 0.022 0.045 ns/pF 6.7 15.8 ns 0.022 0.045 ns/pF 7.6 17.6 ns 0.022 0.045 ns/pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating AT91M42800A 1776A-01/02 AT91M42800A Table 12. EBI Write Signals Symbol Parameter EBI7 MCK Rising to NWR Active (No Wait States) EBI8 MCK Rising to NWR Active (Wait States) EBI9 MCK Falling to NWR Inactive (No Wait States) EBI10 MCK Rising to NWR Inactive (Wait States) EBI11 MCK Rising to D0 - D15 Out Valid EBI12 NWR High to NUB Change EBI13 NWR High to NLB/A0 Change EBI14 NWR High to A1 - A23 Change EBI15 NWR High to Chip Select Inactive Conditions Min Max Units CNWR = 0 pF 8.2 13.6 ns 0.029 0.045 ns/pF 8.5 14.1 ns 0.029 0.045 ns/pF 8.1 13.4 ns 0.022 0.035 ns/pF 8.3 13.9 ns 0.022 0.035 ns/pF 6.8 13.4 ns 0 0.045 ns/pF 5.3 11.3 ns 0.022 0.045 ns/pF 4.5 7.6 ns 0.022 0.045 ns/pF 4.2 9.7 ns 0.022 0.045 ns/pF 4.9 11.4 ns 0.022 0.035 ns/pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CDATA = 0 pF CDATA derating CNUB = 0 pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating C = 0 pF Data Out Valid before NWR High (No Wait States) EBI16 (1) tCHMCK - 0.7 ns CDATA derating -0.045 ns/pF CNWR derating 0.035 ns/pF n x tCPMCK - 0.3(2) ns CDATA derating -0.045 ns/pF CNWR derating 0.035 ns/pF 3 ns tCHMCK - 0.9 ns C = 0 pF Data Out Valid before NWR High (Wait States)(1) EBI17 EBI18 Data Out Valid after NWR High EBI19 NWR Minimum Pulse Width (No Wait States)(1) CNWR derating NWR Minimum Pulse Width (Wait States)(1) EBI20 Notes: CNWR = 0 pF CNWR = 0 pF CNWR derating -0.01 ns/pF (2) n x tCPMCK - 1.0 -0.01 ns ns/pF 1. The derating should not be applied to tCHMCK or tCPMCK. 2. n = number of standard wait states inserted. 11 1776A-01/02 Table 13. EBI Read Signals Symbol Parameter EBI21 MCK Falling to NRD Active(1) EBI22 MCK Rising to NRD Active(2) EBI23 MCK Falling to NRD Inactive(1) EBI24 MCK Falling to NRD Inactive(2) Conditions Min Max Units CNRD = 0 pF 8.1 14.3 ns 0.029 0.045 ns/pF 7.8 13.5 ns 0.029 0.045 ns/pF 7.9 13.9 ns 0.022 0.035 ns/pF 7.8 12.3 ns 0.022 0.035 ns/pF CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating (5) EBI25 D0 - D15 In Setup before MCK Falling Edge -2.1 ns EBI26 D0 - D15 In Hold after MCK Falling Edge(5) 6.2 ns EBI27 NRD High to NUB Change EBI28 NRD High to NLB/A0 Change EBI29 NRD High to A1 - A23 Change EBI30 NRD High to Chip Select Inactive EBI31 Data Setup before NRD High(5) EBI32 Data Hold after NRD High(5) EBI33 NRD Minimum Pulse Width(1)(3) EBI34 (2)(3) CNUB = 0 pF 6.4 12.7 ns 0.022 0.045 ns/pF 5.4 8.8 ns 0.022 0.045 ns/pF 5.1 11 ns 0.022 0.045 ns/pF 5.8 12.6 ns CNCS derating 0.022 0.035 ns/pF CNRD = 0 pF 10.7 ns CNRD derating 0.035 ns/pF -3.9 ns -0.022 ns/pF (n + 1) tCPMCK - 1.8(4) ns -0.01 ns/pF n x tCPMCK + (tCHMCK - 1.2)(4) ns -0.01 ns/pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF NRD Minimum Pulse Width CNRD derating Notes: 12 1. 2. 3. 4. 5. Early Read Protocol. Standard Read Protocol. The derating should not be applied to tCHMCK or tCPMCK. n = number of standard wait states inserted. Only one of these two timings needs to be met. AT91M42800A 1776A-01/02 AT91M42800A Table 14. EBI Read and Write Control Signals. Capacitance Limitation Symbol Parameter TCPLNRD(1) Master Clock Low Due to NRD Capacitance TCPLNWR(2) Master CLock Low Due to NWR Capacitance Notes: Conditions Min Max Units CNRD = 0 pF 13.8 ns CNRD derating 0.035 ns/pF CNWR = 0 pF 11.8 ns CNWR derating 0.035 ns/pF 1. If this condition is not met, the action depends on the read protocol intended for use. * Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle. * Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state. 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. 13 1776A-01/02 Figure 5. EBI Signals Relative to MCK MCK EBI4 EBI4 NCS CS EBI3 A1 - A23 EBI5 EBI6 NWAIT EBI1/EBI2 NUB/NLB/A0 EBI21 EBI23 EBI27 - 30 EBI33 NRD(1) EBI24 EBI22 EBI34 (2) NRD EBI31 EBI32 EBI25 EBI26 D0 - D15 Read EBI9 EBI7 EBI12 - 15 EBI19 NWR (No Wait States) EBI8 EBI10 EBI20 NWR (Wait States) EBI17 EBI11 EBI16 EBI18 EBI18 D0 - D15 to Write No Wait Notes: 14 Wait 1. Early Read Protocol. 2. Standard Read Protocol. AT91M42800A 1776A-01/02 AT91M42800A Peripheral Signals USART Signals The inputs must meet the minimum pulse width and period constraints shown in Table 15 and Table 16, and represented in Figure 6. Table 15. USART Input Minimum Pulse Width Symbol Parameter US1 SCK/RXD Minimum Pulse Width Min Pulse Width Units 5(tCPMCK/2) ns Table 16. USART Minimum Input Period Symbol Parameter Min Input Period US2 SCK Minimum Input Period 9(tCPMCK/2) Units ns Figure 6. USART Signals US1 RXD US2 US1 SCK 15 1776A-01/02 SPI Signals The inputs must meet the minimum pulse width and period constraints shown in Table 17 and Table 18, and represented in Figure 7. Table 17. SPI Input Minimum Pulse Width Symbol Parameter SPI1 SPK/MISO/MOSI/NSS Minimum Pulse Width Min Pulse Width Units 3(tCPMCK/2) ns Min Input Period Units 5(tCPMCK/2) ns Table 18. SPI Minimum Input Period Symbol Parameter SPI2 SPCK Minimum Input Period Figure 7. SPI Signals SPI1 SPCK/ MISO/ MOSI/ NSS SPI2 SPI1 SPCK 16 AT91M42800A 1776A-01/02 AT91M42800A Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCPMCK) in Waveform Event Detection mode and 4(tCPMCK) in Waveform Total-count Detection mode. The inputs must meet the minimum pulse width and minimum input period shown in Table 19 and Table 20, and as represented in Figure 8. Table 19. Timer Input Minimum Pulse Width Symbol Parameter TC1 TCLK/TIOA/TIOB Minimum Pulse Width Min Pulse Width Units 3(tCPMCK/2) ns Min Input Period Units 5(tCPMCK/2) ns Table 20. Timer Input Minimum Period Symbol Parameter TC2 TCLK/TIOA/TIOB Minimum Input Period Figure 8. Timer Input TC2 3(tCPMCK/2) 3(tCPMCK/2) MCK TC1 TIOA/ TIOB/ TCLK Reset Signals A minimum pulse width is necessary, as shown in Table 21 and as represented in Figure 9. Table 21. Reset Minimum Pulse Width Symbol Parameter RST1 NRST Minimum Pulse Width Min Pulse Width Units 310 s Figure 9. Reset Signal RST1 NRST Only the NRST rising edge is synchronized with MCK. The falling edge is asynchronous. 17 1776A-01/02 Advanced Interrupt Controller Signals Inputs must meet the minimum pulse width and minimum input period shown in Table 22 and Table 23, and represented in Figure 10. Table 22. AIC Input Minimum Pulse Width Symbol Parameter AIC1 FIQ/IRQ[6:0] Minimum Pulse Width Min Pulse Width Units 3(tCPMCK/2) ns Min Input Period Units 5(tCPMCK/2) ns Table 23. AIC Input Minimum Period Symbol Parameter AIC2 AIC Minimum Input Period Figure 10. AIC Signals AIC2 MCK AIC1 FIQ/IRQ2 [6:0] Input Parallel I/O Signals The inputs must meet the minimum pulse width shown in Table 24 and represented in Figure 11. Table 24. PIO Input Minimum Pulse Width Symbol Parameter PIO1 PIO Input Minimum Pulse Width Min Pulse Width Units 3(tCPMCK/2) ns Figure 11. PIO Signal PIO1 PIO Inputs 18 AT91M42800A 1776A-01/02 AT91M42800A ICE Interface Signals Table 25. ICE Interface Timing Specifications Symbol Parameter Conditions Min ICE0 NTRST Minimum Pulse Width 19.2 ns ICE1 NTRST High Recovery to TCK High 0.7 ns ICE2 NTRST High Removal from TCK High 0.2 ns ICE3 TCK Low Half-period 42.4 ns ICE4 TCK High Half-period 40.1 ns ICE5 TCK Period 82.5 ns ICE6 TDI, TMS Setup before TCK High 1.0 ns ICE7 TDI, TMS Hold after TCK High 0.8 ns 7.2 ns 0 ns/pF CTDO = 0 pF ICE8 ICE9 TDO Hold Time CTDO derating TCK Low to TDO Valid Max Units CTDO = 0 pF 15.1 ns CTDO derating 0.042 ns/pF Figure 12. ICE Interface Signal ICE0 NTRST ICE1 ICE2 ICE5 TCK ICE3 ICE4 TMS/TDI ICE6 ICE7 TDO ICE8 ICE9 19 1776A-01/02 JTAG Interface Signals Table 26. JTAG Interface Timing Specifications 20 Symbol Parameter Conditions JTAG0 NTRST Minimum Pulse Width 19.2 ns JTAG1 NTRST High Recovery to TCK Toggle 0.8 ns JTAG2 NTRST High Removal from TCK Toggle 1.6 ns JTAG3 TCK Low Half-period 2.5 ns JTAG4 TCK High Half-period 3.1 ns JTAG5 TCK Period 5.6 ns JTAG6 TDI, TMS Setup before TCK High 1.7 ns JTAG7 TDI, TMS Hold after TCK High 2.5 ns 3.3 ns JTAG8 TDO Hold Time 0 ns/pF JTAG9 TCK Low to TDO Valid JTAG10 Device Inputs Setup Time -1.0 ns JTAG11 Device Inputs Hold Time 3.0 ns 4.7 ns JTAG12 Device Outputs Hold Time 0 ns/pF JTAG13 TCK to Device Outputs Valid CTDO = 0 pF CTDO derating Min CTDO = 0 pF CTDO derating COUT = 0 pF COUT derating Max Units 7.2 ns 0.042 ns/pF COUT = 0 pF 11.9 ns COUT derating 0.037 ns/pF AT91M42800A 1776A-01/02 AT91M42800A Figure 13. JTAG Interface Signal JTAG0 NTRST JTAG1 JTAG2 JTAG5 TCK JTAG3 JTAG4 TMS/TDI JTAG6 JTAG7 JTAG10 JTAG11 TDO JTAG8 JTAG9 Device Inputs Device Outputs JTAG12 JTAG13 21 1776A-01/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 e-mail literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. ARM (R), Thumb (R) and ARM Powered (R) are registered trademarks of ARM Limited; ARM7TDMI TM is the trademark of ARM Limited. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1776A-01/02/0M