AT91 ARM Thumb Microcontrollers - Atmel Corporation

Features

•Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– Embedded ICE (In-circuit Emulation)

•8K Bytes Internal RAM

•Fully-programmable External Bus Interface (EBI)

– 128 M Bytes of Maximum External Address Space

– Up to 8 Chip Selects

– Software Programmable 8-/16-bit External Databus

•8-channel Peripheral Data Controller

•8-level Priority, Individually Maskable, Vectored Interrupt Controller

– Five External Interrupts, Including a High-priority, Low-latency Interrupt Request

•54 Programmable I/O Lines

•6-channel 16-bit Timer/Counter

– Six External Clock Inputs, Two Multi-purpose I/O Pins per Channel

•2 USARTs

– Two Dedicated Peripheral Data Controller (PDC) Channels per USART

– Support for up to 9-bit Data Transfers

•2 Master/Slave SPI Interfaces

– Two Dedicated Peripheral Data Controller (PDC) Channels per SPI

– 8-bit to 16-bit Programmable Data Length

– Four External Slave Chip Selects per SPI

•3 System Timers

– Period Interval Timer (PIT), Real-time Timer (RTT) and Watchdog Timer (WDT)

•Power Management Controller (PMC)

– Individual Deactivation of CPU and Peripherals

•Clock Generator with 32.768 kHz Low-power Oscillator and PLL

– Support for 38.4 kHz Crystals

– Software Programmable System Clock (up to 33 MHz)

•IEEE 1149.1 JTAG Boundary-scan on All Active Pins

•

Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at V

DDCORE

= 3.0 V,

85°C

•2.7V to 3.6V Core Operating Range

•2.7V to 5.5V I/O Operating Range

•2.7V to 3.6V Oscillator and PLL Operating Range

•-40°C to +85°C Temperature Range

•Available in a 144-lead TQFP or 144-ball BGA Package

Description

The AT91M42800A is a member of the Atmel AT91 16-/32-bit microcontroller family,

which is based on the ARM7TDMI processor core. This processor has a high-perform-

ance 32-bit RISC architecture with a high-density 16-bit instruction set and very low-

power consumption. In addition, a large number of internally banked registers result in

very fast exception handling, making the device ideal for real-time control applica-

tions. The AT91M42800A has a direct connection to off-chip memory, including Flash,

through the External Bus Interface.

The Power Management Controller allows the user to adjust the device activity

according to system requirements, and, with the 32.768 kHz low-power oscillator,

enables the AT91M42800A to reduce power requirements to an absolute minimum.

The AT91M42800A is manufactured using Atmel’s high-density CMOS technology. By

combining the ARM7TDMI processor core with an on-chip RAM and a wide range of

peripheral functions, including timers, serial communication controllers and a versatile

clock generator on a monolithic chip, the Atmel AT91M42800A provides a highly-flexi-

ble and cost-effective solution to many compute-intensive applications.

AT91

ARM® Thumb®

Microcontroller

AT91M42800A

Electrical

Characteristics

Rev. 1776A–01/02

2AT91M42800A

1776A–01/02

Absolute Maximum Ratings*

DC Characteristics

The following characteristics are applicable over the Operating Temperature range: TA = -40°C to +85°C, unless otherwise

specified and are certified for a Junction Temperature up to TJ = 100°C.

Notes: 1. VDD is applicable to VDDIO and VDDPLL.

2. IO = Output Current.

Operating Temperature (Industrial).........-40°C to + 85°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to

the device. This is a stress rating only and func-

tional operation of the device at these or other con-

ditions beyond those indicated in the operational

sections of this specification is not implied. Expo-

sure to absolute maximum rating conditions for

extended periods may affect device reliability.

Storage Temperature............................-60°C to + 150°C

Voltage on Input Pin with

Respect to Ground....................................-0.3V to +5.5V

Maximum Operating Voltage

(VDDCORE and VDDPLL)................................................3.6V

Maximum Operating Voltage (VDDIO)........................5.5V

DC Output Current (VDDIO).......................................6 mA

Table 1. DC Characteristics

Symbol Parameter Conditions Min Typ Max Units

VDDCORE DC Supply Core 2.7 3.6 V

VDDPLL

DC Supply Oscillator and

PLL VDDCORE 3.6 V

VDDIO DC Supply Digital I/Os VDDCORE

VDDCORE + 2.0

or 5.5 V

VIL Input Low-level Voltage -0.3 0.8 V

VIH Input High-level Voltage 2 VDD + 0.3(1) V

VOL Output Low-level Voltage IOL = 8 mA(2) 0.4 V

IOL = 0 mA(2) 0.2 V

VOH Output High-level Voltage IOH = 8 mA(2) VDD - 0.4(1) V

IOH = 0 mA(2) VDD - 0.2(1) V

ILEAK Input Leakage Current 4µA

IPULL Input Pull-up Current VDD = 3.6V(1), VIN = 0 280 µA

CIN Input Capacitance 144-TQFP Package 8 pF

ISC Static Current

VDD(1) = VDDCORE = 3.6V,

MCK = 0 Hz TA = 25°C 20

µA

All inputs driven TMS,

TDI, TCK, NRST = 1 TA = 85°C 400

AT91M42800A

1776A–01/02

Power

Consumption

The values in the following tables are measured values in the operating conditions indicated

(i.e., VDDIO = 3.3V, VDDCORE = 3.3V, TA = 25°C) on the AT91EB42 Evaluation Board. They rep-

resent the power consumption on the VDDCORE power supply, unless otherwise specified.

Notes: 1. Power consumption on the VDDPLL power supply.

FOSC = 32.768 kHz and the loop filter values are

R = 1.5 kΩ,=C1 = 100 nF, C2 = 10 nF

2. Power consumption on the VDDPLL power supply.

FOSC = 32.768 kHz and the loop filter values are

R = 680Ω,=C1 = 1µF, C2 = 100 nF

Table 2. Power Consumption

Mode Conditions Consumption Unit

Normal

Fetch in ARM mode out of internal SRAM

All peripheral clocks activated

6.47

mW/MHz

Fetch in ARM mode out of internal SRAM

All peripheral clocks deactivated

4.51

Idle All peripheral clocks activated 3.74

All peripheral clocks deactivated 1.67

Table 3. Power Consumption per Peripheral

Peripheral Consumption Unit

PIO Controller 0.77

mW/MHz

Timer/Counter Channel 0.12

Timer/Counter Block (3 Channels) 0.33

USART 0.36

SPI 0.42

PLLA(1) FOUT = 3 MHz 0.812

PLLA(1) FOUT = 8 MHz 1.33

PLLA(1) FOUT = 16 MHz 2.1

PLLA(1) FOUT = 20 MHz 2.2

PLLB(2) FOUT = 20 MHz 1.31

PLLB(2) FOUT = 32.7 MHz 1.81

4AT91M42800A

1776A–01/02

Thermal and

Reliability

Considerations

Thermal Data In Table 4, the device lifetime is estimated with the MIL-217 standard in the “moderately con-

trolled” environmental model (this model is described as corresponding to an installation in a

permanent rack with adequate cooling air), depending on the device Junction Temperature.

(For details see the section “Junction Temperature” on page 5.)

Note that the user must be extremely cautious with this MTBF calculation: as the MIL-217

model is pessimistic with respect to observed values due to the way the data/models are

obtained (test under severe conditions). The life test results that have been measured are

always better than the predicted ones.

Table 5 summarizes the thermal resistance data related to the package of interest.

Reliability Data The number of gates and the device die size are provided for the user to calculate reliability

data with another standard and/or in another environmental model.

Table 4. MTBF Versus Junction Temperature

Junction Temperature (TJ) (C°) Estimated Lifetime (MTBF) (Year)

100 31

125 17

150 10

175 6

Table 5. Thermal Resistance Data

Symbol Parameter Condition Package Typ Unit

θJA=Junction-to-ambient thermal resistance Still Air TQFP144 37

°C/W

PBGA144 57

θJC Junction-to-case thermal resistance TQFP144 10.9

PBGA144 19.9

Table 6. Reliability Data

Parameter Data Unit

Number of Logic Gates 516 K gates

Number of Memory Gates 400 K gates

Device Die Size 22.9 mm2

AT91M42800A

1776A–01/02

Junction

Temperature

The average chip-junction temperature TJ in °C can be obtained from the following:

Where:

•θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 5 on

page 4.

•θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in

Table 5 on page 4.

•θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.

•P

D = device power consumption (W) estimated from data provided in the section “Power

Consumption” on page 3.

•T

A = ambient temperature (°C).

From the first equation, the user can derive the estimated lifetime of the chip and thereby

decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the

second equation should be used to compute the resulting average chip-junction temperature

TJ in °C.

TJTAPDθJA

×()+=

TJTAP(Dθ( HEATSINK

×θ

JC ))++=

6AT91M42800A

1776A–01/02

Conditions

Timing Results The delays are given as typical values in the following conditions:

•VDDIO = VDDCORE = 3.3V

• Ambient Temperature = 25°C

• Load Capacitance = 0 pF

• The output level change detection is 0.5 x VDDIO

• The input level is 0.3 x VDDIO for a low-level detection and is 0.7 x VDDIO for a high level

detection.

The minimum and maximum values given in the AC characteristics tables of this datasheet

take into account the process variation and the design.

In order to obtain the timing for other conditions, the following equation should be used:

Where:

•

T° is the derating factor in temperature given in Figure 1.

•

VDDCORE is the derating factor for the Core Power Supply given in Figure 2.

•tDATASHEET is the minimum or maximum timing value given in this datasheet for a load

capacitance of 0 pF.

•

VDDIO is the derating factor for the IO Power Supply given in Figure 3.

•CSIGNAL is the capacitance load on the considered output pin.(1)

•

CSIGNAL is the load derating factor depending on the capacitance load on the related

output pins given in Min and Max values in this datasheet.

The input delays are given as typical values.

Note: 1. The user must take into account the package capacitance load contribution (CIN) described

in Table 1 on page 2.

Temperature

Derating Factor

Figure 1. Derating Curve for Different Operating Temperatures

tδT°δVDDCORE tDATASHEET

×()δ

VDDIO CSIGNAL δCSIGNAL

×()×()+()×=

Derating Factor for

Typ Case is 1

1.3

1.2

1.1

0.9

0.8

-60 -40 -20 0 20 40 60 80 100 120 140 160

Operating Temperature (˚C)

Derating Factor

AT91M42800A

1776A–01/02

Core Voltage

Derating Factor

Figure 2. Derating Curve for Different Core Supply Voltages

IO Voltage

Derating Factor

Figure 3. Derating Curve for Different VDDIO Power Supply Levels

Derating Factor for

Typ Case is 1

Core Supply Voltage (V)

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

Derating Factor

0.5

1.5

2.5

0.65

0.75

0.85

0.95

1.05

1.15

3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6

VDDIO Voltage Level (V)

Derating Factor

Derating Factor for

Typ Case is 1

8AT91M42800A

1776A–01/02

Crystal Oscillator Characteristics

Clock Waveforms

Table 7. Oscillator Characteristics

Symbol Parameter Conditions Min Typ Max Unit

1/(tCPOSC) Crystal Oscillator Frequency 32.768 kHz

CL1, CL2

Internal Load Capacitance

(CL1 = CL2)20 pF

CLEquivalent Load Capacitance CL1 = CL2 = 20 pF 10 pF

Duty Cycle Measured at the MCKO output pin 45 50 55 %

tST Startup Time

VDDBU = 2.7V;

without any capacitor connected to the

oscillator pins (XIN and XOUT)

1.5 s

Table 8. Master Clock Waveform Parameters

Symbol Parameter Conditions Min Max Units

1/(tCPMCK) Master Clock Frequency 38.1 MHz

tCPMCK Master Clock Period 26.2 ns

tCHMCK Master Clock High Half-period 0.45 x tCPMCK 0.55 x tCPMCK ns

tCLMCK Master Clock Low Half-period 0.45 x tCPMCK 0.55 x tCPMCK ns

AT91M42800A

1776A–01/02

Note: 1. Applicable only when MCKO outputs Master Clock or inverted Master Clock.

Figure 4. Clock Waveform

PMC Characteristics

Table 9. Clock Propagation Times

Symbol Parameter Conditions Min Max Units

tCDEH(1) MCK Edge to MCKO Rising Edge CMCKO = 0 pF 7.8 12.3 ns

CMCKO derating 0.024 0.037 ns/pF

tCDEL(1) MCK Edge to MCKO Falling Edge CMCKO = 0 pF 8.2 12.8 ns

CMCKO derating 0.027 0.042 ns/pF

Table 10. Master Clock Source Switch Times

MCK Source Switch Time

From To Min Typ Max

Oscillator Output PLL Output 3 x tCPSLCK + 2.5 x tCPPLL

PLL Output Oscillator Output 3.5 x tCPSLCK + 2.5 x tCPPLL

MCKO

MCK

tCHMCK

tCLMCK

tCPMCK

0.5 VDDIO

tCDEH tCDEL

0.5 VDDIO

10 AT91M42800A

1776A–01/02

AC Characteristics

EBI Signals Relative to MCK

The following tables show timings relative to operating condition limits defined in the section “Timing Results” on page 6.

Table 11. General-purpose EBI Signals

Symbol Parameter Conditions Min Max Units

EBI1MCK Falling to NUB Valid CNUB = 0 pF 8.3 18.8 ns

CNUB derating 0.022 0.045 ns/pF

EBI2MCK Falling to NLB/A0 Valid CNLB = 0 pF 7 14.8 ns

CNLB derating 0.022 0.045 ns/pF

EBI3MCK Falling to A1 - A23 Valid CADD = 0 pF 6.7 15.8 ns

CADD derating 0.022 0.045 ns/pF

EBI4MCK Falling to Chip Select Change CNCS = 0 pF 7.6 17.6 ns

CNCS derating 0.022 0.045 ns/pF

EBI5NWAIT Setup before MCK Rising 2.1 ns

EBI6NWAIT Hold after MCK Rising 5.2 ns

AT91M42800A

1776A–01/02

Notes: 1. The derating should not be applied to tCHMCK or tCPMCK.

2. n = number of standard wait states inserted.

Table 12. EBI Write Signals

Symbol Parameter Conditions Min Max Units

EBI7MCK Rising to NWR Active (No Wait States) CNWR = 0 pF 8.2 13.6 ns

CNWR derating 0.029 0.045 ns/pF

EBI8MCK Rising to NWR Active (Wait States) CNWR = 0 pF 8.5 14.1 ns

CNWR derating 0.029 0.045 ns/pF

EBI9MCK Falling to NWR Inactive (No Wait States) CNWR = 0 pF 8.1 13.4 ns

CNWR derating 0.022 0.035 ns/pF

EBI10 MCK Rising to NWR Inactive (Wait States) CNWR = 0 pF 8.3 13.9 ns

CNWR derating 0.022 0.035 ns/pF

EBI11 MCK Rising to D0 - D15 Out Valid CDATA = 0 pF 6.8 13.4 ns

CDATA derating 0 0.045 ns/pF

EBI12 NWR High to NUB Change CNUB = 0 pF 5.3 11.3 ns

CNUB derating 0.022 0.045 ns/pF

EBI13 NWR High to NLB/A0 Change CNLB = 0 pF 4.5 7.6 ns

CNLB derating 0.022 0.045 ns/pF

EBI14 NWR High to A1 - A23 Change CADD = 0 pF 4.2 9.7 ns

CADD derating 0.022 0.045 ns/pF

EBI15 NWR High to Chip Select Inactive CNCS = 0 pF 4.9 11.4 ns

CNCS derating 0.022 0.035 ns/pF

EBI16 Data Out Valid before NWR High (No Wait States)(1)

C = 0 pF tCHMCK - 0.7 ns

CDATA derating -0.045 ns/pF

CNWR derating 0.035 ns/pF

EBI17 Data Out Valid before NWR High (Wait States)(1)

C = 0 pF n x tCPMCK - 0.3(2) ns

CDATA derating -0.045 ns/pF

CNWR derating 0.035 ns/pF

EBI18 Data Out Valid after NWR High 3 ns

EBI19 NWR Minimum Pulse Width (No Wait States)(1) CNWR = 0 pF tCHMCK - 0.9 ns

CNWR derating -0.01 ns/pF

EBI20 NWR Minimum Pulse Width (Wait States)(1) CNWR = 0 pF n x tCPMCK - 1.0(2) ns

CNWR derating -0.01 ns/pF

12 AT91M42800A

1776A–01/02

Notes: 1. Early Read Protocol.

2. Standard Read Protocol.

3. The derating should not be applied to tCHMCK or tCPMCK.

4. n = number of standard wait states inserted.

5. Only one of these two timings needs to be met.

Table 13. EBI Read Signals

Symbol Parameter Conditions Min Max Units

EBI21 MCK Falling to NRD Active(1) CNRD = 0 pF 8.1 14.3 ns

CNRD derating 0.029 0.045 ns/pF

EBI22 MCK Rising to NRD Active(2) CNRD = 0 pF 7.8 13.5 ns

CNRD derating 0.029 0.045 ns/pF

EBI23 MCK Falling to NRD Inactive(1) CNRD = 0 pF 7.9 13.9 ns

CNRD derating 0.022 0.035 ns/pF

EBI24 MCK Falling to NRD Inactive(2) CNRD = 0 pF 7.8 12.3 ns

CNRD derating 0.022 0.035 ns/pF

EBI25 D0 - D15 In Setup before MCK Falling Edge(5) -2.1 ns

EBI26 D0 - D15 In Hold after MCK Falling Edge(5) 6.2 ns

EBI27 NRD High to NUB Change CNUB = 0 pF 6.4 12.7 ns

CNUB derating 0.022 0.045 ns/pF

EBI28 NRD High to NLB/A0 Change CNLB = 0 pF 5.4 8.8 ns

CNLB derating 0.022 0.045 ns/pF

EBI29 NRD High to A1 - A23 Change CADD = 0 pF 5.1 11 ns

CADD derating 0.022 0.045 ns/pF

EBI30 NRD High to Chip Select Inactive CNCS = 0 pF 5.8 12.6 ns

CNCS derating 0.022 0.035 ns/pF

EBI31 Data Setup before NRD High(5) CNRD = 0 pF 10.7 ns

CNRD derating 0.035 ns/pF

EBI32 Data Hold after NRD High(5) CNRD = 0 pF -3.9 ns

CNRD derating -0.022 ns/pF

EBI33 NRD Minimum Pulse Width(1)(3) CNRD = 0 pF (n + 1) tCPMCK - 1.8(4) ns

CNRD derating -0.01 ns/pF

EBI34 NRD Minimum Pulse Width(2)(3)

CNRD = 0 pF n x tCPMCK +

(tCHMCK - 1.2)(4)

CNRD derating -0.01 ns/pF

AT91M42800A

1776A–01/02

Notes: 1. If this condition is not met, the action depends on the read protocol intended for use.

• Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle.

• Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state.

2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be

programmed.

Table 14. EBI Read and Write Control Signals. Capacitance Limitation

Symbol Parameter Conditions Min Max Units

TCPLNRD(1) Master Clock Low Due to NRD Capacitance CNRD = 0 pF 13.8 ns

CNRD derating 0.035 ns/pF

TCPLNWR(2) Master CLock Low Due to NWR Capacitance CNWR = 0 pF 11.8 ns

CNWR derating 0.035 ns/pF

14 AT91M42800A

1776A–01/02

Figure 5. EBI Signals Relative to MCK

Notes: 1. Early Read Protocol.

2. Standard Read Protocol.

NCS

A1 - A23

NRD(1)

D0 - D15 Read

MCK

NUB/NLB/A0

NRD(2)

NWAIT

NWR (No Wait States)

D0 - D15 to Write

NWR (Wait States)

No Wait Wait

EBI1/EBI2

EBI3

EBI4

EBI5EBI6

EBI9

EBI8EBI10

EBI11

EBI21

EBI22

EBI25 EBI26

EBI23

EBI4

EBI27 - 30

EBI24

EBI12 - 15

EBI16 EBI18 EBI18

EBI33

EBI34

EBI31 EBI32

EBI7

EBI19

EBI20

EBI17

AT91M42800A

1776A–01/02

Peripheral Signals

USART Signals The inputs must meet the minimum pulse width and period constraints shown in Table 15 and

Table 16, and represented in Figure 6.

Figure 6. USART Signals

Table 15. USART Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

US1SCK/RXD Minimum Pulse Width 5(tCPMCK/2) ns

Table 16. USART Minimum Input Period

Symbol Parameter Min Input Period Units

US2SCK Minimum Input Period 9(tCPMCK/2) ns

SCK

RXD

US1

US2

16 AT91M42800A

1776A–01/02

SPI Signals The inputs must meet the minimum pulse width and period constraints shown in Table 17 and

Table 18, and represented in Figure 7.

Figure 7. SPI Signals

Table 17. SPI Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

SPI1SPK/MISO/MOSI/NSS Minimum Pulse Width 3(tCPMCK/2) ns

Table 18. SPI Minimum Input Period

Symbol Parameter Min Input Period Units

SPI2 SPCK Minimum Input Period 5(tCPMCK/2) ns

SPCK

SPCK/

MISO/

MOSI/

NSS

SPI1

SPI2

AT91M42800A

1776A–01/02

Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a

corresponding output event. This delay is 3(tCPMCK) in Waveform Event Detection mode and

4(tCPMCK) in Waveform Total-count Detection mode. The inputs must meet the minimum pulse

width and minimum input period shown in Table 19 and Table 20, and as represented in Fig-

ure 8.

Figure 8. Timer Input

Reset Signals A minimum pulse width is necessary, as shown in Table 21 and as represented in Figure 9.

Figure 9. Reset Signal

Only the NRST rising edge is synchronized with MCK. The falling edge is asynchronous.

Table 19. Timer Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

TC1TCLK/TIOA/TIOB Minimum Pulse Width 3(tCPMCK/2) ns

Table 20. Timer Input Minimum Period

Symbol Parameter Min Input Period Units

TC2TCLK/TIOA/TIOB Minimum Input Period 5(tCPMCK/2) ns

MCK

IOA/

IOB/

CLK

TC2

TC1

3(tCPMCK/2) 3(tCPMCK/2)

Table 21. Reset Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

RST1NRST Minimum Pulse Width 310 µs

NRST

RST1

18 AT91M42800A

1776A–01/02

Advanced Interrupt

Controller Signals

Inputs must meet the minimum pulse width and minimum input period shown in Table 22 and

Table 23, and represented in Figure 10.

Figure 10. AIC Signals

Parallel I/O Signals

The inputs must meet the minimum pulse width shown in

Table 24

and represented in

Figure 11

Figure 11. PIO Signal

Table 22. AIC Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

AIC1FIQ/IRQ[6:0] Minimum Pulse Width 3(tCPMCK/2) ns

Table 23. AIC Input Minimum Period

Symbol Parameter Min Input Period Units

AIC2AIC Minimum Input Period 5(tCPMCK/2) ns

MCK

FIQ/IRQ2

[6:0] Input

AIC1

AIC2

Table 24. PIO Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

PIO1PIO Input Minimum Pulse Width 3(tCPMCK/2) ns

PIO

Inputs

PIO1

AT91M42800A

1776A–01/02

ICE Interface Signals

Figure 12. ICE Interface Signal

Table 25. ICE Interface Timing Specifications

Symbol Parameter Conditions Min Max Units

ICE0NTRST Minimum Pulse Width 19.2 ns

ICE1NTRST High Recovery to TCK High 0.7 ns

ICE2

NTRST High Removal from TCK

High 0.2 ns

ICE3TCK Low Half-period 42.4 ns

ICE4TCK High Half-period 40.1 ns

ICE5TCK Period 82.5 ns

ICE6TDI, TMS Setup before TCK High 1.0 ns

ICE7TDI, TMS Hold after TCK High 0.8 ns

ICE8TDO Hold Time

CTDO = 0 pF 7.2 ns

CTDO

derating 0 ns/pF

ICE9TCK Low to TDO Valid

CTDO = 0 pF 15.1 ns

CTDO

derating 0.042 ns/pF

TCK

ICE3ICE4

ICE7

ICE6

ICE9

ICE8

MS/TDI

TDO

ICE0

ICE5

NTRST

ICE1ICE2

20 AT91M42800A

1776A–01/02

JTAG Interface Signals

Table 26. JTAG Interface Timing Specifications

Symbol Parameter Conditions Min Max Units

JTAG0NTRST Minimum Pulse Width 19.2 ns

JTAG1

NTRST High Recovery to TCK

Toggle 0.8 ns

JTAG2

NTRST High Removal from TCK

Toggle 1.6 ns

JTAG3TCK Low Half-period 2.5 ns

JTAG4TCK High Half-period 3.1 ns

JTAG5TCK Period 5.6 ns

JTAG6TDI, TMS Setup before TCK High 1.7 ns

JTAG7TDI, TMS Hold after TCK High 2.5 ns

JTAG8TDO Hold Time CTDO = 0 pF 3.3 ns

CTDO derating 0 ns/pF

JTAG9TCK Low to TDO Valid CTDO = 0 pF 7.2 ns

CTDO derating 0.042 ns/pF

JTAG10 Device Inputs Setup Time -1.0 ns

JTAG11 Device Inputs Hold Time 3.0 ns

JTAG12 Device Outputs Hold Time COUT = 0 pF 4.7 ns

COUT derating 0 ns/pF

JTAG13 TCK to Device Outputs Valid COUT = 0 pF 11.9 ns

COUT derating 0.037 ns/pF

AT91M42800A

1776A–01/02

Figure 13. JTAG Interface Signal

TCK

JTAG7

JTAG6

JTAG9

JTAG8

MS/TDI

TDO

NTRST

JTAG12

JTAG13

Device

Outputs

JTAG5

JTAG4

JTAG3

JTAG0

JTAG1JTAG2

JTAG11

JTAG10

Device

Inputs

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components in life support devices or systems.

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Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Europe

Atmel SarL

Route des Arsenaux 41

Casa Postale 80

CH-1705 Fribourg

Switzerland

TEL (41) 26-426-5555

FAX (41) 26-426-5500

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Memory

Atmel Corporate

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 436-4270

FAX 1(408) 436-4314

Microcontrollers

Atmel Corporate

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 436-4270

FAX 1(408) 436-4314

Atmel Nantes

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

Atmel Rousset

Zone Industrielle

13106 Rousset Cedex, France

TEL (33) 4-42-53-60-00

FAX (33) 4-42-53-60-01

Atmel Colorado Springs

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Atmel Smart Card ICs

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

RF/Automotive

Atmel Heilbronn

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

Atmel Colorado Springs

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Atmel Grenoble

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

TEL (33) 4-76-58-30-00

FAX (33) 4-76-58-34-80

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

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