Low Power Mixer/Limiter/RSSI
3 V Receiver IF Subsystem
AD608
Rev. C
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FEATURES
Mixer
−15 dBm, 1 dB compression point
−5 dBm IP3
24 dB conversion gain
>500 MHz input bandwidth
Logarithmic/limiting amplifier
80 dB RSSI range
±3° phase stability over 80 dB range
Low power
21 mW at 3 V power consumption
CMOS-compatible power-down to 300 μW typical
200 ns enable/disable time
APPLICATIONS
PHS, GSM, TDMA, FM, or PM receivers
Battery-powered instrumentation
Base station RSSI measurements
GENERAL DESCRIPTION
The AD608 provides a low power, low distortion, low noise mixer
as well as a complete, monolithic logarithmic/limiting amplifier
that uses a successive-detection technique. In addition, the AD608
provides both a high speed received signal strength indicator
(RSSI) output with 80 dB dynamic range and a hard-limited
output. The RSSI output is from a two-pole postdemodulation
low-pass filter and provides a loadable output voltage of 0.2 V to
1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply
at a typical power level of 21 mW at 3 V.
The RF and local oscillator (LO) bandwidths both exceed
500 MHz. In a typical IF application, the AD608 can accept the
output of a 240 MHz surface acoustic wave (SAW) filter and down-
convert it to a nominal 10.7 MHz IF with a conversion gain of
24 dB (ZIF = 165 Ω). The AD608 logarithmic/limiting amplifier
section handles any IF from low frequency (LF) up to 30 MHz.
The mixer is a doubly balanced gilbert-cell mixer and operates
linearly for RF inputs spanning −95 dBm to −15 dBm. It has a
nominal −5 dBm third-order intercept. An on-board LO pre-
amplifier requires only −16 dBm of LO drive. The current output
of the mixer drives a reverse-terminated, industry-standard
10.7 MHz, 330 Ω filter.
The nominal logarithmic scaling is such that the output is +0.2 V
for a sinusoidal input to the IF amplifier of −75 dBm and +1.8 V
at an input of +5 dBm; over this range, the logarithmic confor-
mance is typically ±1 dB. The logarithmic slope is proportional
to the supply voltage. A feedback loop automatically nulls the
input offset of the first stage down to the submicrovolt level.
The AD608 limiter output provides a hard-limited signal output
at 400 mV p-p. The voltage gain of the limiting amplifier to this
output is more than 100 dB. Transition times are 11 ns and the
phase is stable to within ±3° at 10.7 MHz for signals from −75 dBm
to +5 dBm.
The AD608 is enabled by a CMOS logic-level voltage input,
with a response time of 200 ns. When disabled, the standby
power is reduced to 300 μW within 400 ns.
The AD608 is specified for the industrial temperature range of
−25°C to +85°C for 2.7 V to 5.5 V supplies and −40°C to +85°C for
3.0 V to 5.5 V supplies. This device comes in a 16-lead plastic SOIC.
FUNCTIONAL BLOCK DIAGRAM
24dB MIXER GAIN
110dB LIMITER GAIN
90dB RSSI
BIAS
MXOP
MIXER
BPF
DRIVER
VMID
LO
PREAMP
AD608
RFHI
RFLO
IF INPUT
–75dBm TO
+15dBm
2
IFHI
IFLO
LMOP
VPS2
RSSI
FDBK
COM3
FINAL
LIMITER
100nF
10nF
330Ω
±50µA
330Ω
MIDSUPPLY
IF BIAS
LIMITER
OUTPUT
400mV p-p
PRUP
RF INPUT
–95dBm TO
–15dBm
1
VPS1 COM1 COM2LOHI
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
3dB NOMINAL
INSERTION LOSS
+2.7V TO 5.5V
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
7 FULL-WAVE
RECTIFIER CELLS
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
100Ω
18nF
1
–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
2
39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.
2MHz
LPF
10.7MHz
BAND-PASS
FILTER
5
6
1 2 3 4 16
8
7
10
13
9
15
14
12
11
+
+
+
07886-001
Figure 1.
AD608
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits ....................................................................................... 8
Theory of Operation ........................................................................ 9
Mixer ...............................................................................................9
Mixer Gain .....................................................................................9
IF Filter Terminations ................................................................ 10
The Logarithmic IF Amplifier .................................................. 10
Offset Feedback Loop ................................................................ 10
RSSI Output ................................................................................ 11
Digitizing the RSSI ..................................................................... 11
Power Consumption .................................................................. 11
Troubleshooting .......................................................................... 11
Applications Information .............................................................. 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
2/09—Rev. B to Rev. C
Updated Format .................................................................. Universal
Reorganized Layout ............................................................ Universal
Change to General Description Section ........................................ 1
Changes to DC Level Parameter, Operating Range Parameter,
and TMIN to TMAX Parameter, Table 1 .......................................... 3
Added Typical Performance Characteristics Heading ................ 6
Added Test Circuits Heading .......................................................... 8
Changes to Figure 17 and Figure 19 ............................................... 8
Change to Figure 22 ......................................................................... 9
Changes to Table 5 ............................................................................ 9
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 13
AD608
Rev. C | Page 3 of 16
SPECIFICATIONS
TA = 25°C, supply = 3 V, dBm is referred to 50 Ω, unless otherwise noted.
Table 1.
Parameter Conditions1 Min Typ Max Unit
MIXER PERFORMANCE
RF and LO Frequency Range 500 MHz
LO Power Input terminated in 50 Ω −16 dBm
Conversion Gain Driving doubly terminated 330 Ω IF filter, ZIF = 165 Ω 19 24 28 dB
Noise Figure Matched input, fRF = 100 MHz 11 dB
Matched input, fRF = 240 MHz 16 dB
1 dB Compression Point Input terminated in 50 Ω −15 dBm
Third-Order Intercept fRF = 240 MHz and 240.02 MHz, fLO = 229.3 MHz −5 dBm
Input Resistance fRF = 100 MHz (see Table 5) 1.9 kΩ
Input Capacitance fRF = 100 MHz (see Table 5) 3 pF
LIMITER PERFORMANCE
Gain Full temperature and supply range 110 dB
Limiting Threshold 3° rms phase jitter at 10.7 MHz −75 dBm
280 kHz IF bandwidth
Input Resistance 10 kΩ
Input Capacitance 3 pF
Phase Variation −75 dBm to +5 dBm IF input signal at 10.7 MHz ±3 Degrees
DC Level Center of output swing (VPOS – 1 V) 2 V
Output Level Limiter output driving 5 kΩ load 400 mV p-p
Rise and Fall Times Driving a 5 pF load 11 ns
Output Impedance 200 Ω
RSSI PERFORMANCE At 10.7 MHz
Nominal Slope At VPOS = 3 V; proportional to VPOS 17.27 20 23.27 mV/dB
Nominal Intercept −85 dBm
Minimum RSSI Voltage −75 dBm input signal 0.2 V
Maximum RSSI Voltage +5 dBm input signal 1.8 V
RSSI Voltage Intercept 0 dBm input signal 1.57 1.82 V
Logarithmic Linearity Error −75 dBm to +5 dBm input signal at IFHI ±1 dB
RSSI Response Time 90% RF to 50% RSSI 200 ns
Output Impedance At midscale 250 Ω
POWER-DOWN INTERFACE
Logic Threshold System active on logic high 1.5 V
Input Current For logic high 75 mA
Power-Up Response Time Active limiter output 200 ns
Power-Down Response Time To 200 μA supply current 400 ns
Power-Down Current 100 μA
POWER SUPPLY
Operating Range −25°C to +85°C 2.7 5.5 V
−40°C to +85°C 3.0 5.5 V
Powered Up Current VPOS = 3 V 7.3 mA
OPERATING TEMPERATURE
TMIN to TMAX VPOS = 2.7 V to 5.5 V −25 +85 °C
VPOS = 3.0 V to 5.5 V −40 +85 °C
1 VPOS is used to refer collectively to the VPS1 and VPS2 pins.
AD608
Rev. C | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltages VPS1, VPS2 +6 V
Internal Power Dissipation 600 mW
Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3.
Package Type θJA Unit
16-Lead SOIC 110 °C/W
ESD CAUTION
AD608
Rev. C | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPS1
COM1
PRUP
LMOP
RFHI
RFLO
MXOP
COM3
RSSI
IFLO
LOHI
COM2
VPS2
FDBK
IFHI
VMID
1
2
3
4
16
15
14
13
512
611
710
8 9
AD608
TOP VIEW
(Not to Scale)
07886-002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VPS11 Positive Supply Input
2 COM1 Common
3 LOHI Local Oscillator Input Connection
4 COM2 Common
5 RFHI RF Input, Noninverting
6 RFLO RF Input, Inverting
7 MXOP Mixer Output
8 VMID Midpoint Supply Bias Output
9 IFHI IF Input, Noninverting
10 IFLO IF Input, Inverting
11 RSSI Received Signal Strength Indicator Output
12 COM3 Output Common
13 FDBK Offset-Null Feedback Loop Output
14 VPS21 Limiter Positive Supply Input
15 LMOP Limiter Output
16 PRUP Power-Up
1 VPOS is used to refer collectively to the VPS1 and VPS2 pins in this data sheet.
AD608
Rev. C | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
RF FREQUENCY (MHz)
MIXER CONVERSION GAIN (dB)
25.0
23.5
22.0
500500100 150 200 250 300 350 400 450
24.5
24.0
23.0
22.5
07886-005
Figure 3. Mixer Conversion Gain vs. RF Frequency
IF FREQUENCY (MHz)
MIXER RESPONSE (dB)
0
–8
8010020 30 40 50 60 70
–1
–4
–5
–6
–7
–2
–3
07886-006
Figure 4. Mixer IF Port Bandwidth
INPUT POWER AT IFHI (dBm)
RSSI OUTPUT (V)
3.0
0
10–70–80 –60 –50 –40 0–20 –10–30
2.5
2.0
1.5
1.0
0.5
5V
3V
0
7886-007
Figure 5. IF RSSI Output vs. Input Power at IFHI and Supply Voltage,
Ambient Temperature (See Figure 15)
INPUT POWER (dBm)
RSSI OUTPUT (V)
3.0
0
2.5
2.0
1.5
1.0
0.5
+85°C
+25°C
–25°C
10–70–80 –60 –50 –40 0–20 –10–30
0
7886-008
Figure 6. IF RSSI Output vs. Input Power and Temperature,
3 V Supply (See Figure 15)
INPUT POWER (dBm)
RSSI ERROR (dB)
4
–4
10–80 –70 –50 0–60 –40 –20 –10–30
3
0
–1
–2
–3
2
1
5V
3V
07886-010
Figure 7. RSSI Error vs. Input Power
(See Figure 15)
PRUP RSSI
0
7886-011
100ns/DIV
800mV/DIV
100ns/DIV
1V/DIV
Figure 8. RSSI Power-Up Response
(See Figure 19)
AD608
Rev. C | Page 7 of 16
RSSI IFHI
07886-013
200mV/DIV
800mV/DIV 50ns/DIV
Figure 9. RSSI Pulse Response/RSSI Rise Time
(See Figure 16)
LMOP
07886-015
20ns/DIV
60mV/DIV
Figure 10. Limiter Rise and Fall Times
(See Figure 20)
PRUP LMOP
0
7886-017
220mV/DIV 100ns/DIV
100ns/DIV
1V/DIV
Figure 11. Limiter Power-Up Response Time
(See Figure 17)
INPUT POWER AT IFHI (dBm)
5
–5
4
–1
–2
–3
–4
3
2
0
1
LIMITER PHASE (Degrees)
10–80 –70 –50 0–60 –40 –20 –10–30
0
7886-019
Figure 12. Limiter Phase Performance vs. Input Power at IFHI
(See Figure 21)
INPUT POWER AT IFHI (dBm)
10
0
9
4
3
2
1
8
7
5
6
LIMITER RMS JITTER (Degrees)
10–80 –70 –50 0–60 –40 –20 –10–30
0
7886-021
Figure 13. Limiter RMS Jitter Performance vs. Input Power at IFHI
(See Figure 21)
AD608
Rev. C | Page 8 of 16
TEST CIRCUITS
PRUP INPUT
VPOS
51.
1Ω
51.1Ω
0.1µF
1nF
1nF
332Ω
0.1µF
332Ω
301Ω
54.9Ω
IF INPUT
0.1µF
10nF RSSI OUTPUT
100Ω
18nF
0.1µF
LMOP OUTPUT
TRIGGER
4.7kΩ
U1 – 74HC00
0.1µF
U1A
U1B
47kΩ
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD608
VPS1
COM 1
RFHI
RFLO
MXOP
LOHI
COM 2
VMID
PRUP
LMOP
COM3
RSSI
IFLO
VPS2
FDBK
IFHI
0
7886-003
Figure 14. IF Test Board Schematic
IFHI
VPOS
RSSI
IF TEST BOARD
10.7MHz
FLUKE 6082A
SYNTHESIZER
DCPS
DC POWER
SUPPLY
(DCPS)
3V
AGILENT
HP3366A
DMM
DIGITAL
MULTIMETER
(DMM)
AGILENT
HP34401A
07886-009
Figure 15. Test Circuit for IF RSSI Output vs. Input Power at IFHI and Supply
Voltage, Ambient Temperature (Figure 5); IF RSSI Output vs. Input Power and
Temperature, 3 V Supply (Figure 6); and RSSI Error vs. Input Power (Figure 7)
IFHI
VPOS
RSSI
IF TEST BOARD
AGILENT
HP3366A
FET
PROBE
TEKRONIX
P6201
CH 1
CH 2
COUPLER
MCL
ZDC-20-1
AGILENT
HP54120A
DIGITAL
OSCILLOSCOPE
3VDCPS
10.7MHz
0dBm
FLUKE 6082A
SYNTHESIZER
07886-014
Figure 16. Test Circuit for RSSI Pulse Response/RSSI Rise Time (Figure 9)
IFHI
VPOS
LMOP
IF TEST BOARD
3V
AGILENT
HP3366A
TEKRONIX
P6201
PRUP
CH 1
CH 2
AGILENT
HP54120A
DIGITAL
OSCILLOSCOPE
DCPS
10.7MHz
0dBm
FLUKE 6082A
SYNTHESIZER
FET
PROBE
07886-018
Figure 17. Test Circuit for Limiter Power-Up Response Time (Figure 11)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD608
VPS1
COM1
RFHI
RFLO
MXOP
LOHI
COM2
VMID
PRUP
LMOP
COM3
RSSI
IFLO
VPS2
FDBK
IFHI
VPOS
LO INPUT
RF INPUT
IF OUTPUT
NC
NC
0.1µF
1nF
51.1Ω
1nF
332
Ω
301
Ω
0.1µF
54.9
Ω
51.1Ω
1nF
0.1µF 332
Ω
10nF
100
Ω
18nF
18nF
47k
Ω
NC = NO CONNECT
0
7886-004
Figure 18. Mixer Test Board Schematic
IFHI
VPOS
RSSI
IF TEST BOARD
10.7MHz
0dBm
FLUKE 6082A
SYNTHESIZER
DCPS
AGILENT
HP3366A
FET
PROBE
TEKRONIX
P6201
PRUP
CH 1
CH 2
A
GILENT
HP54120A
DIGITAL
OSCILLOSCOPE
3V
07886-012
Figure 19. Test Circuit for RSSI Power-Up Response (Figure 8)
IFHI
VPOS
LMOP
IF TEST BOARD
10.7MHz
0dBm
FLUKE 6082A
SYNTHESIZER
DCPS
AGILENT
HP3366A
FET
PROBE
TEKRONIX
P6201
A
GILENT
HP54120A
DIGITAL
OSCILLOSCOPE
3V
07886-016
Figure 20. Test Circuit for Limiter Rise and Fall Times (Figure 10)
IFHI RSSI
IF TEST BOARD
10.7MHz
FLUKE 6082A
S
YNTHESIZER
DCPS 3V
AGILENT
HP3366A
FET
PROBE
TEKTRONIX
P6201
CH 1
TRIG
AGILENT
HP54120A
DIGITAL
OSCILLOSCOPE
MCL
ZDC-20-1
BPF
AGILENT
HP8447A
AGILENT
HP8494A
HP8495A
280kHz BW
10.7MHz CF
TOKO SK107MK1-A0-10
COUPLER
07886-020
Figure 21. Test Circuit for Limiter Phase Performance vs. Input Power at IFHI
(Figure 12) and Limiter RMS Jitter Performance vs. Input Power at IFHI (Figure 13)
AD608
Rev. C | Page 9 of 16
THEORY OF OPERATION
The AD608 consists of a mixer followed by a logarithmic IF
strip with RSSI and hard-limited outputs (see Figure 22).
MIXER
The mixer is a doubly balanced, modified gilbert-cell mixer. Its
maximum input level for linear operation is either ±56.2 mV,
regardless of the impedance across the mixer inputs, or −15 dBm
for a 50 Ω input termination. The input impedance of the mixer
can be modeled as a simple parallel RC network; the resistance
and capacitance values vs. frequency are listed in Table 5. The
bandwidth from the RF input to the IF output at the MXOP pin
is −1 dB at 30 MHz and then rapidly decreases as frequency
increases (see Figure 4).
MIXER GAIN
The conversion gain of the mixer is the product of its trans-
conductance and the impedance seen at Pin MXOP. For a 330 Ω
parallel-terminated filter at 10.7 MHz, the load impedance is
165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV (or
±891 mV) centered on the midpoint of the supply voltage. For
other load impedances, the expression for the gain in decibels is
GdB = 20 log10(0.0961 RL)
where:
GdB is the gain in decibels.
RL is the load impedance at Pin MXOP.
The gain of the mixer can be increased or decreased by changing
RL. The limitations on the gain are the ±6 mA maximum output
current at MXOP and the maximum allowable voltage swing at
Pin MXOP, which is ±1.0 V for a 3 V supply or 5 V supply.
24dB MIXER GAIN
110dB LIMITER GAIN
90dB RSSI
BIAS
MXOP
MIXER
BPF
DRIVER
VMID
LO
PREAMP
AD608
RFHI
RFLO
IF INPUT
–75dBm TO
+15dBm
2
IFHI
IFLO
LMOP
VPS2
RSSI
FDBK
COM3
FINAL
LIMITER
100nF
10nF
330Ω
±50µA
330Ω
MIDSUPPLY
IF BIAS
LIMITER
OUTPUT
400mV p-p
PRUP
RF INPUT
–95dBm TO
–15dBm
1
VPS1 COM1 COM2
LOHI
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
3dB NOMINAL
INSERTION LOSS
2.7V TO 5.5V
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
7 FULL-WAVE
RECTIFIER CELLS
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
100Ω
18nF
1
–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
2
39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.
2MHz
LPF
10.7MHz
BAND-PASS
FILTER
5
6
1 2 3 4 16
8
7
10
13
9
15
14
12
11
+
+
+
07886-022
Figure 22. Functional Block Diagram
Table 5. Mixer Input Impedance vs. Frequency
Frequency (MHz) Resistance (Ω) Capacitance (pF)
45 2800 3.1
70 2600 3.1
100 1900 3.0
200 1200 3.1
300 760 3.2
400 520 3.4
500 330 3.6
AD608
Rev. C | Page 10 of 16
IF FILTER TERMINATIONS
The AD608 was designed to drive a parallel-terminated 10.7 MHz
band-pass filter (BPF) with a 330 Ω impedance. With a 330 Ω
parallel-terminated filter, Pin MXOP sees a 165 Ω termination,
and the gain is nominally 24 dB. Other filter impedances and
gains can be accommodated by either accepting an increase or
decrease in gain in proportion to the filter impedance or by
keeping the impedance seen by MXOP at a nominal 165 Ω (by
using resistive dividers or matching networks). Figure 23 shows a
simple resistive voltage divider for matching an assortment of
filter impedances, and Tabl e 6 lists component values.
THE LOGARITHMIC IF AMPLIFIER
The logarithmic IF amplifier consists of five amplifier stages
of 16 dB gain each, plus a final limiter. The IF bandwidth is
30 MHz (−1 dB), and the limiting gain is 110 dB. The phase
skew is ±3° from −75 dBm to +5 dBm (approximately 111 μV p-p
to 1.1 V p-p). The limiter output impedance is 200 Ω, and the
limiter output drive is ± 200 mV (400 mV p-p) into a 5 kΩ load.
In the absence of an input signal, the limiter output limits noise
fluctuations, producing an output that continues to swing
400 mV p-p, but with random zero crossings.
OFFSET FEEDBACK LOOP
Because the logarithmic amplifier is dc-coupled and has more
than 110 dB of gain from the input to the limiter output, a dc
offset at its input of even a few microvolts causes the output to
saturate. Therefore, the AD608 uses a low frequency feedback
loop to null the input offset. Referring to Figure 23, the loop
consists of a current source driven by the limiter, which sends
50 μA current pulses to Pin FDBK. The pulses are low-pass filtered
by a π-network consisting of C1, R4, and C5. The smoothed dc
voltage that results is subtracted from the input to the IF amplifier
at Pin IFLO. Because this is a high gain amplifier with a feedback
loop, care should be taken in layout and component values to
prevent oscillation. Recommended values for the common IFs
of 450 kHz, 455 kHz, 6.5 MHz, and 10.7 MHz are listed in Table 6.
5V
C2
100pF
47kΩ
24dB MIXER GAIN 110dB LIMITER GAIN
90dB RSSI
BIAS
MXOP
MIXER
BPF
DRIVER
VMID
LO
PREAMP
AD608
RFHI
RFLO
IFHI
IFLO
LMOP
VPS2
RSSI
FDBK
COM3
FINAL
LIMITER
100nF
C5
R1
±50µA
R3
MIDSUPPLY
IF BIAS
PRUPVPS1 COM1 COM2LOHI
12dB NOMINAL
INSERTION LOSS
(ASSUMES 6dB IN FILTER)
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
7 FULL-WAVE
RECTIFIER CELLS
LO INPUT
–16dBm
CMOS LOGIC
INPUT
R4
C1
2MHz
LPF
BAND-PASS
FILTER
5
6
1 2 3 4 16
8
7
10
13
9
15
14
12
11
R2
+
+
+
C1
1µF
07886-023
Figure 23. Applications Diagram for Common IFs and Filter Impedances
Table 6. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs
IF Filter Impedance
Filter Termination Resistor
Values1 for 24 dB of Mixer Gain
Offset-Null
Feedback Loop Values
R1 R2 R3 R4 C1 C5
450 kHz2
1500 Ω 174 Ω 1330 Ω 1500 Ω 1000 Ω 200 nF 100 nF
455 kHz 1500 Ω 174 Ω 1330 Ω 1500 Ω 1000 Ω 200 nF 100 nF
6.5 MHz 1000 Ω 178 Ω 825 Ω 1000 Ω 100 Ω 18 nF 10 nF
10.7 MHz 330 Ω 330 Ω 0 Ω 330 Ω 100 Ω 18 nF 10 nF
1 Resistor values were calculated so that R1 + R2 = ZFILTER and R1||(R2 + ZFILTER) = 165 Ω.
2 Operation at IFs of 450 kHz and 455 kHz requires use of an external low-pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple at 900 kHz).
AD608
Rev. C | Page 11 of 16
RSSI OUTPUT
The logarithmic amplifier uses a successive-detection architecture.
Each of the five stages has a full-wave detector; two additional
high level detectors are driven by attenuators at the input to the
limiting amplifiers, for a total of seven detector stages. Because
each detector is a full-wave rectifier, the ripple component in
the resulting dc is at twice the IF. The AD608 low-pass filter has
a 2 MHz cutoff frequency, which is one decade below the 21.4 MHz
ripple that results from a 10.7 MHz IF.
For operation at lower IFs, such as 450 kHz or 455 kHz, the
AD608 requires an external low-pass filter with a single pole
located at 90 kHz, a decade below the 900 kHz ripple frequency
for these IFs. The RSSI range is from the noise level at approx-
imately −80 dBm to overload at +15 dBm and is specified for
±1 dB accuracy from −75 dBm to +5 dBm. The +15 dBm
maximum IF input is provided to accommodate band-pass
filters of lower insertion loss than the nominal 4 dB for
10.7 MHz ceramic filters.
DIGITIZING THE RSSI
In typical cellular radio applications, the RSSI output of the
AD608 is digitized by an analog-to-digital converter (ADC).
The RSSI output of the AD608 is proportional to the power
supply voltage, which not only allows the ADC to use the
supply as a reference, but also causes the RSSI output and the
ADC output to track over power supply variations, reducing
system errors and component costs.
POWER CONSUMPTION
The total power supply current of the AD608 is a nominal
7.3 mA. The power is signal dependent, partly because the RSSI
output increases (the current is increased by 200 μA at an RSSI
output of +1.8 V), but mostly due to the IF consumption of the
band-pass filter when driven to ±891 mV, assuming a 4 dB loss
in this filter and a peak input of +5 dBm to the log-IF amp. In
addition, the power is temperature dependent because the
biasing system used in the AD608 is proportional to the
absolute temperature (PTAT).
TROUBLESHOOTING
The most common causes of problems with the AD608 are
incorrect component values for the offset feedback loop, poor
board layout, and pickup of radio frequency interference (RFI),
which all cause the AD608 to lose the low end (typically below
−65 dBm) of its RSSI output and cause the limiter to swing
randomly. Both poor board layout and incorrect component
values in the offset feedback loop can cause low level oscillations.
Pickup of RFI can be caused by improper layout and shielding
of the circuit.
AD608
Rev. C | Page 12 of 16
APPLICATIONS INFORMATION
Figure 24 shows the AD608 configured for operation in a digital
system at a 10.7 MHz IF. The input and output impedance of the
filter are parallel terminated using 330 Ω resistors, and the
conversion gain is 24 dB. The RF port is terminated in 50 Ω; in
a typical application, the input is matched to a SAW filter using
the impedance data provided in Table 5.
Figure 25 shows the AD608 configured for narrow-band FM
operation at a 450 kHz or 455 kHz with an external discriminator.
The IF filter has 1500 Ω input and output impedances—the
input is matched via a resistive divider, and the output is
terminated in 1500 Ω. The discriminator requires a 1 V p-p
drive from a 1 kΩ source impedance, which in Figure 25 is
provided by a Class A amplifier with a gain of 2.5.
10.7MHz BPF Z = 330Ω
R2
330Ω
C5
0.1µF
R1
330Ω
C2
100pF
C3
100pF
C4
100pF
C1
1µF
V
POS
LIMO
C6
10nF
SUPPLY
2.7V TO 5.5V
POWER-UP
3V CMOS
LO INPUT
–16dBm
RF INPUT
–95dBm
TO
–15dBm
C7
18nF
16
15
12
11
10
14
13
9
1
2
5
6
7
3
4
8
AD608
VPS1
COM1
RFHI
RFLO
MXOP
LOHI
COM2
VMID
PRUP
LMOP
COM3
RSSI
IFLO
VPS2
FDBK
IFHI
R3
100Ω
R4
47kΩ
R6
51.1Ω
R5
51.1Ω
LIMITER
OUTPUT
VPOS –1V
±200mV
RSSI OUTPUT
+0.2V TO +1.8V
(20mV/dB)
+
+
+
+
+
+
+
07886-024
OFFSET-CONTROL
LOOP FILTER
BPF
TEMINATION
IF BIAS POINT
DECOUPLING
BPF REVERSE
TERMINATION
BIAS POINT
AT VPOS/2
Figure 24. Application at 10.7 MHz (the Band-Pass Filter Can Be a Toko SK107 or Murata SFE10.7)
+5V
R1
51.1Ω
R2
51.1Ω
C1
0.1µF
C2
1nF
GND 1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD608
VPS1
COM1
RFHI
RFLO
MXOP
LOHI
COM2
VMID
PRUP
LMOP
COM3
RSSI
IFLO
VPS2
FDBK
IFHI
R3
374Ω
R4
1.5kΩ
R6
1kΩ
LOHI
RFHI
C3
1nF
R7
1130ΩF1
C7
0.1µF
C6 0.1µF
C8 0.1µF
C9
0.2µF R5
200Ω
C5 0.1µF
R14
8.66kΩ
R15
24.9kΩ
R13
402Ω
R12
1kΩCR1
CR2
R8
1kΩ
R9
1kΩ
C10
0.01µF
R11
3.3kΩ
AUDIO
PRUP
RSSI
JUMPE
R
F1: TOKO HCFM2–455B
F2: MURATA CFY455S
CR1, CR2: 1N60
Q1: 2N3906
F2 R10
3.3kΩ
R16
47kΩ
Q1
C11
0.1µF
C4
1nF
07886-025
Figure 25. Narrow-Band FM Application at 450 kHz or 455 kHz
AD608
Rev. C | Page 13 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 26. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD608AR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
AD608AR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
AD608ARZ1
−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
AD608ARZ-RL1
−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
EVAL-AD608EBZ1
Evaluation Board
1 Z = RoHS Compliant Part.
AD608
Rev. C | Page 14 of 16
NOTES
AD608
Rev. C | Page 15 of 16
NOTES
AD608
Rev. C | Page 16 of 16
NOTES
©1996–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07886-0-2/09(C)
