General Description The MAX178 is a complete, calibrated 12-bit A/D con- verter (ADC) which includes a precision voltage refer- ence, track-and-hold, and conversion clock. Internal calibration circuitry maintains true 12-bit performance over the full operating temperature range without external adjustments. In addition, each conversion includes an auto-zero cycle which reduces zero errors to typically below 100ynV CHIP SELECT, READ, and WRITE inputs are included for easy microprocessor interfacing without additional logic. 2-byte, 12-bit conversion data is provided over an 8-bit three-state output bus. Either byte may be read first. Two converter busy flags facilitate polling of the converters status. The MAX178s analog input range is OV to +5V when using a +5V reference. The MAX178As internal refer- ence accuracy is 0.3%, while the MAX178B is intended for use with an external reference. Applications Digital-Signal Processing Audio and Telecom Processing High-Speed Data Acquisition High-Accuracy Process Control Pin Configuration MA AXAXLNVI Calibrated 12-Bit ADC with T/H and Reference Features @ Continuous Transparent Calibration of Offset and Gain @ True 12-Bit Performance without Adjustments @ T/H Front End and Internal Reference # DC and Dynamically Specified @ Zero Error Typically <100uV @ Standard Microprocessor Interface @ 24-Pin DIP and Wide SO Packages Ordering Information PART [_ TEMP. RANGE PIN-PACKAGE | MAX17BACNG OC to +70C 24 Plastic DIP | MAX178BCNG OC to +70C 24 Plastic DIP | MAXI78ACWG OC to. + 70C 24 Wide SO" | | MAX178BCWG OC lo +70 24 Wide SO MAX178AENG -40C to +85C 24 Plastic DIP | MAX178BENG 40C to 485C 24 Plastic DIP MAX178AEWG -40'C to +85C 24 Wide SO" | | MAX1788EWG -40C to +85 C 24 Wide SO* MAX178AMRG -55'C to +125 C 24 CERDIP | [ Maxi7aBMaG 55Cto +125C 24 CERDIP * Consult factory. Functional Diagram TOP VIEW CAZ = Vio Vs Voc | 1 | 4 |B 7 ; CJ = . ANAXLMA| >> REFOUIT va ba oo to MAXI78 an AIN [2 | [23] ss ~ RUTO-2ERO NC[3] Anapenan [22] REFOUT ve 3 COMPARATOR REFIN| 4) MAX178 [at clk __ | AGNO [5 | f20] BUSY rein f= I 12-17 DAC | peno [6 | 19] BYSL ~ ao Vee | 7 | ia} WR SR 174 | Wi acnn > [___ sar LH vay oa? [8 17] CS I, P| AJ THREE- BK pas | 9 16! RD SIAIE \, DATA _ 21 CLK \ QUTPUT / OUT ops [10] 15] DBO(LS8) CLK PF] age f* ORIVERS 15 in i pea |14 14] 0Bt 288 4 ___ 1 20 na 12! 13, 082 1, CONTROL roo | BUSY Tie In7 lig Tp) 6 DIP/SO aD cS wR Bysl OGND MAZIXIsvI Maxim Integrated Products 1 MAXIM is aregistered trademark of Maxim Integrated Products. SZLIXVINMAX178 Calibrated 12-Bit ADC with T/H and Reference ABSOLUTE MAXIMUM RATINGS VoptoDGND ................ ce. -0.3V. +17V Operating Temperature Range Vsg to DGND_ . an cece. 4+0.3V,-7V MAX178 C OC to +70C AGNDtoDGND .............. -0.3V, REFIN +0.3V MAX178 E -40'C to +85'C VectoDGND swe ... -O0.38V, +7V MAX178_.M va -55 C to +125 C REFINtoAGND .............. . -0.3V, Vion +0.3V Power Dissipation (any Package) AIN to AGND co. . -0.3V, Vin +0.3V To+75C 1,000mWw Digital Input Voltage to DGND -0.3V, Vin +0.3V Derate above +75 'C by . 1OmWw/C Digital Output Voltage toDGND ..... -0.3V, Vop +0.3V Storage Temperature ..... 65 C lo +1506 Lead Temperature (Soldering. 10 sec.) +300 C Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage to the device Ihese are stress ratings only, and funchonai operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications 1s notimplied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS (VoD = +15V. Voc = +5V, Vss = -5V, REFIN = +5.0V. all specifications TA = TMIN to TMAX. fCLK = 266.67kKHz external. unless otherwise PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS ACCURACY Resolution ite Bits Total Unadjusted Error (Note 1) TUE +1 LSB Differential Nonlinearity DNL No missing codes guaranteed +1 LSB Full-Scale Error (Gain Error) Ta = +25C OO +1/2 LSB [ Full-Scale Error Tempco _, 0.5 ppm/ C Zero Error | Ta = +25C +1/2 SB | Zero Error Tempco 0.5 pom/ Cc ANALOG INPUT a : : Input Voltage Range , VREF = +5V 0 +5 v On-Channel Input Capacitance CAIN : 8 pF AIN = OV to +5V Input Leakage Current IAIN TA = +25C 10 nA Ta = TMIN to TMAX 100 | DYNAMIC ACCURACY (t WA = 14.81kHz. fAIN = 2.011kKH7, Ta = 25C, Note 2) Signal-to-Noise + Distortion SAN + D) _ 70 dB |_Total Harmonic Distortion THD 80 dB Peak bartonc 2 a REFERENCE INPUT For specified performance +5 45% | REFIN Range VREFIN Vv - | Degraded transfer accuracy +4 +6 | REFIN Input Current REFIN = +5V 1.0 mA REFERENCE OUTPUT 7 - MAX178A REFOUT Voltage Ta=+250 0 44.985 45 45.015 V REFOUT Temp (C) +10 +40 ppm/ C REFOUT Sink Current 1 mA MAX178B Use External Reference Only MIA AISICalibrated 12-Bit ADC with T/H and Reference ELECTRICAL CHARACTERISTIC (continued) (Vop = +15V, Voc = +V. Vss = -5V, REFIN = +5.0V, all specifications TA = TMIN to TMAX. {CLK = 266.67kHz external, unless otherwise noted.) "PARAMETER | SYMBOL CONDITIONS | MIN TYP MAX | UNITS LOGIC INPUTS _ | RD, cs. WR, BYSE __ | _ Input High Voltage _| _VIH | Vcc = + = +5V +5 (15% i +24 | Input Low Voltage ; VIL Voc = +5V 45% +0.8 | | | VIN = 0 to Vcc: | Input Current liN Ta = 425C +1 | HA | _ ee TA=TMINtOTMAX _ | +10 | __ Input Capacitance | CIN | (Note 3) 10 | pF | CLOCK _ a Input High Voltage Vid | Voc = +5V 45% 7 | +3.0 | | _Input Low Voltage vin Voc = +5V +5% i _ +0.8 | Input High Current NH , Veco = +5V +5% 1.5 mA | __Input Low Current ot | Voc = +5V +5% | _ 12 nA | LOGIC OUTPUTS a | DBO-DB. BUSY a __ | _ Output High Voltage _ Vox , | Vcc = = 45V: 45%, ISOURCE = 200UA +4.0 | Vv | Output Low Voltage VOL + Voc = +5V +5%. ISINK = 1.6mA 4 +04 Vv JW _ _ Floating State Leakage - | Current (DBO-DB7) ILKG "= = OV to Vcc | + WA | | P| Floating State Output | Capacitance (OB0-D87)_ Cour | mews) _ me PR | CONVERSION TIME (Note 4) _ _ 7 | With External Clock FOLK = 266.67KH2 60 1 us _ =| Ks 200.07" __ = _ + With Internal Clock Ta=+25'C Tt 90, vo | ons | POWER R REQUIREMENTS ITS(Note5) _ _ VoD laa +15.75 | | Power-Supply Voltage - Vss __ __ _ 445 -5.25 Vv | _ Veo [| Lt _ | +4.75 +5,25 | | Vop Supply Rejection: 4 Yoo = +14.25V to +15.75V. Vss = -5V _ 1/8 | LSB | | ss Supply Rejection _ I VSS = -4.75V to -5.25V, Vop = +15V | _ +1/8 LSB Vpb Supply Rejection | Vob = +11.4V to +12.6V. Vss=-5V | +1/8 - | LSB | Vsg Supply Rejection | Vsg = -4.75V to -8.25V, VoD = +12V_ ; _ 118 LSB UL Ipp | VIN= VIL orVIH | 6 10 | Power-Supply Current Iss | a | 8 | mA | Ico | 0.1 1.0 __ | Note 1: Includes: Full-Scale Error, Ole Error, Relative Accuracy Note 2: Up to 5th Harmonic is measured Note 3: Guaranteed by design Note 4: Track/Hold aquisition time included in conversion time. using t13 condition (see Timing Characteristics Note 5: Power-supply current is measured when MAX178 is inactive (CS = WR = RD = BUSY = High). MAAILSVI 3 8ZELXVINMAX178 Calibrated 12-Bit ADC with T/H and Reference TIMING CHARACTERISTICS (Note 6, Figures 1 and 2) (Vop = +15V, Voc = +5V, Vss = -5V, REFIN = +5.0V, unless otherwise noted.) Ta=425C |Ta=-40C to 485C] Ta = -55'C to +125C PARAMETER SYMBOL | CONDITIONS -~ __ UNITS MIN TYP MAX' MIN TYP MAX! MIN TYP CS to WR Setup Time 4 0 2) a) ns WR Pulse Width t2 120 120 120 ns CS to WR Hold Time i 0 0) 0 ns WR to BUSY Propagation Delay t4 85 120 100 = 140 115 160 ns BUSY to CS Setup Time 15 (Note 3) 0 _ 0 0 ns CS to RD Setup Time te 0 O 0 ns RD Pulse Width 7 120 120 120 ns CS to RD Hold Time tg _ | 0 0 _ 0 ns BYSL to RD Setup Time to 50 50 50 ns BYSL to RD Hold Time tio 0 0 0 ns RD to Valid Data(Note7) | tir FE Rooess 60 100 70 110 90 130 | ns AD to Three-State Output (Bus Relinguish : ) < | | (Note 8) tie Time) 20 100 20 100 20 100 | ns WR to CLK for 16 Clock Conversions (Note 9) 43 r 20 20 __ 20 ns | WR to CLK for 17 Clock | Conversions (Note 9) ha 20 : 20 20 | NS Note 6: Data is timed from Vor, Vor; all input control signals are timed from a voltage level of +1.6V and specified with t- - bo = 20ns (10% to 90% of +5V). Note 7: ti1, the time required for an output to cross 0.8V or 2.4V, is measured with the load circuits of Figure 3 Note 8: ti, the time required for the data lines to change 0.5V. is measured with the load circuits of Figure 4 Note 9: See Figure 7. Figure 7: 4 Start Cycle Timing MAXICalibrated 12-Bit ADC with T/H and Reference Busy Ltn HIGH IMPEDANCE DATA ( LOW-BYTE DATA NOTE: THE 2 BYTE CONVERSION RESULT CAN BE READ IN EITHER ORDER THIS FIGURE IS FOR | OW-BYTE. HIGH-BYIE ORDER. IF BYSL CHANGES WHILE CS AND RD ARE LOW. DATA WILL CHANGE 10 REFLECT THF BYSL INPUT ( HIGH-BYIF DATA Figure 2. Read Cycle Timing Pin Description ' jpn! NAME | Function =) IN| NAME | FUNCTION | 1 | Caz i! 146 Auto-Zero Capacitor Input. Connect Ro |READ Input. Used with CS to enable + oe ____| other end of capacitor to AGND. | | the three-state data outputs. RD is | 2 AIN Analog Input f [active low 3 1) Ne! -! NoConnect ~ Sl faz cs jCHIP SELECT Input. Used with either - - S oT RD or WR for control. CS is active low. | 4 | REFIN Voltage Reference Input. The L =f Se were ee a | MAX178 is specified with REFIN = 18 WR WRITE Input. tn combination with CS | 45V. | this active low signal starts a new | SoS SS He 7" conversion 5 | AGND Analog Ground _ _ + ave, | | - 7 = STOTT 19 BYSL BYTE SELECT. BYSL selects high- or 6 | _OGND | DigitalGround |low-byte output during a data READ | 7 | Vee T Logic Supply. Digital inputs and | | | | oPeration. (RD. CS low). See pins | | | outputs are TTL compatible for TB AS. ee |. voce 20 BUSY | Converter Status. BUSY is only low | 8-15 | DBO-DB7 | Three-State Data Outputs. Active | | + oe uring conversion. | | | when CS and RD are brought low. | 24 CLK CLOCK Input. Internal clock opera- | | Individual pin functions depend upon | | | tion, with this pin floating and [| BYTE SELECT(BYSLJinput. | | junloaded. Wypically results 1 (20s | ee conversion time (Figure 8}. This can DATA BUS OUTPUT, CS, RD = LOW be lowered by using an external 74HC _ _ _DATABUS OUTPUT, CS,RD=LOW _ | y using PIN | BYSL = HIGH | _ _ _BYSLsLOW fp | oo iret source (Figure 9) 8 BUSY (Note 10) DB7 LL . 22 | REFOUT | Reference Output | 9 q LOW (Note 11) DBO a 23 | _ Vss_ ; | Negative Supply Voltage. -5V | 10 | LOW (Note 11) | DBS | 24 | Yoo ___| Positive Supply Voltage, + 15V | M [Low (Note 11) ao ee | Note 10: High during a conversion. BUSY is a converter stalus flag. te | DBI (MSB) DBS _- -- -- Fe er | Note 11: When BYSL is high. pins 9-11output a logic low. The [ 13 DB10 DB2 _ | 12-bit digital result is in DBO-DB11. DBI is the MSB fa BO Bt 15! DB8 DBO (LSB) : BP BB | RRL SB) 4 MAAAIs/w SZEXVINMAX178 Calibrated 12-Bit ADC with T/H and Reference Detailed Operation Operating Information Figure 5 shows an operational diagram for the MAX178. The only required passive components are a hold capacitor (CAZ) and a reference bypass capacitor and resistor. Indi- vidual pin functions are listed in the Pin Description table. On-Chip Clock Operation The on-chip oscillator requires no external components. Therefore, the CLK pin can be left unconnected resulting in atypical 120us conversion time. The conversion time can be increased by adding acapacitive load on the CLK pin. The timing diagrams in Figures 6 and 7 show the resulting tracking duration for relative positions of WR and CLK. Figure 8 is a schematic for on-chip clock operation. Anew conversion is initiated by bringing WR low, with CS low. This starts a track acquisition sequence. In this state, the T/H goes into track mode. Capacitor CAZ charges to the analog input voltage minus the input offset voltage of the comparator. Note: when WR is low (with CS low), the MAX182 is in track mode. When WR goes high, tracking time is extended by another 4 to 5 clock periods (4clock periods beginning with the first falling clock edge following the rising edge of WR). 16 to 17 clock periods are required for each conversion (Figure 7) BV 4 ak BN e beN. = * KS =p 100pF = 100pF L | pGND ~ DGND HIGH-2 T0 Vow HIGH-2 0 Vow Figure 3. Load Circuits for Access Time Test (t1:) OV > ke DBN z + DeN + = 3k T 10pF | 10pF ~ DCND > DGND VoH TO HIGH Z Vou TO HIGH-Z Figure 4. Load Circuits for Output Three-State Delay Test (t:2) 8 The MAX178 is in track mode between conversions when BUSY is high. After the tracking sequence, the most significant bit (MSB) decision is made. Following this, the remaining 11 bits are digitized on successive clock cy- cles, as indicated in Figure 6. The WR pulse need not be synchronized with the internal clock. External Clock Operation For external clock operation, drive the CLK input with a 74HC compatible clock source (Figure 9) The MAX178 automatically tracks for the appropriate time by means of an on-chip counter. Both WR and CS must be low to initiate a new conversion. Whenever WR and CS are low, the chip enters into track mode until WR or CS rises. After the rising edge of WR, the next falling edge of the clock starts a counter, which extends the tracking time by 4 to 5 external clock periods The analog input acquisition is complete at the end of the tracking period, and the signal is stored in the internal track-and-hold. The external clock source need not be synchronized with the WR pulse. Reading Data The 12-bit result of a conversion plus the converter status flag are accessible over an 8-bit data bus. The data is available from the MAX178 in right-justified format (the least significant bit (LSB) is the right-most bit in a 16-bit word). Two byte sized read operations are needed. The Byte Select (BYSL) input determines which byte is to be read first, 8LSBs or 4MSBs plus status flag. It is necessary to wait for the end of a conversion to obtain valid 12-bit data from the MAX178's successive approx- CAZ A7nt o4 ALOG INPUT ) . me AN wee eM | CAL An Axiant, eV ne lo REFERRED f= JAIN MAXI78 Vos]. 5Y wy 10 RD \ ea TNC REFQUT F4 Ww 5 RETIN oer og STANLE 12 b 2 AGND BUSY BUEPUL 19 tf ; DGNO BYSI 8 , EN as i we ov al ee WAY TS CONTROL - BUSY/DB7 es] 44 { INPUTS ) 7 (yDB6 RO} . o/s opaiono 3 " oyopa opoioe1 uP 8 Bu | DATABUS i | j [pers DB 10/08? | Ww Figure 5. MAX178 Operational Diagram MIAXKI/WVICalibrated 12-Bit ADC with T/H and Reference ay | we LU rrackg e" * f f SB) rn oer DBI0 =DB9 DB8 DB/ DB6 DBS DB4 DB3 NB? = DBs DBO ( TRACKING ~ (1 SB} Figure 6. MAX178 Timing Diagram imation register (SAR). If a read operation instruction is performed during a conversion, the MAX178 will dump the existing contents of the SAR onto the data bus. There are three methods to ensure correct operation: 1. Insert a software delay longer than the ADC con- version time between the conversion start and the data read operations. 2. The BUSY output is low during the conversion and high at the conversion end. Use this signal as an interrupt to the uP. 3. Poll the converter status flag, BUSY, at user-de- fined intervals after a conversion start. The status flag is available on DB7 during a high-byte READ The flag is the left-most bit and can be shifted directly into the pPs carry flag for testing. BUSY is high during a conversion. A write operation to the MAX178 during a conversion restarts the conversion. a TRACKING =MSB DECISION we 4 ee l1g = t14= 20ns MIN ve MSB DECISION} Application Hints Auto-Zero Capacitor (CAZ) CAZ (Figure 5) must be a low-leakage, low-dielectric absorption capacitor such as polypropylene, polysty- rene, or teflon. Connect the outside foil of CAZ to AGND to minimize noise. CAZ should be 4,700pF Clock Figure 10 shows typical conversion time versus temper- ature when using the MAX178's on-chip clock. Due to variations in manufacturing, the actual operating fre- quency can differ from chip-to-chip by up to 20%. For this reason, itis suggested that an external clock be used when fixed conversion times are required Analog Inputs The high-impedance analog input, AIN, allows simple analog interfacing. Signal sources from OV to +5V may be connected directly to AIN without extra buffering for source impedances up to 5kQ (Figure 11). The input/out- put (I/O) transfer characteristic and transition points for this input signal *ange are demonstrated in Figure 12 and Table 1. The M X178 transfer characteristic has transi- MAAXLAN MAX178 21 NO CONNECTION GLK TO CLK Figure 7. Width of Tracking Interval as a Function of WR Rising Edge Timing with Respect to CLK Falling Edge MAXAIWI Figure 8. Internal Clock Operation SZELXVINMAX178 Calibrated 12-Bit ADC with T/H and Reference tion points designed to occur on integer multiples of 1LSB. The output code is natural binary with: 1LSB = (Full Scale (FS))/4096 = (5/4096)V = 1.22mvV. For signal ranges other than OV to +5V, use resistor divider networks to provide OV to +5V signal ranges at the MAX178 input pins. The connection in Figure 13 shows a divider network for a OV to +10V signal range. Resistors should be of the same type and manufacturer to ensure matched temperature coefficients. The source impedance must now be as low as possible since it adds to the resistor divider impedance. Figure 14 shows how bipolar signals -5V to +5V are accommodated by referencing the resistor divider net- work to REFIN. The signal source must be capable of sinking 0.5mA with the resistor values shown. Refer to Figure 15 and Table 2 for the I/O transfer characteristic and transition points for this signal range. Output coding is offset binary with an LSB size of: (FS)(1/4096) = (10/4096)V = 2.44mV To adjust bipolar zero error, apply 1.22mV (+ 1/2LSB) to AIN and adjust the offset of A1 so that the ADC output switches between 1000 0000 0000 and 1000 C000 0001. Power-Supply Decoupling Power supplies to the MAX178 should be bypassed with either a 10uF electrolytic or tantulum capacitor in parallel with a 0.01uF disc ceramic capacitor for clean, high- frequency performance. Place all capacitors as close as possible to the MAX178 supply pins. Rs Ay AIN Vs 2) Vs OVTO -5V WIT 74HC Slo VS * MAX178 COMPATIBLE j 24} CLK I CLOCK SOURCE maxm 5 - _ AGND MAX178 Re <5 t " DGND Figure 11. Unipolar OV to +5V Operation Figure 9. External Clock Operation WA | 105 11.110 a | = 10 = 11.101 2 a & uu a oS = < 1 18 a = o.on Ss S yi a a 102 a 00 010 + = we s 5 a FS BY Sig. a 00.00: + ISB. FS#096 a 100 To 00.00 -- - fF | Yt 5 25 0 25 507100195 OV 11SB 2LSB 3ISB- --FS-2LSB FS 11S8B TEMPERATURE C} ANALOG INPLIT Figure 10. Typical Change in Conversion Time Variation Figure 12. Ideal Input/Output Transfer Characteristic for vs. Temperature when Using Internal Clock Unipolar Circuit of Figure 11 MAXILSVIinternal Reference The internal reference (REFOUT) should be bypassed with a 1Q resistor in series with a capacitor. The capac- itor should be a 10uF electrolytic or tantalum in parallel with a 0.01pF disc ceramic (Figure 16). Figure 17 snows a circuit that allows input adjustment which is useful for trimming out initial (room temperature) error in the refer- ence voltage. Table 1. Transition Points for Unipolar OV to +5V Operation Analog Input (V) Digital Output 0.00122 0.00244 2.49878 2,50000 2.50122 4.99756 4.99878 0000 6000 0001 0000 0000 0010 O111 1147 4444 1000 0000 0000 1000 9000 0001 Table 2. Transition Points for Bipolar -5V to +5V Operation Analog Input (V) Digital Output Calibrated 12-Bit ADC with T/H and Reference External Reference Circuit Figure 18 shows how to set up a MX584LH to generate a reference voltage of 5.00V. Atypical adjustment range of 75mV is provided by R2. Over the commercial tem- perature range, the MX584LH contributes no more than +1LSB of gain error. During a conversion, transient currents flow at the REFIN input. To prevent dynamic errors, place either a 10uF electrolytic or tantalum smoothing capacitor in parallel with a 0.01nF disc ceramic from the REFIN pin to AGND. -4.99878 -4.99634 -0.00122 +0,00122 +4,99389 +4,99634 0000 0000 0001 0000 9000 0010 1000 0000 0000 1000 0000 0001 MAXAI/VI 0.01% AN 2d ain > 10k AL MAXLAN 001% MAX176 5 f + AGND Figure 13. Unipolar OV to + 10V Operation RFFIN BV AP an _ [ I RL 10k 2 ~_waxao0 oom: | a a Tan EO) ve SvTO sv LY 5 _ . T AND Figure 14. Bipolar -5V to +5V Operation SZEXVINMAX178 Calibrated 12-Bit ADC with T/H and Reference Layout When designing layout for a printed circuit board, keep digital and analog signal lines separated whenever pos- sible. It is critical that no digital line runs alongside an analog signal line or near the CAZ. Guard the analog inputs, the reference input and the CAZ input with AGND. Establish a single-point analog ground (AGND) as close to the MAX178 as possible, isolated from the logic sys- tem. Connect the single-point analog ground to the digital systern ground, which is attached to DGND at one point, as close as possible to the MAX178. The following should be returned to the analog ground point: input-sig- nal common, input guards, the CAZ, and any bypass capacitors for the reference input and the analog sup- plies. Low-impedance analog and digital power-supply common returns, with wide trace widths, are essential for quiet operation of the MAX178 11.111 | 111110 | 100 .010 | joo.oo1 - =fS -1/2LSB [ 100.000 -, - | | a +FS On = "pousB * 1188 011.110 | rl 000.001 ~, S-t0V 000.000 {7 1LSB ~FS/4096 ov ANALOG INPUT Figure 15. Ideal Input/Output Transfer Characteristic for Bipolar Circuit of Figure 14 Noise To minimize input noise coupling, input signal leads to AIN and signal return leads from AGND should be kept as short as possible. A shielded cable between source and ADC is suggested in applications where longer leads are required. Also, care should be taken to reduce ground circuit impedances as much as possible since any potential difference in grounds between the signal source and ADC creates an error voltage in series with the input signal When interfacing to continuously busy and noisy pP buses, it is possible to get errors at the LSB level. These errors exist because of feedthrough from the bus to the integrated circuit through the package. The problem can be minimized in ceramic packaged chips by grounding the metal lid. Another solution is to isolate the MAX178 from the noisy uP bus using three-state buffers Figure 17. Adjusting Analog Input Gain to Trim Out Initial Refer- ence Voltage Error ) ANAXLMA MAX178 4 22 12 REFIN REFOUT F-- A/V gt TOF AS = O.01pr ] Figure 16. Internal Reference Hookup. Note: Reference Value Is Not Adjustable. 10 2 TY A 24 Vip O.0inr 7] amaxnaa | 1 19 00OV 4 REFIN CER) | xsd | > J re? | | 6] 3 10k . AAAXIAN Po AAA wet 10h iM TANT | MAX 178 4 Rt 5 > AGN Figure 18. MX584LH as Reference Generator MAXILWVICalibrated 12-Bit ADC with T/H and Reference Chip Topography 0.160" AGND DGND oa (3.40 mm) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time MAXAIL/VI ou SZLXVW