FUNCTIONAL BLOCK DIAGRAM 2 GND 3 ATTIN 4 PS LE 14 13 SERIAL/ PARALLEL INTERFACE 4-BIT DIGITAL ATTENUATOR 5 6 7 12 VDD 11 VSS 10 GND 9 ATTOUT 8 PACKAGE BASE 16999-001 D5/CLK 15 GND 1 16 GND D4/SERIN D2 ADRF5721 D3/SEROUT Ultrawideband frequency range: 9 kHz to 40 GHz Attenuation range: 2 dB steps to 30 dB Low insertion loss 1.6 dB to 18 GHz 2.0 dB to 26 GHz 3.4 dB to 40 GHz Attenuation accuracy (0.1 + 1.0%) of attenuation state up to 18 GHz (0.1 + 2.5%) of attenuation state up to 26 GHz (0.6 + 10.0%) of attenuation state up to 40 GHz Typical step error 0.15 dB to 18 GHz 0.20 dB to 26 GHz 0.60 dB to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 26 dBm IP3: 50 dBm typical High RF input power handling: 26 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency switching spurs SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 8.5 s 2.5 mm x 2.5 mm, 16-terminal LGA package Pin compatible with ADRF5731, fast switching version GND FEATURES GND Data Sheet 2 dB LSB, 4-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz ADRF5721 Figure 1. APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5721 is a silicon, 4-bit digital attenuator with a 30 dB attenuation control range in 2 dB steps. semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls. This device operates from 9 kHz to 40 GHz with better than 3.4 dB of insertion loss. The ATTIN port of the ADRF5721 has a radio frequency (RF) input power handling capability of 26 dBm average and 30 dBm peak for all states. The ADRF5721 is pin compatible with the ADRF5731, the fast switching version, which operates from 100 MHz to 40 GHz. The ADRF5721 requires a dual supply voltage of +3.3 V and -3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide The ADRF5721 comes in a 16-terminal, 2.5 mm x 2.5 mm, RoHS compliant, land grid array (LGA) package and operates from -40C to +105C. Rev. A The ADRF5721 RF ports are designed to match a characteristic impedance of 50 . Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5721 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase ................................................................................8 Functional Block Diagram .............................................................. 1 Input Power Compression and Third-Order Intercept ......... 10 General Description ......................................................................... 1 Theory of Operation ...................................................................... 11 Revision History ............................................................................... 2 Power Supply............................................................................... 11 Specifications..................................................................................... 3 RF Input and Output ................................................................. 11 Electrical Specifications ............................................................... 3 Serial or Parallel Mode Selection ............................................. 12 Timing Specifications .................................................................. 5 Serial Mode Interface ................................................................. 12 Absolute Maximum Ratings ....................................................... 6 Parallel Mode Interface .............................................................. 13 Thermal Resistance ...................................................................... 6 Applications Information .............................................................. 14 Power Derating Curves ................................................................ 6 Evaluation Board ........................................................................ 14 ESD Caution .................................................................................. 6 Probe Matrix Board ................................................................... 16 Pin Configuration and Function Descriptions ............................. 7 Packaging and Ordering Information ......................................... 17 Interface Schematics..................................................................... 7 Outline Dimensions ................................................................... 17 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 17 REVISION HISTORY 3/2020--Rev. 0 to Rev. A Changes to RF Power Parameter, Table 1 ...................................... 4 Changes to Table 3 ............................................................................ 6 Changes to Power Supply Section ................................................ 11 Added Power-Up State Section ..................................................... 11 Moved Serial or Parallel Mode Selection Section and Table 7; Renumbered Sequentially ......................................................................12 9/2018--Revision 0: Initial Version Rev. A | Page 2 of 17 Data Sheet ADRF5721 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V, VSS = -3.3 V, digital voltages = 0 V or VDD, case temperature (TCASE) = 25C, and a 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS (IL) RETURN LOSS ATTENUATION Range Step Size Accuracy Step Error RELATIVE PHASE SWITCHING CHARACTERISTICS Rise and Fall Time (tRISE and tFALL) On and Off Time (tON and tOFF) RF Amplitude Settling Time 0.1 dB 0.05 dB Overshoot Undershoot RF Phase Settling Time 5 1 Test Conditions/Comments 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz ATTIN and ATTOUT, all attenuation states 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 1.3 1.6 2.0 2.7 3.4 Unit MHz dB dB dB dB dB 20 19 17 17 16 dB dB dB dB dB Between minimum and maximum attenuation states Between any successive attenuation states Referenced to insertion loss 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz Between any successive attenuation states 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz Referenced to insertion loss 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz All attenuation states at input power (PIN) = 10 dBm 10% to 90% of RF output 50% triggered control (CTL) to 90% of RF output 30 2 dB dB (0.1 + 1.0%) (0.1 + 1.0%) (0.1 + 2.5%) (0.2 + 6.0%) (0.6 + 10%) dB dB dB dB dB 0.05 0.15 0.20 0.35 0.60 dB dB dB dB dB 17 26 37 53 77 Degrees Degrees Degrees Degrees Degrees 1.3 3.8 s s 8.5 11 1.5 -1.0 s s dB dB 2.2 3.5 s s 50% triggered CTL to 0.1 dB of final RF output 50% triggered CTL to 0.05 dB of final RF output f = 5 GHz 50% triggered CTL to 5 of final RF output 50% triggered CTL to 1 of final RF output Rev. A | Page 3 of 17 Min 0.009 Typ Max 40,000 ADRF5721 Parameter INPUT LINEARITY1 0.1 dB Power Compression (P0.1dB) Insertion Loss State Other Attenuation States Third-Order Intercept (IP3) DIGITAL CONTROL INPUTS Voltage Low (VINL) High (VINH) Current Low (IINL) High (IINH) DIGITAL CONTROL OUTPUT Voltage Low (VOUTL) High (VOUTH) Low and High Current (IOUTL, IOUTH) SUPPLY CURRENT Positive Negative RECOMMENDED OPERATING CONDITIONS Supply Voltage Positive (VDD) Negative (VSS) Digital Control Voltage RF Power3 Input at ATTIN Input at ATTOUT Data Sheet Test Conditions/Comments 500 kHz to 30 GHz Min Typ Max 30 26 50 Two-tone input power = 14 dBm per tone, f = 1 MHz, all attenuation states LE, PS, D2, D3/SEROUT,2 D4/SERIN, D5/CLK pins 0 1.2 D2 LE, PS, D3/SEROUT,2 D4/SERIN, D5/CLK pins D3/SEROUT pin2 Unit dBm dBm dBm 0.8 3.3 V V <1 33 <1 A A A 0 0.3 VDD 0.3 V V mA 0.5 VDD and VSS pins 117 -117 3.15 -3.45 0 3.45 -3.15 VDD V V V -40 26 30 24 27 18 21 15 18 +105 dBm dBm dBm dBm dBm dBm dBm dBm C f = 500 kHz to 30 GHz, TCASE = 85C,4 all attenuation states Steady state average Steady state peak Hot switching average Hot switching peak Steady state average Steady state peak Hot switching average Hot switching peak Case Temperature (TCASE) 1 Input linearity performance degrades over frequency (see Figure 20 and Figure 21). The D3/SEROUT pin is an input in parallel control mode and an output in serial control mode. See Table 5 for the pin function descriptions. For power derating over frequency, see Figure 2 and Figure 3. Applicable for all ATTIN and ATTOUT power specifications. 4 For 105C operation, the power handling degrades from the TCASE = 85C specifications by 3 dB. 2 3 Rev. A | Page 4 of 17 A A Data Sheet ADRF5721 TIMING SPECIFICATIONS See Figure 24, Figure 25, and Figure 26 for the timing diagrams. Table 2. Parameter tSCK tCS tCH tLN tLEW tLES tCKN tPH tPS tCO Description Minimum serial period, see Figure 24 Control setup time, see Figure 24 Control hold time, see Figure 24 LE setup time, see Figure 24 Minimum LE pulse width, see Figure 24 and Figure 26 Minimum LE pulse spacing, see Figure 24 Serial clock hold time from LE, see Figure 24 Hold time, see Figure 26 Setup time, see Figure 26 Clock to output (SEROUT) time, see Figure 25 Rev. A | Page 5 of 17 Min 70 15 Typ 20 15 10 630 0 10 2 20 Max Unit ns ns ns ns ns ns ns ns ns ns ADRF5721 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Table 4. Thermal Resistance Rating -0.3 V to +3.6 V -3.6 V to +0.3 V Package Type CC-16-6 -0.3 V to VDD + 0.3 V 3 mA POWER DERATING CURVES JC 100 Unit C/W 2 0 POWER DERATING (dB) -2 27 dBm 31 dBm 25 dBm 28 dBm 19 dBm 22 dBm 16 dBm 19 dBm -4 -6 -8 -10 -12 -16 1k 10k 100k 1M 10M 100M 1G 10G 100G FREQUENCY (Hz) 16999-002 -14 Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85C 21 dBm 15 dBm 2 0 135C -65C to +150C 260C 0.5 W -2 POWER DERATING (dB) 1500 V 2000 V 1250 V -4 -6 -8 -10 -12 -14 -16 26 1 For power derating over frequency, see Figure 2 and Figure 3. Applicable for all ATTIN and ATTOUT power specifications. 2 For 105C operation, the power handling derates from the TCASE = 85C specifications by 3 dB. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 28 30 32 34 36 38 40 42 FREQUENCY (GHz) 44 46 48 50 16999-003 Parameter Positive Supply Voltage (VDD) Negative Supply Voltage (VSS) Digital Control Inputs Voltage Current RF Power1 (f = 500 kHz to 30 GHz, TCASE = 85C2) Input at ATTIN Steady State Average Steady State Peak Hot Switching Average Hot Switching Peak Input at ATTOUT Steady State Average Steady State Peak Hot Switching Average Hot Switching Peak RF Power Under Unbiased Condition (VDD, VSS = 0 V) Input at ATTIN Input at ATTOUT Temperature Junction (TJ) Storage Reflow Continuous Power Dissipation (PDISS) Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) ATTIN and ATTOUT Pins Digital Pins Charged Device Model (CDM) Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85C ESD CAUTION THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JC is the junction to case bottom (channel to package bottom) thermal resistance. Rev. A | Page 6 of 17 Data Sheet ADRF5721 PS LE 15 14 13 1 ATTIN 4 ADRF5721 TOP VIEW (Not to Scale) 5 6 7 8 GND 3 GND 2 GND GND D5/CLK 12 VDD 11 VSS 10 GND 9 ATTOUT NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO THE RF AND DC GROUND OF THE PCB. 16999-004 D2 16 GND D4/SERIN D3/SEROUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic D4/SERIN 2 D5/CLK 3, 5 to 8, 10 4 GND ATTIN 9 ATTOUT 11 12 13 14 VSS VDD LE PS 15 16 D2 D3/SEROUT 17 EPAD Description Parallel Control Input for 8 dB Attenuator Bit (D4). Serial Data Input (SERIN). See the Theory of Operation section for more information. Parallel Control Input for 16 dB Attenuator Bit (D5). Serial Clock Input (CLK). See the Theory of Operation section for more information. Ground. These pins must be connected to the RF and dc ground of the PCB. Attenuator Input. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is needed when the RF line potential is equal to 0 V dc. Attenuator Output. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is needed when the RF line potential is equal to 0 V dc. Negative Supply Input. Positive Supply Input. Latch Enable Input. See the Theory of Operation section for more information. Parallel or Serial Control Interface Selection Input. See the Theory of Operation section for more information. Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information. Parallel Control Input for 4 dB Attenuator Bit (D3). Serial Data Output (SEROUT). See the Theory of Operation section for more information. Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB. INTERFACE SCHEMATICS VDD VDD LE, PS, D3/SEROUT, D4/SERIN, D5/CLK 16999-005 D2 100k 16999-006 Figure 5. Digital Input Interface Schematic for LE, PS, D3/SEROUT, D4/SERIN, and D5/CLK ATTIN, ATTOUT VDD Figure 6. ATTIN and ATTOUT Interface Schematic Rev. A | Page 7 of 17 16999-007 VDD Figure 7. Digital Input Interface Schematic for D2 ADRF5721 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE 0 0 -1 -5 -2 -10 -3 OUTPUT RETURN LOSS (dB) -40C +25C +85C +105C -4 -5 -6 -7 -8 STATE 2dB STATE 8dB STATE 30dB -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) -50 16999-008 -10 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) Figure 8. Insertion Loss vs. Frequency over Temperature 16999-011 -45 -9 Figure 11. Output Return Loss vs. Frequency (Major States Only) 0 1.5 -5 1.0 -10 STEP ERROR (dB) NORMALIZED ATTENUATION (dB) STATE 0dB STATE 4dB STATE 16dB -15 -20 -25 0.5 0 -0.5 STATE 0dB STATE 4dB STATE 16dB -1.0 -30 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) -1.5 16999-009 -35 STATE 2dB STATE 8dB STATE 30dB 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) Figure 9. Normalized Attenuation vs. Frequency for All States at Room Temperature 16999-012 INSERTION LOSS (dB) VDD = 3.3 V, VSS = -3.3 V, digital voltages = 0 V or VDD, TCASE = 25C, and a 50 system, unless otherwise noted. Measured on probe matrix board using ground signal ground (GSG) probes close to the RF pins (ATTIN and ATTOUT). See the Applications Information section for details on evaluation and probe matrix boards. Figure 12. Step Error vs. Frequency (Major States Only) 0 1.5 -5 1.0 -20 -25 -30 -35 -40 STATE 0dB STATE 4dB STATE 16dB -45 STATE 2dB STATE 8dB STATE 30dB 5 10 15 20 25 30 35 40 0 -0.5 5GHz 20GHz 35GHz -1.0 -50 0 0.5 45 FREQUENCY (GHz) Figure 10. Input Return Loss vs. Frequency (Major States Only) -1.5 0 2 4 6 8 10GHz 25GHz 40GHz 15GHz 30GHz 45GHz 10 12 14 16 18 20 22 24 26 28 30 ATTENUATION STATE Figure 13. Step Error vs. Attenuation State over Frequency Rev. A | Page 8 of 17 16999-013 STEP ERROR (dB) -15 16999-010 INPUT RETURN LOSS (dB) -10 Data Sheet 9 ADRF5721 STATE 0dB STATE 4dB STATE 16dB 8 100 STATE 2dB STATE 8dB STATE 30dB 6 5 4 3 2 1 70 60 50 40 30 20 10 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) 0 16999-014 0 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) 16999-016 0 -1 Figure 16. Relative Phase vs. Frequency (Major States Only) Figure 14. State Error vs. Frequency (Major States Only) 100 9 8 5GHz 20GHz 35GHz 10GHz 25GHz 40GHz 5GHz 20GHz 35GHz 90 15GHz 30GHz 45GHz RELATIVE PHASE (Degrees) 7 6 5 4 3 2 1 10GHz 25GHz 40GHz 15GHz 30GHz 45GHz 80 70 60 50 40 30 20 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 ATTENUATION STATE Figure 15. State Error vs. Attenuation State over Frequency 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 ATTENUATION STATE Figure 17. Relative Phase vs. Attenuation State over Frequency Rev. A | Page 9 of 17 16999-017 10 0 16999-015 STATE ERROR (dB) STATE 2dB STATE 8dB STATE 30dB 80 RELATIVE PHASE (Degrees) STATE ERROR (dB) 7 -1 STATE 0dB STATE 4dB STATE 16dB 90 ADRF5721 Data Sheet 35 30 30 25 25 20 15 10 STATE 0dB STATE 4dB STATE 16dB 5 STATE 2dB STATE 8dB STATE 30dB 15 10 STATE 0dB STATE 4dB STATE 16dB 5 STATE 2dB STATE 8dB STATE 30dB 0 0 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 20. Input P0.1dB vs. Frequency (Major States Only), Low Frequency Detail Figure 18. Input P0.1dB vs. Frequency (Major States Only) 80 70 70 60 60 50 50 INPUT IP3 (dBm) 80 40 30 40 30 20 STATE 0dB STATE 4dB STATE 16dB 10 STATE 2dB STATE 8dB STATE 30dB STATE 0dB STATE 4dB STATE 16dB 10 STATE 2dB STATE 8dB STATE 30dB 0 0 0 5 10 15 20 25 30 35 FREQUENCY (GHz) Figure 19. Input IP3 vs. Frequency (Major States Only) 40 10k 100k 1M 10M 100M 1G 16999-021 20 16999-019 INPUT IP3 (dBm) 20 16999-020 INPUT P0.1dB (dBm) 35 16999-018 INPUT P0.1dB (dBm) INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT FREQUENCY (Hz) Figure 21. Input IP3 vs. Frequency (Major States Only), Low Frequency Detail Rev. A | Page 10 of 17 Data Sheet ADRF5721 THEORY OF OPERATION The ADRF5721 incorporates a 4-bit fixed attenuator array that offers an attenuation range of 30 dB in 2 dB steps. An integrated driver provides both serial and parallel mode control of the attenuator array (see Figure 22). 4. The power-down sequence is the reverse order of the power-up sequence. Note that when referring to a single function of a multifunction pin in this section, only the portion of the pin name that is relevant is mentioned. For full pin names of the multifunction pins, refer to the Pin Configuration and Function Descriptions section. Power-Up State The ADRF5721 has internal power-on reset circuity. This circuity sets the attenuator to the maximum attenuation state (30 dB) when the VDD and VSS voltages are applied and LE is set to low. POWER SUPPLY RF INPUT AND OUTPUT Bypassing capacitors are recommended on the positive supply voltage line (VDD) and negative supply line (VSS) to filter high frequency noise. Both RF ports (ATTIN and ATTOUT) are dc-coupled to 0 V. DC blocking is not required at the RF ports when the RF line potential is equal to 0 V. The power-up sequence is as follows: The RF ports are internally matched to 50 . Therefore, external matching components are not required. 1. 2. Connect GND. Power up the VDD and VSS voltages. Power up VSS after VDD to avoid current transients on VDD during ramp-up. 3. Power up the digital control inputs. The order of the digital control inputs is not important. However, powering the digital control inputs before the VDD voltage supply may inadvertently forward bias and damage the internal ESD structures. To avoid this damage, use a series 1 k resistor to limit the current flowing in to the control pin. Use pullup or pull-down resistors if the controller output is in a Table 6. Truth Table D5 Low Low Low Low High High D3 Low Low High Low Low High The ADRF5721 supports bidirectional operation at a lower power level. The power handling of the ATTIN and ATTOUT ports are different. Therefore, the bidirectional power handling is defined by the ATTOUT port. Refer to the RF input power specifications in Table 1. Digital Control Input1 D2 D1 Low Don't care High Don't care Low Don't care Low Don't care Low Don't care High Don't care Attenuation State (dB) 0 (reference) 2 4 8 16 30 D0 Don't care Don't care Don't care Don't care Don't care Don't care Any combination of the control voltage input states shown in Table 6 provides an attenuation equal to the sum of the bits selected. D2 SERIN D Q D Q D Q D3 D Q D4 D Q D5 D Q D Q D Q SEROUT CLK PS PARALLEL OR SERIAL SELECT LE 6-BIT OR 8-BIT LATCH RF INPUT 2dB 4dB 8dB Figure 22. Simplified Circuit Diagram Rev. A | Page 11 of 17 16dB RF OUTPUT 16999-022 1 D4 Low Low Low High Low High high impedance state after the VDD voltage is powered up and the control pins are not driven to a valid logic state. Apply an RF input signal to ATTIN or ATTOUT. ADRF5721 Data Sheet SERIAL OR PARALLEL MODE SELECTION Using SEROUT The ADRF5721 can be controlled in either serial or parallel mode by setting the PS pin to high or low, respectively (see Table 7). The ADRF5721 also features a serial data output, SEROUT. SEROUT outputs the serial input data at the eighth clock cycle, and can control a cascaded attenuator using a single SPI bus. Figure 25 shows the serial output timing diagram. Table 7. Mode Selection Control Mode Parallel Serial When using the attenuator in a daisy-chain operation, 8-bit SERIN data must be used due to the 8-clock cycle delay between SERIN and SEROUT. SERIAL MODE INTERFACE It is optional to use a 1 k resistor between SEROUT on the first attenuator and SERIN of the next attenuator to filter the signal (see Figure 23). The ADRF5721 supports a 3-wire SPI: serial data input (SERIN), clock (CLK), and latch enable (LE). The serial control interface is activated when PS is set to high. 4 The ADRF5721 attenuation state is controlled by Bits[D5:D2]. Bit D0 and Bit D1 are don't care bits but must be input. Therefore, at least a 6-bit SERIN must be used to control the attenuation states. If using an 8-bit word to control the state of the attenuator, Bits[D7:D6] and Bits[D1:D0] are don't care bits. It does not matter if these bits are held low or high. Refer to Table 6 and Figure 24 for additional information. VOLTAGE (V) 3 2 In serial mode, the SERIN data is clocked most significant bit (MSB) first on the rising CLK edges into the shift register. Then, LE must be toggled high to latch the new attenuation state into the device. LE must be set to low to clock new SERIN data into the shift register as CLK is masked to prevent the attenuator value from changing if LE is kept high. See Figure 24 in conjunction with Table 2 and Table 6. PS SERIN [FIRST IN] OPTIONAL OPTIONAL X X D7 MSB D6 tCS D5 1 0 D4 D3 0 50 100 150 200 250 300 350 400 450 500 TIME (ns) Figure 23. Using a Resistor on SEROUT LSB tCH WITHOUT 1k WITH 1k 16999-023 PS Low High [LAST IN] DON'T CARE DON'T CARE D2 D1 D0 D[7:0] NEXT WORD X tLN tLEW X tCKN tSCK 16999-024 CLK tLES LE Figure 24. Serial Control Timing Diagram PS SERIN X X D5 1 D4 2 D3 D2 D1 D0 3 4 5 6 X 7 8 9 10 11 12 13 14 CLK SEROUT X D5 tCO Figure 25. Serial Output Timing Diagram Rev. A | Page 12 of 17 D4 D3 D2 D1 D0 X 16999-025 LE Data Sheet ADRF5721 PARALLEL MODE INTERFACE Latched Parallel Mode The ADRF5721 has four digital control inputs, D2 (LSB) to D5 (MSB), to select the desired attenuation state in parallel mode, as shown in Table 6. The parallel control interface is activated when PS is set to low. To enable latched parallel mode, keep the LE pin low when changing the control voltage inputs (D2 to D5) to set the attenuation state. When the desired state is set, toggle LE high to transfer the 4-bit data to the bypass switches of the attenuator array, and then toggle LE low to latch the change into the device until the next desired attenuation change (see Figure 26 in conjunction with Table 2). There are two modes of parallel operation: direct parallel and latched parallel. Direct Parallel Mode PS X tPS D5 TO D2 tPH X X tLEW LE 16999-026 To enable direct parallel mode, keep the LE pin high. To change the attenuation state, use the control voltage inputs (D2 to D5) directly. This mode is ideal for manual control of the attenuator. Figure 26. Latched Parallel Mode Timing Diagram Rev. A | Page 13 of 17 ADRF5721 Data Sheet APPLICATIONS INFORMATION 0 EVALUATION BOARD W = 16mil 1.5oz Cu (2.2mil) G = 6mil 1.5oz Cu (2.2mil) H = 12mil -3 -4 -5 -6 THRU LOSS DE-EMBEDDED INSERTION LOSS EMBEDDED INSERTION LOSS -7 -8 0.5oz Cu (0.7mil) -10 0 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 Figure 28. Insertion Loss vs. Frequency 0.5oz Cu (0.7mil) 1.5oz Cu (2.2mil) 5 16999-028 -9 16999-027 TOTAL THICKNESS ~62mil RO4003 1.5oz Cu (2.2mil) T = 2.2mil -2 INSERTION LOSS (dB) The ADRF5721-EVALZ is a 4-layer evaluation board. The top and bottom copper layer are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil) and are separated by dielectric materials. The stackup for this evaluation board is shown in Figure 27. -1 Figure 29 shows the actual ADRF5721-EVALZ evaluation board with component placement. All RF and dc traces are routed on the top copper layer, whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. The top dielectric material is 12 mil Rogers RO4003, offering optimal high frequency performance. The middle and bottom dielectric materials provide mechanical strength. The overall board thickness is 62 mil, which allows 2.4 mm RF launchers to be connected at the board edges. The RF transmission lines are designed using a coplanar waveguide (CPWG) model, with a trace width of 16 mil and ground clearance of 6 mil to have a characteristic impedance of 50 . For optimal RF and thermal grounding, as many through vias as possible are arranged around transmission lines and under the exposed pad of the package. Thru calibration can be used to calibrate out the board loss effects from the ADRF5721-EVALZ evaluation board measurements to determine the device performance at the pins of the IC. Figure 28 shows the typical board loss (THRU) for the ADRF5721-EVALZ evaluation board at room temperature, the embedded insertion loss, and the de-embedded insertion loss for the ADRF5721. 16999-029 Figure 27. Evaluation Board Stackup, Cross Sectional View Figure 29. Evaluation Board Layout, Top View Two power supply ports are connected to the VDD and VSS test points, TP1 and TP2, and the ground reference is connected to the GND test point, TP4. On the supply traces, VDD and VSS, use a 100 pF bypass capacitor to filter high frequency noise. Additionally, unpopulated components positions are available for applying extra bypass capacitors. All the digital control pins are connected through digital signal traces to the 2 x 9-pin header, P1. There are provisions for a resistor capacitor (RC) filter that helps eliminate dc-coupled noise. The ADRF5721 was evaluated without an external RC filter, the series resistors are 0 , and shunt capacitors are unpopulated on the evaluation board. The RF input and output ports (ATTIN and ATTOUT) are connected through 50 transmission lines to the 2.4 mm RF launchers, J1 and J2, respectively. These high frequency RF launchers are connected by contact and are not soldered onto the board. A thru calibration line connects the unpopulated J3 and J4 launchers. This transmission line is used to estimate the loss of the PCB over the environmental conditions being evaluated. The schematic of the ADRF5721-EVALZ evaluation board is shown in Figure 30. Rev. A | Page 14 of 17 Data Sheet ADRF5721 P1 D2 R6 R1 PS 0 0 R2 LE R5 D3_SEROUT 0 4 13 LE 14 PS 15 D2 VSS D5/CLK ADRF5721 GND GND 12 C2 100pF GND TP4 10 ATTOUT J3 DNI J2 THRU CAL J4 DNI 16999-030 5 VSS TP2 2 6 4 8 10 12 14 16 18 11 ATTOUT 9 ATTIN GND ATTIN 3 GND J1 2 VDD TP1 C1 100pF VDD 8 0 D4/SERIN GND R3 D5_CLK 1 7 R4 0 GND D4_SERIN EPAD 6 17 D3/SEROUT 16 0 D5_CLK 1 D4_SERIN 3 D3_SEROUT 5 7 D2 PS 9 11 LE 13 15 17 Figure 30. Evaluation Board Schematic Table 8. Evaluation Board Components Component C1, C2 J1, J2 P1 R1 to R6 TP1, TP2, TP4 U1 Default Value 100 pF Not applicable Not applicable 0 Not applicable ADRF5721 Description Capacitors, C0402 package 2.4 mm end launch connectors (Southwest Microwave: 1492-04A-6) 2 x 9-pin header Resistors, 0402 package Through hole mount test points ADRF5721 digital attenuator, Analog Devices, Inc. Rev. A | Page 15 of 17 ADRF5721 Data Sheet PROBE MATRIX BOARD The probe matrix board is a 4-layer board. Similar to the evaluation board, the probe matrix board also uses a 12 mil Rogers RO4003 dielectric. The top and bottom copper layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil). The RF transmission lines are designed using a CPWG model with a width of 16 mil and ground spacing of 6 mil to have a characteristic impedance of 50 . Figure 31 and Figure 32 show the cross sectional view and the top view of the board, respectively. Measurements are made using GSG probes at close proximity to the RF pins (ATTIN and ATTOUT). Unlike the evaluation board, probing reduces reflections caused by mismatch arising from connectors, cables, and board layout, resulting in a more accurate measurement of the device performance. 1.5oz Cu (2.2mil) G = 6mil 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) T = 2.2mil Figure 32. Probe Matrix Board Layout (Top View) H = 12mil The probe matrix board includes a thru reflect line (TRL) calibration kit, allowing board loss de-embedding. The actual board duplicates the same layout in matrix form to assemble multiple devices at one time. Figure 33 is a detailed image of the trace to pin transition with corresponding dimensions. All S parameters were measured on this board. 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) 1.5oz Cu (2.2mil) 16999-031 Figure 31. Probe Matrix Board (Cross Sectional View) 16mil 8mil 16999-033 16mil TOTAL THICKNESS ~62mil RO4003 16999-032 W = 16mil Figure 33. Probe Board Layout Dimensions (Top View) Rev. A | Page 16 of 17 Data Sheet ADRF5721 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS PIN 1 CORNER AREA 0.250 0.200 0.150 0.325 0.275 0.225 CHAMFERED PIN 1 (0.1 x 45) 16 13 12 1 1.20 REF 0.40 BSC TOP VIEW 0.850 0.750 0.650 SIDE VIEW 4 9 5 8 BOTTOM VIEW 0.125 REF 0.530 REF 0.260 0.220 0.180 PKG-005309 1.10 1.00 SQ 0.90 EXPOSED PAD FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 04-14-2017-A 2.60 2.50 SQ 2.40 Figure 34. 16-Terminal Land Grid Array [LGA] 2.5 mm x 2.5 mm Body and 0.75 mm Package Height (CC-16-6) Dimensions shown in millimeters ORDERING GUIDE Model1 ADRF5721BCCZN ADRF5721BCCZN-R7 ADRF5721-EVALZ 1 Temperature Range -40C to +105C -40C to +105C Package Description 16-Terminal Land Grid Array [LGA] 16-Terminal Land Grid Array [LGA] Evaluation Board Package Option CC-16-6 CC-16-6 Marking Code 21 21 Z = RoHS Compliant Part. (c)2018-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16999-3/20(A) www.analog.com/ADRF5721 Rev. A | Page 17 of 17