1 of 32 May 23, 2013
2013 Integrated Device Technology, Inc. DSC 6928
®
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Device Overview
The 89HPES16T4AG2 is a member of IDT’s PRECISE™ family of
PCI Express® switching solutions. The PES16T4AG2 is a 16-lane, 4-
port Gen2 peripheral chip that performs PCI Express Base switching
with a feature set optimized for high performance applications such as
servers, storage, and communications/networking. It provides connec-
tivity and switching functions between a PCI Express upstream port and
up to three downstream ports and supports switching between down-
stream ports.
Features
High Performance PCI Express Switch
Sixteen 5 Gbps Gen2 PCI Express lanes
Four switch ports
One x8 or x4 upstream port
Up to three x4 downstream ports
Low latency cut-through switch architecture
Support for Max Payload Size up to 2048 bytes
One virtual channel
Eight traffic classes
PCI Express Base Specification Revision 2.0 compliant
Flexible Architecture with Numerous Configuration Options
Automatic per port link width negotiation to x8, x4, x2 or x1
Automatic lane reversal on all ports
Automatic polarity inversion
Ability to load device configuration from serial EEPROM
Legacy Support
PCI compatible INTx emulation
Bus locking
Highly Integrated Solution
Incorporates on-chip internal memory for packet buffering and
queueing
Integrates sixteen 5 Gbps embedded SerDes with 8b/10b
encoder/decoder (no separate transceivers needed)
Receive equalization (RxEQ)
Reliability, Availability, and Serviceability (RAS) Features
Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Supports ECRC and Advanced Error Reporting
All internal data and control RAMs are SECDED ECC
protected
Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
Compatible with Hot-Plug I/O expanders used on PC mother-
boards
Supports Hot-Swap
Block Diagram
Figure 1 Internal Block Diagram
4-Port Switch Core / 16 PCI Express Lanes
Frame Buffer Route Table Port
Arbitration Scheduler
SerDes
Phy
Logical
Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
(Port 0) (Port 1) (Port 3)
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
(Port 2)
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
89HPES16T4AG2
Data Sheet
16-Lane 4-Port
Gen2 PCI Express® Switch
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IDT 89HPES16T4AG2 Data Sheet
Power Management
Utilizes advanced low-power design techniques to achieve low
typical power consumption
Support PCI Express Power Management Interface specifica-
tion (PCI-PM 2.0)
Unused SerDes are disabled.
Supports Advanced Configuration and Power Interface Spec-
ification, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
Built in Pseudo-Random Bit Stream (PRBS) generator
Numerous SerDes test modes
Ability to read and write any internal register via the SMBus
Ability to bypass link training and force any link into any mode
Provides statistics and performance counters
Seven General Purpose Input/Output Pins
Each pin may be individually configured as an input or output
Each pin may be individually configured as an interrupt input
Some pins have selectable alternate functions
Packaged in a 19mm x 19mm, 324-ball Flip Chip BGA with
1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES16T4AG2
provides the most efficient fan-out solution for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 16 GBps (128 Gbps) of aggregated,
full-duplex switching capacity through 16 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 Gbps of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES16T4AG2 is based on a flexible and efficient layered archi-
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 2.0. The PES16T4AG2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
Figure 2 I/O Expansion Application
SMBus Interface
The PES16T4AG2 contains two SMBus interfaces. The slave inter-
face provides full access to the configuration registers in the
PES16T4AG2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES16T4AG2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
Two pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin and an SMBus data pin. The Master
SMBus address is hardwired to 0x50, and the slave SMBus address is
hardwired to 0x77.
As shown in Figure 3, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 3(a), the master and slave SMBuses are tied together and the
PES16T4AG2 acts both as a SMBus master as well as a SMBus slave
on this bus. This requires that the SMBus master or processor that has
access to PES16T4AG2 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES16T4AG2 may be configured to operate in a split configuration as
shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES16T4AG2 supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
Memory
Memory
Memory
Processor
Memory
North
Bridge
PES16T4AG2
I/O
10GbE
I/O
10GbE
I/O
SATA
I/O
SATA
PCI Express
Slot
Processor
x8/x4
x4 x4 x4
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IDT 89HPES16T4AG2 Data Sheet
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES16T4AG2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES16T4AG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES16T4AG2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES16T4AG2. In response to an I/O expander interrupt, the PES16T4AG2 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES16T4AG2 provides 7 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Processor
PES16T4AG2
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES16T4AG2
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
... ...
(a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses
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IDT 89HPES16T4AG2 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES16T4AG2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal Type Name/Description
PE0RP[3:0]
PE0RN[3:0]
IPCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TP[3:0]
PE0TN[3:0]
OPCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PE1RP[3:0]
PE1RN[3:0]
IPCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1.
PE1TP[3:0]
PE1TN[3:0]
OPCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1.
PE2RP[3:0]
PE2RN[3:0]
IPCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[3:0]
PE2TN[3:0]
OPCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE3RP[3:0]
PE3RN[3:0]
IPCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3.
PE3TP[3:0]
PE3TN[3:0]
OPCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 3.
PEREFCLKP
PEREFCLKN
IPCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is set at 100 MHz.
Table 1 PCI Express Interface Pins
Signal Type Name/Description
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus which operates at 400 KHz.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus which operates at 400 KHz.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 2 SMBus Interface Pins
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IDT 89HPES16T4AG2 Data Sheet
Signal Type Name/Description
GPIO[0] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2.
GPIO[1] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[2] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O expander interrupt 0 input.
GPIO[7] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
GPIO[8] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
GPIO[9] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
GPIO[10] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 3 General Purpose I/O Pins
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IDT 89HPES16T4AG2 Data Sheet
Signal Type Name/Description
CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be overridden by modifying the SCLK bit in each down-
stream port’s PCIELSTS register.
CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the P0_PCIELSTS register.
P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled high
internally via a 92K ohm resistor.
When this pin is low, port 0 is merged with port 1 to form a single x8 port.
The Serdes lanes associated with port 1 become lanes 4 through 7 of port
0. When this pin is high, port 0 and port 1 are not merged, and each oper-
ates as a single x4 port.
P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled high
internally via a 92K ohm resistor.
When this pin is low, port 2 is merged with port 3 to form a single x8 port.
The Serdes lanes associated with port 3 become lanes 4 through 7 of port
2. When this pin is high, port 2 and port 3 are not merged, and each oper-
ates as a single x4 port.
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside
PES16T4AG2 and initiates a PCI Express fundamental reset.
SWMODE[2:0] I Switch Mode. These configuration pins determine the PES16T4AG2
switch operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
Table 4 System Pins
Signal Type Name/Description
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 5 Test Pins (Part 1 of 2)
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IDT 89HPES16T4AG2 Data Sheet
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Signal Type Name/Description
REFRES0 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES1 I/O Port 1 External Reference Resistor. Provides a reference for the Port 1
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES2 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES3 I/O Port 3 External Reference Resistor. Provides a reference for the Port 3
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
VDDCORE I Core VDD. Power supply for core logic.
VDDI/O I I/O VDD. LVTTL I/O buffer power supply.
VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V).
VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).
VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
VSS IGround.
Table 6 Power, Ground, and SerDes Resistor Pins
Signal Type Name/Description
Table 5 Test Pins (Part 2 of 2)
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IDT 89HPES16T4AG2 Data Sheet
Pin Characteristics
Note: Some input pads of the PES16T4AG2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function Pin Name Type Buffer I/O
Type
Internal
Resistor1Notes
PCI Express Inter-
face
PE0RN[3:0] I PCIe
differential2
Serial Link
PE0RP[3:0] I
PE0TN[3:0] O
PE0TP[3:0] O
PE1RN[3:0] I
PE1RP[3:0] I
PE1TN[3:0] O
PE1TP[3:0] O
PE2RN[3:0] I
PE2RP[3:0] I
PE2TN[3:0] O
PE2TP[3:0] O
PE3RN[3:0] I
PE3RP[3:0] I
PE3TN[3:0] O
PE3TP[3:0] O
PEREFCLKN I HCSL Diff. Clock
Input
Refer to Table 8
PEREFCLKP I
SMBus MSMBCLK I/O STI3pull-up on board
MSMBDAT I/O STI pull-up on board
SSMBCLK I/O STI pull-up on board
SSMBDAT I/O STI pull-up on board
General Purpose I/O GPIO[10:7, 2:0] I/O LVTTL STI,
High Drive
pull-up
System Pins CCLKDS I LVTTL Input pull-up
CCLKUS I Input pull-up
P01MERGEN I pull-up
P23MERGEN I pull-up
PERSTN I STI
SWMODE[2:0] I Input pull-down
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up
Table 7 Pin Characteristics (Part 1 of 2)
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IDT 89HPES16T4AG2 Data Sheet
SerDes Reference
Resistors
REFRES0 I/O Analog Input
REFRES1 I/O
REFRES2 I/O
REFRES3 I/O
1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down.
2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3. Schmitt Trigger Input (STI).
Function Pin Name Type Buffer I/O
Type
Internal
Resistor1Notes
Table 7 Pin Characteristics (Part 2 of 2)
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IDT 89HPES16T4AG2 Data Sheet
Logic Diagram — PES16T4AG2
Figure 4 PES16T4AG2 Logic Diagram
PE0TP[0]
Reference
Clocks PEREFCLKP
PEREFCLKN
JTAG_TCK
GPIO[10:7,2:0]
7General Purpose
I/O
VDDCORE
VDDI/O
VDDPEA
Power/Ground
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Master
SMBus Interface
Slave
SMBus Interface
CCLKUS
P01MERGEN
System
Pins
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
VSS
SWMODE[2:0] 3
CCLKDS
PERSTN
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PCI Express
Switch
SerDes Input
PE0TN[0]
PE0TP[3]
PE0TN[3]
PCI Express
Switch
SerDes Output
...
Port 0 Port 0
...
PE1RP[0]
PE1RN[0]
PE1RP[3]
PE1RN[3]
PCI Express
Switch
SerDes Input
PE1TP[0]
PE1TN[0]
PE1TP[3]
PE1TN[3]
PCI Express
Switch
SerDes Output
...
Port 1 Port 1
...
PE2RP[0]
PE2RN[0]
PE2RP[3]
PE2RN[3]
PCI Express
Switch
SerDes Input
PE2TP[0]
PE2TN[0]
PE2TP[3]
PE2TN[3]
PCI Express
Switch
SerDes Output
...
Port 2 Port 2
...
PE3RP[0]
PE3RN[0]
PE3RP[3]
PE3RN[3]
PCI Express
Switch
SerDes Input
PE3TP[0]
PE3TN[0]
PE3TP[3]
PE3TN[3]
PCI Express
Switch
SerDes Output
...
Port 3 Port 3
...
PES16T4AG2
REFRES0 SerDes
Reference
Resistors
REFRES1
REFRES2
REFRES3
VDDPEHA
VDDPETA
P23MERGEN
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IDT 89HPES16T4AG2 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 14.
AC Timing Characteristics
Parameter Description Condition Min Typical Max Unit
RefclkFREQ Input reference clock frequency range 100 1001
1. The input clock frequency is set at 100 MHz.
MHz
TC-RISE Rising edge rate Differential 0.6 4 V/ns
TC-FALL Falling edge rate Differential 0.6 4 V/ns
VIH Differential input high voltage Differential +150 mV
VIL Differential input low voltage Differential -150 mV
VCROSS Absolute single-ended crossing point
voltage
Single-ended +250 +550 mV
VCROSS-DELTA Variation of VCROSS over all rising clock
edges
Single-ended +140 mV
VRB Ring back voltage margin Differential -100 +100 mV
TSTABLE Time before VRB is allowed Differential 500 ps
TPERIOD-AVG Average clock period accuracy -300 2800 ppm
TPERIOD-ABS Absolute period, including spread-spec-
trum and jitter
9.847 10.203 ns
TCC-JITTER Cycle to cycle jitter 150 ps
VMAX Absolute maximum input voltage +1.15 V
VMIN Absolute minimum input voltage -0.3 V
Duty Cycle Duty cycle 40 60 %
Rise/Fall Matching Single ended rising Refclk edge rate ver-
sus falling Refclk edge rate
20 %
ZC-DC Clock source output DC impedance 40 60 Ω
Table 8 Input Clock Requirements
Parameter Description Gen 1 Gen 2 Units
Min1Typ1Max1Min1Typ1Max1
PCIe Transmit
UI Unit Interval 399.88 400 400.12 199.94 200 200.06 ps
TTX-EYE Minimum Tx Eye Width 0.75 0.75 UI
TTX-EYE-MEDIAN-to-
MAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
0.125 UI
TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% 0.125 0.15 UI
TTX- IDLE-MIN Minimum time in idle 20 20 UI
Table 9 PCIe AC Timing Characteristics (Part 1 of 2)
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IDT 89HPES16T4AG2 Data Sheet
TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending
an Idle ordered set
88 ns
TTX-IDLE-TO-DIFF-
DATA
Maximum time to transition from valid idle to diff data 8 8 ns
TTX-SKEW Transmitter data skew between any 2 lanes 1.3 1.3 ns
TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA 0.9 UI
TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI
TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI
PCIe Receive
UI Unit Interval 399.88 400 400.12 199.94 200.06 ps
TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI
TRX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation 0.3 UI
TRX-SKEW Lane to lane input skew 20 8 ns
TRX-HF-RMS 1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps
TRX-HF-DJ-DD Maximum tolerable DJ by the receiver (common clock) NA 88 ps
TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps
TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0
Signal Symbol Reference
Edge Min Max Unit
Timing
Diagram
Reference
GPIO
GPIO[10:7,2:0]1
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
Tpw2
2. The values for this symbol were determined by calculation, not by testing.
None 50 ns
Table 10 GPIO AC Timing Characteristics
Parameter Description Gen 1 Gen 2 Units
Min1Typ1Max1Min1Typ1Max1
Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
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IDT 89HPES16T4AG2 Data Sheet
Figure 5 JTAG AC Timing Waveform
Signal Symbol Reference
Edge Min Max Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK Tper_16a none 50.0 ns See Figure 5.
Thigh_16a,
Tlow_16a
10.0 25.0 ns
JTAG_TMS1,
JTAG_TDI
1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK rising 2.4 ns
Thld_16b 1.0 ns
JTAG_TDO Tdo_16c JTAG_TCK falling 20 ns
Tdz_16c2
2. The values for this symbol were determined by calculation, not by testing.
—20ns
JTAG_TRST_N Tpw_16d2none 25.0 ns
Table 11 JTAG AC Timing Characteristics
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
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IDT 89HPES16T4AG2 Data Sheet
Recommended Operating Supply Voltages
Absolute Maximum Voltage Rating
Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages
in Table 12. The absolute maximum operating voltages in Table 13 are offered to provide guidelines for voltage excursions outside the recommended
voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside
the maximum range may adversely affect device functionality and reliability.
Power-Up/Power-Down Sequence
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Symbol Parameter Minimum Typical Maximum Unit
VDDCORE Internal logic supply 0.9 1.0 1.1 V
VDDI/O I/O supply except for SerDes LVPECL/CML 3.135 3.3 3.465 V
VDDPEA1
1. VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC
value.
PCI Express Analog Power 0.95 1.0 1.1 V
VDDPEHA2
2. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
VDDPETA1PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
VSS Common ground 0 0 0 V
Table 12 PES16T4AG2 Operating Voltages
Core Supply PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply
1.5V 1.5V 4.6V 1.5V 4.6V
Table 13 PES16T4AG2 Absolute Maximum Voltage Rating
Grade Temperature
Commercial 0°C to +70°C Ambient
Industrial -40°C to +85°C Ambient
Table 14 PES16T4AG2 Operating Temperatures
15 of 32 May 23, 2013
IDT 89HPES16T4AG2 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 12
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 12 (and also listed below).
Thermal Considerations
This section describes thermal considerations for the PES16T4AG2 (19mm2 FCBGA324 package). The data in Table 16 below contains informa-
tion that is relevant to the thermal performance of the PES16T4AG2 switch.
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value
specified in Table 16. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be
maintained below the value determined by the formula:
θ
JA = (TJ(max) - TA(max))/P
Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to
achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value
provided in Table 16), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the
circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more
layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform
their own thermal analysis for their own board and system design scenarios.
Number of active
Lanes per Port
Core Supply PCIe Analog
Supply
PCIe Analog
High Supply
PCIe Termin-
ation Supply I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465V
Typ
Power
Max
Power
8/4/4 mA 413 905 901 963 110 123 360 429 2 2
Watts 0.41 1.0 0.90 1.06 0.28 0.34 0.36 0.47 0.007 0.007 1.96 2.87
4/4/4/4 mA 413 905 901 963 110 123 180 215 2 2
Watts 0.41 1.0 0.90 1.06 0.28 0.34 0.18 0.24 0.01 0.01 1.78 2.64
Table 15 PES16T4AG2 Power Consumption
Symbol Parameter Value Units Conditions
TJ(max) Junction Temperature 125 oCMaximum
TA(max) Ambient Temperature 70 oCMaximum
θJA(effective) Effective Thermal Resistance, Junction-to-Ambient
16.8 oC/W Zero air flow
10.1 oC/W 1 m/S air flow
9.2 oC/W 2 m/S air flow
θJB Thermal Resistance, Junction-to-Board 4.1 oC/W
θJC Thermal Resistance, Junction-to-Case 0.3 oC/W
P Power Dissipation of the Device 2.87 Watts Maximum
Table 16 Thermal Specifications for PES16T4AG2, 19x19 mm FCBGA324 Package
16 of 32 May 23, 2013
IDT 89HPES16T4AG2 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 12.
Note: See Table 7, Pin Characteristics, for a complete I/O listing.
I/O Type Parameter Description Gen1 Gen2 Unit Condi-
tions
Min1Typ1Max1Min1Typ1Max1
Serial Link PCIe Transmit
VTX-DIFFp-p Differential peak-to-peak output
voltage
800 1200 800 1200 mV
VTX-DIFFp-p-LOW Low-Drive Differential Peak to
Peak Output Voltage
400 1200 400 1200 mV
VTX-DE-RATIO-
3.5dB
De-emphasized differential output
voltage
-3 -4 -3.0 -3.5 -4.0 dB
VTX-DE-RATIO-
6.0dB
De-emphasized differential output
voltage
NA -5.5 -6.0 -6.5 dB
VTX-DC-CM DC Common mode voltage 0 3.6 0 3.6 V
VTX-CM-ACP RMS AC peak common mode
output voltage
20 mV
VTX-CM-DC-active-
idle-delta
Abs delta of DC common mode
voltage between L0 and idle
100 100 mV
VTX-CM-DC-line-
delta
Abs delta of DC common mode
voltage between D+ and D-
25 25 mV
VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV
RLTX-DIFF Transmitter Differential Return
loss
10 10 dB 0.05 - 1.25GHz
8 dB 1.25 - 2.5GHz
RLTX-CM Transmitter Common Mode
Return loss
66dB
ZTX-DIFF-DC DC Differential TX impedance 80 100 120 120 Ω
VTX-CM-ACpp Peak-Peak AC Common NA 100 mV
VTX-DC-CM Transmit Driver DC Common
Mode Voltage
0 3.6 0 3.6 V
VTX-RCV-DETECT The amount of voltage change
allowed during Receiver Detec-
tion
600 600 mV
ITX-SHORT Transmitter Short Circuit Current
Limit
090 90mA
Table 17 DC Electrical Characteristics (Part 1 of 2)
17 of 32 May 23, 2013
IDT 89HPES16T4AG2 Data Sheet
Serial Link
(cont.)
PCIe Receive
VRX-DIFFp-p Differential input voltage (peak-to-
peak)
175 1200 120 1200 mV
RLRX-DIFF Receiver Differential Return Loss 10 10 dB 0.05 - 1.25GHz
8 1.25 - 2.5GHz
RLRX-CM Receiver Common Mode Return
Loss
66dB
ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Refer to return loss spec Ω
ZRX--DC DC common mode impedance 40 50 60 40 60 Ω
ZRX-COMM-DC Powered down input common
mode impedance (DC)
200k 350k 50k Ω
ZRX-HIGH-IMP-DC-
POS
DC input CM input impedance for
V>0 during reset or power down
50k 50k Ω
ZRX-HIGH-IMP-DC-
NEG
DC input CM input impedance for
V<0 during reset or power down
1.0k 1.0k Ω
VRX-IDLE-DET-
DIFFp-p
Electrical idle detect threshold 65 175 65 175 mV
VRX-CM-ACp Receiver AC common-mode peak
voltage
150 150 mV VRX-CM-ACp
PCIe REFCLK
CIN Input Capacitance 1.5 1.5 pF
Other I/Os
LOW Drive
Output
IOL —2.5— —2.5 mAV
OL = 0.4v
IOH —-5.5— —-5.5 mAV
OH = 1.5V
High Drive
Output
IOL 12.0 12.0 mA VOL = 0.4v
IOH -20.0 -20.0 mA VOH = 1.5V
Schmitt Trig-
ger Input
(STI)
VIL -0.3 0.8 -0.3 0.8 V
VIH 2.0 VDDI/O +
0.5
2.0 VDDI/O +
0.5
V—
Input VIL -0.3 0.8 -0.3 0.8 V
VIH 2.0 VDDI/O +
0.5
2.0 VDDI/O +
0.5
V—
Capacitance CIN ——8.5——8.5pF
Leakage Inputs + 10 + 10 μAV
DDI/O (max)
I/OLEAK W/O
Pull-ups/downs
——+
10 + 10 μAV
DDI/O (max)
I/OLEAK WITH
Pull-ups/downs
——+
80 + 80 μAV
DDI/O (max)
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0.
I/O Type Parameter Description Gen1 Gen2 Unit Condi-
tions
Min1Typ1Max1Min1Typ1Max1
Table 17 DC Electrical Characteristics (Part 2 of 2)
18 of 32 May 23, 2013
IDT 89HPES16T4AG2 Data Sheet
Package Pinout — 324-BGA Signal Pinout for PES16T4AG2
The following table lists the pin numbers and signal names for the PES16T4AG2 device.
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
A1 VSS B17 NC D15 VDDCORE F13 VSS
A2 VDDI/O B18 NC D16 VSS F14 NC
A3 P01MERGEN C1 PE3TP02 D17 VSS F15 NC
A4 P23MERGEN C2 PE3TN02 D18 VSS F16 VSS
A5 VSS C3 VSS E1 PE3TP01 F17 NC
A6 VDDI/O C4 PE3RP02 E2 PE3TN01 F18 NC
A7 VSS C5 PE3RN02 E3 VSS G1 VSS
A8 JTAG_TDI C6 VSS E4 PE3RP01 G2 VSS
A9 MSMBDAT C7 JTAG_TCK E5 PE3RN01 G3 VSS
A10 VDDI/O C8 JTAG_TRST_N E6 VDDCORE G4 VDDCORE
A11 VSS C9 SSMBDAT E7 VDDCORE G5 VDDCORE
A12 GPIO_00 1 C10 CCLKDS E8 VDDCORE G6 VDDPEA
A13 VDDI/O C11 SWMODE_2 E9 VSS G7 VDDPEA
A14 VDDI/O C12 GPIO_02 1 E10 VDDCORE G8 VDDCORE
A15 VSS C13 GPIO_09 1 E11 VDDCORE G9 VDDCORE
A16 VSS C14 NC E12 VDDCORE G10 VDDCORE
A17 VDDI/O C15 NC E13 VDDCORE G11 VSS
A18 VDDI/O C16 VSS E14 NC G12 VDDPEA
B1 PE3TP03 C17 NC E15 NC G13 VDDPEA
B2 PE3TN03 C18 NC E16 VSS G14 VDDCORE
B3 VSS D1 VSS E17 NC G15 VDDCORE
B4 PE3RP03 D2 VSS E18 NC G16 VSS
B5 PE3RN03 D3 VSS F1 PE3TP00 G17 VSS
B6 VDDI/O D4 VDDCORE F2 PE3TN00 G18 VSS
B7 VDDI/O D5 VDDCORE F3 VSS H1 PE2TP03
B8 JTAG_TMS D6 VSS F4 PE3RP00 H2 PE2TN03
B9 SSMBCLK D7 JTAG_TDO F5 PE3RN00 H3 VSS
B10 VDDI/O D8 MSMBCLK F6 VSS H4 PE2RP03
B11 SWMODE_1 D9 CCLKUS F7 VSS H5 PE2RN03
B12 GPIO_01 D10 SWMODE_0 F8 VDDCORE H6 VDDPEA
B13 GPIO_10 D11 PERSTN F9 VSS H7 VDDPEA
B14 NC D12 GPIO_07 1 F10 VDDCORE H8 VDDCORE
B15 NC D13 GPIO_08 1 F11 VSS H9 VDDCORE
B16 VSS D14 VDDCORE F12 VSS H10 VDDCORE
Table 18 PES16T4AG2 324-pin Signal Pin-Out (Part 1 of 3)