TECHNITROL
P ART NO .
T A P DEL AYS (n s ) ALL TAP S
T
DD
1 T
DD
2 T
DD
3 T
DD
4 T
DD
5 T
RORO
T
FOFO
CTTLDL025 5.0 10.0 15.0 20.0 25.0 2.0 2.0
CTTLDL050 10.0 20.0 30.0 40.0 50.0 2.0 2.0
CTTLDL075 15.0 30.0 45.0 60.0 75.0 2.0 2.0
CTTLDL100 20.0 40.0 60.0 80.0 100.0 2.0 5.0
CTTLDL125 25.0 50.0 75.0 100.0 125.0 2.0 5.0
CTTLDL150 30.0 60.0 90.0 120.0 150.0 2.0 6.0
CTTLDL200 40.0 80.0 120.0 160.0 200.0 2.0 7.0
High-Performance Surface-Mount
TTL Delay Lines
nFive equal taps in 20% increments of total delay.
nLumped constant, active series.
nTransfer-molded packaging for highest reliability.
nDesigned for leading edge timing. Trailing edge
timing available.
nSupports Schottky TTL, FAST, and FACT logics.
nFanout 1 -- 20 loads; logic 0 -- 10 loads.
nTemperature coefficient +2 ns or +4% (whichever is
greater) at maximum delay, 0 to 70oC.
TWO PEARL BUCK COURT
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BRISTOL, PA 19007-6812
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TEL 215-781-6400
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FAX 215-781-6403
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www.pulsespecialty.com
nMilitary models with temperature range -55 to
+125oC and ceramic package IC to meet MIL-STD-
883C, but not screened to that specification, add
suffix “M” to part number.
nMilitary models as above, but with ceramic package
IC screened to MIL-STD 883C and 38510, add
suffix “MX” to part number.
nMilitary models as “MX” above, but with in-house
burn-in and thermal shock, add suffix “MY”.
For TTL delay lines qualified
to MIL-D-83532, refer to PSC
information sheet entitled
“QPL Active Delay Lines.”
CTTLDL,
BJTTLDL,
GBTTLDL,
BTTLDL
Delay Characteristics measured at Vcc = 5.0V, 25oC, no load.
Delay Tolerance +2 ns or 5%, whichever is greater.
Rise time measured @ 0.8V to 2.0V levels.
For minimum input pulse width -- contact factory.
LOW PROFILE SURFACE-MOUNT 5-TAP TTL DELAY LINES
O.175”
MAX
HEIGHT
SCHEMATIC
MECHANICAL OUTLINE
Notes
nPin numbers shown are for reference only
and are not necessarily marked on unit.
nLead material is electro tin plated
(alloy 42) or solder dipped.
nAll specifications are subject to change
without notice.