© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 8 1Publication Order Number:
MC74HCT4851A/D
MC74HCT4851A,
MC74HCT4852A
Analog Multiplexers/
Demultiplexers with
Injection Current Effect
Control with LSTTL
Compatible Inputs
Automotive Customized
This device is pin compatible to standard HC405x and MC1405xB
analog mux/demux devices, but feature injection current effect
control. This makes them especially suited for usage in automotive
applications where voltages in excess of normal logic voltage are
common.
The injection current effect control allows signals at disabled analog
input channels to exceed the supply voltage range without affecting
the signal of the enabled analog channel. This eliminates the need for
external diode/ resistor networks typically used to keep the analog
channel signals within the supply voltage range.
The devices utilize low power silicon gate CMOS technology. The
Channel Select and Enable inputs are compatible with standard CMOS
or LSTTL outputs.
Features
•Injection Current Cross−Coupling Less than 1mV/mA (See Figure 6)
•Pin Compatible to HC405x and MC1405xB Devices
•Power Supply Range (VCC − GND) = 4.5 to 5.5 V
•In Compliance With the Requirements of JEDEC Standard No. 7 A
•Chip Complexity: 154 FETs or 36 Equivalent Gates
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
1
16
1
16
HCT485xAG
AWLYWW
HCT4
85xA
ALYWG
G
1
16
X = 1 or 2
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
1
16 SOIC−16 WIDE
DW SUFFIX
CASE 751G
1
16
HCT485xA
AWLYWWG
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
2
Figure 1. MC74HCT4851A Logic Diagram
Single−Pole, 8−Position Plus Common Off
X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
A11
B10
C9
ENABLE 6
MULTIPLEXER/
DEMULTIPLEXER X
3
ANALOG
INPUTS/
CHANNEL
INPUTS
PIN 16 = VCC
PIN 8 = GND
COMMON
OUTPUT/
INPUT
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X0 X3 A B C
X4 X6 X X7 X5 Enable NC GND
Figure 2. MC74HCT4851A 16−Lead Pinout (Top View)
OUTPUTS
SELECT
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE − MC74HCT4851A
Control Inputs
ON Channels
Enable Select
CBA
X0
X1
X2
X3
X4
X5
X6
X7
NONE
L
L
L
L
L
L
L
L
H
Figure 3. MC74HCT4852A Logic Diagram
Double−Pole, 4−Position Plus Common Off
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
A10
B9
ENABLE 6
X SWITCH
Y SWITCH
X
13
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS PIN 16 = VCC
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
L
L
H
H
X
L
H
L
H
X
FUNCTION TABLE − MC74HCT4852A
Control Inputs
ON Channels
Enable Select
BA
X0
X1
X2
X3
L
L
L
L
H
X = Don’t Care
Figure 4. MC74HCT4852A 16−Lead Pinout (Top View)
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X X0 X3 A B
Y0 Y2 Y Y3 Y1 Enable NC GND
Y
3
Y0
Y1
Y2
Y3 NONE
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage (Referenced to GND) –0.5 to + 7.0 V
Vin DC Input Voltage (Any Pin) (Referenced to GND) –0.5 to VCC + 0.5 V
IDC Current, Into or Out of Any Pin $25 mA
PDPower Dissipation in Still Air, SOIC Package†
TSSOP Package† 500
450 mW
Tstg Storage Temperature Range –65 to + 150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package 260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC Positive DC Supply Voltage (Referenced to GND) 4.5 5.5 V
Vin DC Input Voltage (Any Pin) (Referenced to GND) GND VCC V
VIO*Static or Dynamic Voltage Across Switch 0.0 1.2 V
TAOperating Temperature Range, All Package Types – 55 + 125 °C
tr, tfInput Rise/Fall Time VCC = 2.0 V
(Channel Select or Enable Inputs) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbo
l
Parameter Condition VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
VIH Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs Ron = Per Spec 4.5
to
5.5
2.0 2.0 2.0 V
VIL Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs Ron = Per Spec 4.5
to
5.5
0.8 0.8 0.8 V
Iin Maximum Input Leakage Current on Digital Pins
(Enable/A/B/C) Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply Current
(per Package) Vin(digital) = VCC or GND
Vin(analog) = GND 5.5 2.0 20 40 mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
4
DC CHARACTERISTICS — Analog Section
Symbo
l
Parameter Condition VCC
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to
GND (Note 1); IS ≤ 2.0 mA
(Note 2)
4.5
5.5 550
400 650
500 750
600 W
DRon Delta “ON” Resistance Vin = VIL or VIH; VIS = VCC/2
(Note 1); IS ≤ 2.0 mA (Note 2) 4.5
5.5 80
60 100
80 120
100 W
Ioff Maximum Off−Channel Leakage Current,
Any One Channel Common Channel
Vin = VCC or GND 5.5 ±0.1
±0.1 ±0.1
±0.1 ±0.1
±0.1
mA
Ion Maximum On−Channel Leakage
Channel−to−Channel Vin = VCC or GND 5.5 ±0.1 ±0.1 ±0.1 mA
1. VIS is the input voltage of an analog I/O pin.
2. IS is the currebnt flowing in or out of analog I/O pin.
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%)
Symbol Parameter VCC −55 to 25°C≤85°C≤125°C Unit
tPHL,
tPLH Maximum Propagation Delay, Analog Input to Analog Output 5.0 40 45 50 ns
tPHL,
tPHZ,PZH
tPLH,
tPLZ,PZL
Maximum Propagation Delay, Enable or Channel−Select to Analog Output 5.0 80 90 100 ns
Cin Maximum Input Capacitance Digital Pins
(All Switches Off) Any Single Analog Pin
(All Switches Off) Common Analog Pin
10
35
40
10
35
40
10
35
40
pF
CPD Power Dissipation Capacitance Typical 5.0 20 pF
INJECTION CURRENT COUPLING SPECIFICATIONS (VCC = 5V, TA = −55°C to +125°C)
Symbol Parameter Condition Typ Max Unit
VDout Maximum Shift of Output Voltage of Enabled Analog Channel Iin* ≤ 1 mA, RS ≤ 3,9 kW
Iin* ≤ 10 mA, RS ≤ 3,9 kW
Iin* ≤ 1 mA, RS ≤ 20 kW
Iin* ≤ 10 mA, RS ≤ 20 kW
0.1
1.0
0.5
5.0
1.0
5.0
2.0
20
mV
* Iin = Total current injected into all disabled channels.
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
5
Figure 5. Typical On Resistance VCC = 4.5V
Figure 6. Injection Current Coupling Specification
Current Source
HP4155C
Smu #2
Vin1 = 4.9 V (Smu3)
Iin1 measure here
Vm1 connected here.
Vin2 / Iin2 meas. here.
GND or VSS
3
NOTES: Rs = 3.9 KW or 20 KW.
NOTES: Vm1 & Vm2 are internal
NOTES: HP4155C Voltmeters.
16
4
13
6
8
External DC P.S.
VCC = 5 V
XVout
Vm2 connected here.
X7
X0
RS
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
6
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Common Out
VCC
HCT4051A Microcontroller
A/D - Input
VCC
5V
6V5V
Sensor
(8x Identical Circuitry)
Figure 7. Actual Technology
Requires 32 passive components and one extra 6V regulator
to suppress injection current into a standard HCT4051 multiplexer
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Common Out
VCC
HCT4851A Microcontroller
A/D - Input
VCC
5V
Sensor
(8x Identical Circuitry)
Figure 8. MC74HCT4851A Solution
Solution by applying the HCT4851A multiplexer
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
7
Figure 9. On Resistance Test Set−Up
PLOTTER
MINI COMPUTER
PROGRAMMABLE
POWER
SUPPLY
DC ANALYZER
VCC
DEVICE
UNDER TEST
+-
ANALOG IN COMMON OUT
GND
Figure 10. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
OFF
OFF
6
8
16
COMMON O/I
VCC
VIH
NC
A
VCC
VEE
VCC
Figure 11. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
OFF
OFF
6
8
16
COMMON O/I
VCC
VIH
ANALOG I/O
VCC
VEE
VCC
A
Figure 12. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
ON
OFF
6
8
16
COMMON O/I
VCC
VIL
VCC
VEE
VCC
N/C
A
ANALOG I/O
Figure 13. Propagation Delays, Channel Select
to Analog Out Figure 14. Propagation Delay, Test Set−Up Channel
Select to Analog Out
VCC
GND
CHANNEL
SELECT
(VI)
ANALOG
OUT 50%
tPLH tPHL
VM
ON/OFF
6
8
16
VCC
CL*
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
OFF/ON
ANALOG I/O
VCC
VI = GND to 3.0 V
VM = 1.3 V
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
8
Figure 15. Propagation Delays, Analog In
to Analog Out Figure 16. Propagation Delay, Test Set−Up
Analog In to Analog Out
Figure 17. Propagation Delays, Enable to
Analog Out Figure 18. Propagation Delay, Test Set−Up
Enable to Analog Out
VCC
GND
ANALOG
IN
(VI)
ANALOG
OUT 50%
tPLH tPHL
50%
ON
6
8
16
VCC
CL*
*Includes all probe and jig capacitance
TEST
POINT
COMMON O/I
ANALOG I/O
ON/OFF
6
8
ENABLE
VCC
ENABLE
(VI)
90%
VM
10%
tftr
VCC
GND
ANALOG
OUT
tPZL
ANALOG
OUT
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
ANALOG I/O
CL*
TEST
POINT
16
VCC
10kW
1
2
1
2
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
Figure 19. Power Dissipation Capacitance,
Test Set−Up
VI = GND to 3.0 V
VM = 1.3 V
VI = GND to 3.0 V
VM = 1.3 V
6
8
16
VCC
CHANNEL SELECT
NC
COMMON O/I
ANALOG I/O
VCC A
11
VCC
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
9
Figure 20. Diagram of Bipolar Coupling Mechanism
Appears if Vin exceeds VCC, driving injection current into the substrate
Figure 21. Function Diagram, HCT4851A
++
+
P+ P+
N - Substrate (on VCC potential)
Gate = VCC
(Disabled) Common Analog Output
Vout > VCC
Disabled Analog Mux Input
Vin > VCC + 0.7V
INJECTION 13
INJECTION 14
INJECTION 15
INJECTION 12
INJECTION 1
INJECTION 5
INJECTION 2
INJECTION 4
INJECTION 3
6
9
10
11
A
B
C
E
NABLE
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
10
Figure 22. Function Diagram, HCT4852A
INJECTION 13
INJECTION 14
INJECTION 1315
INJECTION 12
INJECTION 1
INJECTION 5
INJECTION 2
INJECTION 4
INJECTION 3
6
9
10
A
B
E
NABLE
X
0
X
1
X
2
X
3
Y
0
Y
1
Y
2
Y
3
Y
INJECTION 3X
CURRENT
CONTROL
CURRENT
CONTROL
CURRENT
CONTROL
CURRENT
CONTROL
CURRENT
CONTROL
CURRENT
CONTROL
CURRENT
CONTROL
CURRENT
CONTROL
CURRENT
CONTROL
CURRENT
CONTROL
MC74HCT4851A, MC74HCT4852A
www.onsemi.com
11
ORDERING INFORMATION
Device Package Shipping†
MC74HCT4851ADG SOIC−16
(Pb−Free) 48 Units / Rail
MC74HCT4851ADR2G SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
NLV74HCT4851ADRG* SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
MC74HCT4851ADTG TSSOP−16
(Pb−Free) 48 Units / Rail
M74HCT4851ADTR2G TSSOP−16
(Pb−Free) 2500 Units / Tape & Reel
NLVHCT4851ADTR2G* TSSOP−16
(Pb−Free) 2500 Units / Tape & Reel
M74HCT4851ADWR2G SOIC−16 WIDE
(Pb−Free) 1000 Units / Tape & Reel
MC74HCT4852ADG SOIC−16
(Pb−Free) 48 Units / Rail
MC74HCT4852ADR2G SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
MC74HCT4852ADTG TSSOP−16
(Pb−Free) 48 Units / Rail
M74HCT4852ADTR2G TSSOP−16
(Pb−Free) 2500 Units / Tape & Reel
NLVHCT4852ADTR2G* TSSOP−16
(Pb−Free) 2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
15. EMITTER
16. COLLECTOR
STYLE 2:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
16. CATHODE
STYLE 3:
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
15. EMITTER, #4
16. COLLECTOR, #4
STYLE 4:
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
STYLE 5:
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
STYLE 7:
PIN 1. SOURCE N‐CH
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
9. SOURCE P‐CH
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
16
89
8X
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42566B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOIC−16
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−16 WB
CASE 751G−03
ISSUE D
DATE 12 FEB 2013
SCALE 1:1
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
eT
A1
A
L
C
qNOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
GENERIC
MARKING DIAGRAM*
16
1
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
11.00
16X 0.58
16X
1.62 1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42567B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOIC−16 WB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TSSOP−16
CASE 948F−01
ISSUE B
DATE 19 OCT 2006
SCALE 2:1
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
1
16
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYW
1
16
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G or G= Pb−Free Package
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DOCUMENT NUMBER:
DESCRIPTION:
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TSSOP−16
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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