IRFR420TRLPBF - Vishay [Siliconix]

Document Number: 91275 www.vishay.com

S10-1135-Rev. C, 10-May-10 1

Power MOSFET

IRFR420, IRFU420, SiHFR420, SiHFU420

Vishay Siliconix

FEATURES

•Halogen-free According to IEC 61249-2-21

Definition

• Dynamic dV/dt Rating

• Repetitive Avalanche Rated

• Surface Mount (IRFR420, SiHFR420)

• Straight Lead (IRFU420, SiHFU420)

• Available in Tape and Reel

•Fast Switching

• Ease of Paralleling

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and

cost-effictiveness.

The DPAK is designed for surface mounting using vapor

phase, infrared, or wave soldering techniques. The straight

lead version (IRFU, SiHFU series) is for through-hole

mounting applications. Power dissipation levels up to 1.5 W

are possible in typical surface mount applications.

Note

a. See device orientation.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. VDD = 50 V, starting TJ = 25 °C, L = 124 mH, Rg = 25 Ω, IAS = 2.4 A (see fig. 12).

c. ISD ≤ 2.4 A, dI/dt ≤ 50 A/μs, VDD ≤ VDS, TJ ≤ 150 °C.

d. 1.6 mm from case.

e. When mounted on 1” square PCB (FR-4 or G-10 material).

PRODUCT SUMMARY

VDS (V) 500

RDS(on) (Ω)V

GS = 10 V 3.0

Qg (Max.) (nC) 19

Qgs (nC) 3.3

Qgd (nC) 13

Configuration Single

N-Channel MOSFET

DPAK

(TO-252)

IPAK

(TO-251)

GDS

ORDERING INFORMATION

Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)

Lead (Pb)-free and Halogen-free SiHFR420-GE3 SiHFR420TR-GE3aSiHFR420TRL-GE3aSiHFR420TRR-GE3aSiHFU420-GE3

Lead (Pb)-free IRFR420PbF IRFR420TRPbFa IRFR420TRLPbFa IRFR420TRRPbFa IRFU420PbF

SiHFR420-E3 SiHFR420T-E3a SiHFR420TL-E3a - SiHFU420-E3

SnPb IRFR420 IRFR420TRa IRFR420TRLa IRFR420TRRa IRFU420

SiHFR420 SiHFR420Ta SiHFR420TLa - SiHFU420

ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage VDS 500 V

Gate-Source Voltage VGS ± 20

Continuous Drain Current VGS at 10 V TC = 25 °C ID

2.4

ATC = 100 °C 1.5

Pulsed Drain CurrentaIDM 8.0

Linear Derating Factor 0.33 W/°C

Linear Derating Factor (PCB Mount)e0.020

Single Pulse Avalanche EnergybEAS 400 mJ

Repetitive Avalanche CurrentaIAR 2.4 A

Repetitive Avalanche EnergyaEAR 4.2 mJ

Maximum Power Dissipation TC = 25 °C PD

42 W

Maximum Power Dissipation (PCB Mount)eTA = 25 °C 2.5

Peak Diode Recovery dV/dtcdV/dt 3.5 V/ns

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C

Soldering Recommendations (Peak Temperature) for 10 s 260d

* Pb containing terminations are not RoHS compliant, exemptions may apply

www.vishay.com Document Number: 91275

2S10-1135-Rev. C, 10-May-10

IRFR420, IRFU420, SiHFR420, SiHFU420

Vishay Siliconix

Note

a. When mounted on 1” square PCB (FR-4 or G-10 material).

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient RthJA - 110

°C/W

Maximum Junction-to-Ambient

(PCB Mount)aRthJA -50

Maximum Junction-to-Case (Drain) RthJC -3.0

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 500 - - V

VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.59 - V/°C

Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V

Gate-Source Leakage IGSS V

GS = ± 20 V - - ± 100 nA

Zero Gate Voltage Drain Current IDSS

VDS = 500 V, VGS = 0 V - - 25 μA

VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250

Drain-Source On-State Resistance RDS(on) V

GS = 10 V ID =1.4 Ab--3.0Ω

Forward Transconductance gfs VDS = 50 V, ID = 1.4 A 1.5 - - S

Dynamic

Input Capacitance Ciss VGS = 0 V,

VDS = 25 V,

f = 1.0 MHz, see fig. 5

- 360 -

pFOutput Capacitance Coss -92-

Reverse Transfer Capacitance Crss -37-

Total Gate Charge Qg

VGS = 10 V ID = 2.1 A, VDS = 400 V,

see fig. 6 and 13b

nC Gate-Source Charge Qgs --

3.3

Gate-Drain Charge Qgd --

Turn-On Delay Time td(on)

VDD = 250 V, ID = 2.1 A,

Rg = 18 Ω, RD = 120 Ω, see fig. 10b

-8.0-

Rise Time tr -8.6-

Turn-Off Delay Time td(off) -33-

Fall Time tf -16-

Internal Drain Inductance LD Between lead,

6 mm (0.25") from

package and center of

die contact

-4.5-

Internal Source Inductance LS-7.5-

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS

MOSFET symbol

showing the

integral reverse

p - n junction diode

--2.4

Pulsed Diode Forward CurrentaISM --8.0

Body Diode Voltage VSD TJ = 25 °C, IS = 2.4 A, VGS = 0 Vb--1.6V

Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 2.1 A, dI/dt = 100 A/μsb- 260 520 ns

Body Diode Reverse Recovery Charge Qrr - 0.70 1.4 μC

Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Document Number: 91275 www.vishay.com

S10-1135-Rev. C, 10-May-10 3

IRFR420, IRFU420, SiHFR420, SiHFU420

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 -Typical Output Characteristics, TC = 150 °C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

www.vishay.com Document Number: 91275

4S10-1135-Rev. C, 10-May-10

IRFR420, IRFU420, SiHFR420, SiHFU420

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

Document Number: 91275 www.vishay.com

S10-1135-Rev. C, 10-May-10 5

IRFR420, IRFU420, SiHFR420, SiHFU420

Vishay Siliconix

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

VGS

D.U.T.

10 V

VDS

VDD

VDS

90 %

10 %

VGS

td(on) trtd(off) tf

0.01 Ω

D.U.T.

VDS

-V

10 V

Vary t

to obtain

required I

www.vishay.com Document Number: 91275

6S10-1135-Rev. C, 10-May-10

IRFR420, IRFU420, SiHFR420, SiHFU420

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

QGS QGD

Charge

10 V

D.U.T.

3 mA

VGS

VDS

IGID

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

Document Number: 91275 www.vishay.com

S10-1135-Rev. C, 10-May-10 7

IRFR420, IRFU420, SiHFR420, SiHFU420

Vishay Siliconix

Fig. 14 -For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91275.

P.W. Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied

voltage

Reverse

recovery

current

Body diode forward

current

VGS = 10 Va

ISD

Driver gate drive

D.U.T. lSD waveform

D.U.T. VDS waveform

Inductor current

D = P.W.

Period

Peak Diode Recovery dV/dt Test Circuit

VDD

• dV/dt controlled by Rg

• Driver same type as D.U.T.

• ISD controlled by duty factor “D”

• D.U.T. - device under test

D.U.T. Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

Note

a. VGS = 5 V for logic level devices

VDD

Document Number: 91344 www.vishay.com

Revision: 15-Sep-08 1

Package Information

Vishay Siliconix

TO-252AA (HIGH VOLTAGE)

Notes

1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.

2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but

including any mismatch between the top and bottom of the plastic body.

3. The package top may be smaller than the package bottom.

4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum

material condition. The dambar cannot be located on the lower radius of the foot.

D H

MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX.

E 6.40 6.73 0.252 0.265

L 1.40 1.77 0.055 0.070

L1 2.743 REF 0.108 REF

L2 0.508 BSC 0.020 BSC

L3 0.89 1.27 0.035 0.050

L4 0.64 1.01 0.025 0.040

D 6.00 6.22 0.236 0.245

H 9.40 10.40 0.370 0.409

b 0.64 0.88 0.025 0.035

b2 0.77 1.14 0.030 0.045

b3 5.21 5.46 0.205 0.215

e 2.286 BSC 0.090 BSC

A 2.20 2.38 0.087 0.094

A1 0.00 0.13 0.000 0.005

c 0.45 0.60 0.018 0.024

c2 0.45 0.58 0.018 0.023

D1 5.30 - 0.209 -

E1 4.40 - 0.173 -

θ0' 10' 0' 10'

ECN: S-81965-Rev. A, 15-Sep-08

DWG: 5973

Document Number: 91362 www.vishay.com

Revision: 15-Sep-08 1

Package Information

Vishay Siliconix

TO-251AA (HIGH VOLTAGE)

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimension are shown in inches and millimeters.

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the

outermost extremes of the plastic body.

4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.

5. Lead dimension uncontrolled in L3.

6. Dimension b1, b3 and c1 apply to base metal only.

7. Outline conforms to JEDEC outline TO-251AA.

Base

metal

Plating b1, b3

(b, b2)

(c)

Section B - B and C - C

Lead tip

(Datum A)

Thermal PAD

View A - A

Seating

plane

θ1

θ2

3 x b2

3 x b

2 x e 0.010 C B

0.25

0.010 BA

0.25

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 -

A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265

b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 -

b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC

b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380

b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090

b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050

c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060

c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15'

c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35'

D 5.97 6.22 0.235 0.245

ECN: S-82111-Rev. A, 15-Sep-08

DWG: 5968

Application Note 826

Vishay Siliconix

Document Number: 72594 www.vishay.com

Revision: 21-Jan-08 3

APPLICATION NOTE

RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)

0.420

(10.668)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.224

(5.690)

0.180

(4.572)

0.055

(1.397)

0.243

(6.180)

0.087

(2.202)

0.090

(2.286)

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Revision: 12-Mar-12 1Document Number: 91000

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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that

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