PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Detect Feature Features Description * One high-speed PCI-Express lane * Adjustable Transmiter De-Emphasis & Amplitude * Adjustable Receiver Equalization * One Spread Spectrum Reference Clock Buffer Output * Input Signal Level Detect and Output Squelch * 100 Differential CML I/O's * Low Power (100mW per Channel) * Stand-by Mode - Power Down State * VDD Operating Range: 1.8V 0.1V * Packaging (Pb-free & Green): -- 36-pad TQFN (ZF36) Pericom Semiconductor's PI2EQX4401D is a low power, PCI-Express compliant signal re-driver. The device provides programmable equalization, amplification, and de-emphasis by using 4 select bits, SEL[0:3], to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. PI2EQX4401D supports two 100 Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the PCI-express signal before the re-driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the PCI-express signal after the ReDriver. A low-level input signal detection and output squelch function is provided for both channels. Each channel operates fully independantly. When a channel is enabled (EN_x=1) and operating, that channel's input signal level (on xl+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the output driver switches off, and the pin is pulled to VDD via a high impedance resistor. In addition to providing signal re-conditioning, Pericom's PI2EQX4401D also provides power management Stand-by mode operated by a Bus Enable pin. A differential clock buffer is provided for test and other system requirements. This clock function is not used by the data channels. 08-0241 1 PS8872H 09/26/08 PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Defect FeaTure CML CML xl+ Equalizer SIG_x xO+ Limiting Amp xl+ xO- SEL[0:1] SEL[2]_x SEL0_A SEL1_A SEL2_A SEL3_A EN_A EN_B 30 29 28 VDD AI+ 2 27 A0+ AI- 3 26 A0- GND 4 25 GND AVDD 5 24 AGND VDD 6 23 VDD B0+ 7 22 BI+ B0- 8 21 BI- GND 9 20 GND VDD 10 19 IREF GND 11 12 13 14 15 16 17 18 OUT+ OUT- 2 31 SEL3_B 08-0241 32 SEL2_B IREF 33 SEL1_B OUT0OUT0+ 34 SEL0_B CLK 35 1 CLKIN- Buffer 36 VDD CLKIN+ CLKINCLKIN+ SEL SIG_B LVCMOS SIG_A Pin Description Block Diagram PS8872H 09/26/08 PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Defect Feature Pin Description Pin # 1, 6, 10, 23, 28 Pin Name VDD I/O PWR 2 AI+ I 3 AI- I 4, 9, 20, 25 GND PWR 22 BI+ I 21 BI- I 34, 33 13, 14 32 15 31 16 SEL[0:1]_A SEL[0:1]_B SEL[2]_A SEL[2]_B SEL[3]_A SEL[3]_B I I I I I I 27 AO+ O 26 AO- O 7 BO+ O 8 BO- O 30, 29 EN_[A,B] I 12 11 17, 18 5 24 CLKINCLKIN+ OUT+, OUTAVDD AGND I I O PWR PWR 19 IREF O 36, 35 SIG_A, SIG_B O 08-0241 Description 1.8V Supply Voltage Positive CML Input Channel A with internal 50 pull down during normal operation (EN_A=1). When EN_A=0, this pin is high-impedance. Negative CML Input Channel A with internal 50 pull down during normal operation (EN_A=1). When EN_A=0, this pin is high-impedance. Supply Ground Positive CML Input Channel B with internal 50 pull down during normal operation (EN_B=1). When EN_B=0, this pin is high-impedance. Negative CML Input Channel B with internal 50 pull down during normal operation (EN_B=1). When EN_B=0, this pin is high-impedance. Selection pins for equalizer (see Amplifier Configuration Table) w/ 50K internal pull up Selection pins for amplifier (see Amplifier Configuration Table) w/ 50K internal pull up Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50K internal pull up Positive CML Output Channel A internal 50 pull up during normal operation and 2K pull up otherwise. Negative CML Output Channel A with internal 50 pull up during normal operation and 2K pull up otherwise. Positive CML Output Channel B with internal 50 pull up during normal operation and 2K pull up otherwise. Negative CMLOutput Channel B with internal 50 pull up during normal operation and 2K pull up otherwise. EN_[A:B] is the enable pin. A LVCMOS high provides normal operation. A LVCMOS low selects a low power down mode. Differential Input Reference Clock. If clock buffer is not used, then both CLKIN+, CLKIN- should be pulled high to VDD. Differential Reference Clock Output 1.8V Analog supply voltage Analog ground External 475 resistor connection to set the differential output current. If the clock buffer is not used, then IREF should be unconnected (open). SIG Detector output for channel A-B. Provides a LVCMOS high output when an input signal greater than the threshold is detected 3 PS8872H 09/26/08 PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Defect Feature Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ -65C to +150C Supply Voltage to Ground Potential ................................... -0.5V to +2.5V DC SIG Voltage ..........................................................-0.5V to VDD +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 500mW Operating Temperature .............................................................. 0 to +70C Output Swing Control SEL2_[A:B] 0 1 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Output De-emphasis Adjustment Swing 1x 1.2x SEL3_[A:B] 0 1 De-emphasis 0dB -3.5dB Equalizer Selection SEL0_[A:B] 0 0 1 1 SEL1_[A:B] 0 1 0 1 Compliance Channel no equalization [0:2.5dB] @ 1.25 GHz [2.5:4.5dB] @ 1.25 GHz [4.5:6.5dB] @ 1.25 GHz Note: 1. Design target specification. Absolute values will be based on characterization. 08-0241 4 PS8872H 09/26/08 PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Defect Feature AC/DC Electrical Characteristics (VDD = 1.8 0.1V) Symbol Ps Parameter Supply Power Latency CML Receiver Input Return Loss RLRX Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage VTHSignal Detection Threshold DC Differential Input ZRX-DIFF-DC Impedance DC Input Impedance ZRX-DC Conditions EN = LVCMOS Low EN = LVCMOS High From input to output Min. 50 MHz to 1.25 GHz Typ. Max. 0.1 0.6 Units W 2.0 ns 12 dB 0.175 1.200 V 150 mV 120 175 mV 80 100 120 40 50 60 EN_x=High Equalization JRS Residual Jitter JRM Random Jitter Total Jitter (2) Deterministic jitter See note 2 0.3 0.2 1.5 Ulp-p psrms Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at 0V at point C of Figure 1. FR4 Signal Source A B SmA Connector SmA Connector Pericom PI2EQX4401A In C Out 30IN Figure 1. Test Condition Referenced in the Electrical Characteristic Table 08-0241 5 PS8872H 09/26/08 PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Defect Feature AC/DC Electrical Characteristics (TA = 0 to 70C) Symbol Parameter Conditions Min. Typ. Max. Units 650 mVp-p 150 ps CML Transmitter Output (100 differential) VDIFFP Output Voltage Swing Differential Swing | VTX-D+ - VTX-D- | VTX-C Common-Mode Voltage | VTX-D+ + VTX-D- | / 2 tF, tR Transition Time 20% to 80% (3) ZOUT Output resistance Single ended ZTX-DIFF-DC 400 VDD0.3 40 50 60 DC Differential TX Impedance 80 100 120 CTX AC Coupling Capacitor 75 200 nF VTX-DIFFP-P Differential Peak-to-peak Ouput Voltage 0.8 1.3 V 0.65 x VDD VDD VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | LVCMOS Control Pins VIH Input High Voltage VIL Input Low Voltage 0.35 x VDD IIH Input High Current 250 IIL Input Low Current 500 V A Notes 3. Using K28.7 (0011111000) patern) 4. AC specifications are guaranteed by design and characterization 08-0241 6 PS8872H 09/26/08 PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Defect Feature AC Switching Characteristics for Clock Buffer (VDD = 1.8 0.1V, AVDD = 1.8 0.1V) Symbol Trise / Tfall Trise / Tfall Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Min Max. 125 525 Rise and Fall Time Variation 75 VHIGH Voltage High including overshoot 660 VLOW Voltage Low including undershoot -200 Absolute crossing point voltages 200 VCROSS VCROSS TDC Total Variation of Vcross over all edges Units 1 ps 900 550 45 55 1 1 mV 250 Duty Cycle (input duty cycle = 50%) Notes 1 1 1 % 2 Notes: 1. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3. Test configuration is RS = 33.2, Rp = 49.9, and 2pF. Configuration Test Load Board Termination Rs 33 5% Clock TLA CLKBUF Rs 33 5% Clock# TLB Rp 49.9 1% 475 1% Rp 49.9 1% 2pF 5% 2pF 5% Figure 2. Configuration test load board termination Note: 1. TLA and TLB are 3" transmission lines. 08-0241 7 PS8872H 09/26/08 PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Defect Feature Packaging Mechanical: 36-pad TQFN (ZF36) Notes: 1) All dimensions are in millimeters, angles in degrees 2) Bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 3) Ref JEDEC: MO-220I/WJHD 4) Thermal Via Diameter. Recommended 0.2~0.33mm 5) Thermal Pitch. Recommended 1.27mm DATE: 4/28/06 DESCRIPTION: 36-contact, Very Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZF36 REVISION: B DOCUMENT CONTROL #: PD-2023 Ordering Information Ordering Number Package Code Package Description PI2EQX4401DZFE ZF Pb-Free and Green 36-pad TQFN Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 08-0241 8 PS8872H 09/26/08