Z9974AAB - Cypress Semiconductor Corp.

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 1 of 9

http://www.imicorp.com

Product Features

• PLL controlled zero input-output propagation delay

• 15 low skew high drive Low Voltage CMOS outputs

• Programmable output frequency Up to 125MHz.

• 3.3V power supply

• +/- 100 pS Cycle to Cycle jitter

• Configurable Output Disable, Tri-state (Hi-Z), PLL

Bypass, and test modes.

• Two reference clock inputs for dynamic reference

toggling.

• Designed to drive 50 Ohm parallel terminated

transmission lines on the incident edge.

• Available in 52 pin TQFP package.

• 2KV ESD inputs

• Glitch-free output clocks transitioning between

frequencies.

Product Description

The Z9974 is a low cos t 3.3V zero delay c lock dr iver f or

high speed signal buffering and redistribution.

It provides the designer with the flexibility of selecting

various Output/Input Frequenc y ratios selected by fsela,

fselb, fselc, fselFB(0:1), and VCO_sel input settings.

The Z9974 integrates PLL technology for Zero delay

propagation from Input to Output. The PLL feedback is

externally available for propagation delay tuning and

divide ratio alternatives as per table 1.

The Z9974 has thr ee banks of outputs with independent

divider stages. These dividers allow the banks to have

different frequencies as per table 2.

TCLK0 and TCLK1 one are selectable input reference

clock s and may be toggled dynamic ally during operation

to provide modulation and phase shifting designs.

This device includes a Master Reset signal which

disables the outputs into Tris tate ( Hi-Z) mode, and res et

all internal digital circuitry (excluding the PLL).

An Output Enable, OE, input pin is available f or s hutting

Qa(0:4), Qb(0:4) , and Qc(0:3) outputs in a low state. All

outputs are held low with input clock turned off.

Feedback Ratio Selection Table

Inputs Outputs

VCO_Sel fselFB0 fselFB1 QFB

000VCO/8

001VCO/12

010VCO/16

011VCO/24

100VCO/16

101VCO/24

110VCO/32

111VCO/48

Table 1

Pin Configuration

VSSA

MR#

fselb

fselc

PLL_EN

fsela

TClk_Sel

TClk0

TClk1

VDDI

VDDA

VDDa

Qa0

VSSa

Qa1

VDDa

Qa2

fselFB1

VSSa

Qa3

VDDa

Qa4

VSSI

fselFB0

Qb0

VDDb

VSSc

Qc3

VDDc

QC2

VSSc

QC1

VDDc

QC0

VSSc

VCO_Sel

VSSb

QB1

VDDb

Qb2

VSSb

Qb3

VDDb

Qb4

FB_IN

VSSFB

QFB

VDDFB

14 15 16 17 18 19 20 21 22 23 24 25 26

52 51 50 49 48 47 46 45 44 43 42 41 40

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 2 of 9

http://www.imicorp.com

Block Diagram

Fig.1

VDD

250K

Divide by

2 & 4

Divide by

2, 4 & 6

Div. by 2

AND

Gate

250K

PLL

Ref-in

VCO-out

Feedback

250K

TCLK0

TCLK1

FB_In

PLL_EN

VCO_sel

QFB

Qa(0:4)

Qb(0:4)

Qc(0:3)

MR#

fsela

TCLK_sel

fselc

fselb

fselFB1

fselFB0

Reset#

PLLinit#

AND

Gate

AND

Gate

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 3 of 9

http://www.imicorp.com

Output Frequency Selection Table

Inputs Outputs

VCO_sel fsela fselb fselc Qa(0:4) Qb(0:4) Qc(0:3)

0 0 0 0 VCO/4 VCO/4 VCO/8

0 0 0 1 VCO/4 VCO/4 VCO/12

0 0 1 0 VCO/4 VCO/8 VCO/8

0 0 1 1 VCO/4 VCO/8 VCO/12

0 1 0 0 VCO/8 VCO/4 VCO/8

0 1 0 1 VCO/8 VCO/4 VCO/12

0 1 1 0 VCO/8 VCO/8 VCO/8

0 1 1 1 VCO/8 VCO/8 VCO/12

1 0 0 0 VCO/8 VCO/8 VCO/16

1 0 0 1 VCO/8 VCO/8 VCO/24

1 0 1 0 VCO/8 VCO/16 VCO/16

1 0 1 1 VCO/8 VCO/16 VCO/24

1 1 0 0 VCO/16 VCO/8 VCO/16

1 1 0 1 VCO/16 VCO/8 VCO/24

1 1 1 0 VCO/16 VCO/16 VCO/16

1 1 1 1 VCO/16 VCO/16 VCO/24

Table 2

PIN DESCRIPTION

PIN No. Pin Name I/O Description

2MR# IActive low Master Reset pin. It has a 250KΩ internal pull-up. When forced low, all outputs

are Tri-stated (high impedance) and internal ratio dividers are reset.

3OE IActive high Output Enable pin. It has a 250KΩ internal pull-up. When forced low, Qa(0:4),

Qb(0:4), and Qc(0:3) outputs are stopped in a low state. QFB is not effected by this signal.

7,4, 5 Fsel(a,b,c) I Input select pins for setting the output dividers at Qa(0:4), Qb(0:4), and Qc(0:3)

respectively. Each pin has an internal 250KΩ pull-down. See table 2, page 3.

6PLL_EN IInput pin for bypassing the PLL. It has an internal 250KΩ pull-up. When forced low,

the input reference clock (applied at TCLK0, or TCLK1) bypasses the PLL and drives the

dividers, typically for device testing. In this case, the PLL is disabled.

8TCLK_sel I Input pin for selecting TCLK0 or TCLK1 as input reference. When TCLK_sel = 0, TCLK0 is

selected, when TCLK_sel = 1, TCLK1 is selected. This pin has a 250KΩ internal pull-down.

9,10 TCLK(0:1) I Input pins for applying a reference clock to the PLL. The active input is selected by

TCLK_sel, pin# 8. TCLK0 has a 250KΩ internal pull-down. TCLK1 has a 250KΩ internal

pull-up.

14, 20 FselFB(0:1) I Input select pins for setting the Feedback divide ratio at QFB output, pin#29. See table 1,

page1. Each of these pins has a 250KΩ internal pull-down.

25,23,21,

18,16 Qa(0:4) O High drive, Low Voltage CMOS, Output clock buffers, Bank Qa. Their divide ratio is

programmed by fsela, pin#7.

29 QFB O Low Voltage CMOS output feedback clock to the internal PLL. The divide ratio for this

output is set by fsleFB(0:1). A delay capacitor, or trace may be applied to this pin in order

to control the Input Reference/Output Banks phase relationship.

31 FB_In I Feedback input pin. Typically connects to the QFB output for accessing the Feedback to

the PLL. It has a a 250KΩ internal pull-up.

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 4 of 9

http://www.imicorp.com

PIN DESCRIPTION (Cont.)

PIN No. Pin Name I/O Description

40,38,36,

34,32 Qb(0:4) O High drive, Low Voltage CMOS, Output clock buffers, Bank Qb. Their divide ratio is

programmed by fselb, pin#4.

50,48,46,

44 Qc(0:3) O High drive, Low Voltage CMOS, Output clock buffers, Bank Qc. Their divide ratio is

programmed by fselc, pin#5.

52 VCO_Sel IInput select pin for settin

the divider of the VCO output. It has a 250KΩ internal pull-down.

If VCO_sel = 0, then the PLL VCO output is divided by 2. If VCO_sel = 1, then the PLL

VCO output is divided by 4. See fig.1, page2; table 1, page1, table 2, page 3.

11,27,42 n/c - These pins are not connected internally. They may be attached to a ground plane.

12 VDDI P Power for input logic circuitry.

15 VSSI P Ground for input logic circuitry.

13, VDDA P Power and Ground supply pins for internal Analog circuitry.

17,22,26 VDDa P 3.3V supply for Qa(0:4) output bank, and fselFB1 input.

19,24 VSSa P Common ground for Qa(0:4) output bank, and fselFB1 input.

28, 30 VDDFB / VSSFB P Power and ground supply pins for QFB output and FB_In input pins and digital circuitry.

33,37,41 VDDb P 3.3V supply for Qb(0:4) output bank.

35,39 VSSb P Common ground for Qb(0:4) output bank.

45,49 VDDc P 3.3V supply for Qc(0:3) output bank and VCO_sel pin.

43,47,51 VSSc P Common ground for Qc(0:3) output bank and VCO_sel pin.

1VSSA P Analog Ground

A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass

capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductances of

the traces.

Glitch-Free Output Frequency Transitions

Customarily w hen zero delay buffers have their internal counter’s changed “on the fly’ their output clock periods will:

A. Contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either

the old or new frequency that is being transitioned to.

B. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old

or new frequency that is being transitioned to.

This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic

levels of any or all of the following pins changed “on the fly” while it is operating: Tclk_Sel, Fsela, Fselb, Fselc, VCO_Sel,

FselFB!, and FselFB2.

Maximum Ratings

Input Voltage Relative to VSS: VSS-0.3V

Input Voltage Relative to VDD: VDD+0.3V

Storage Temperature: -40°C to + 125°C

Operating Temperature: 0°C to +70°C

Maximum Power Supply: 5.6V

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

field; however, precautions should be taken to avoid

application of any voltage higher than the maximum

rated voltages to this circuit. For proper operation, Vin

and Vout should be constrained to the range:

VSS<(Vin or Vout)<VDD

Unused inputs must always be tied to an appropriate

logic voltage level (either VSS or VDD).

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 5 of 9

http://www.imicorp.com

DC Parameters

Characteristic Symbol Min Typ Max Units Conditions

Input Low Voltage VIL VSS - 0.8 Vdc

Input High Voltage VIH 2.0 - VDD Vdc Applicable to all input signals.

Input Low Current IIL 51.1 µA VIN† = 1V

Input High Current IIH ±100 µA VIN† = VDD

Output Low Voltage VOL 0.5 V IOL = 20 mA

Output High Voltage VOH 2.4 V IOH = - 20mA

Tri-State leakage Current Ioz - - 11 µA MR# = 0

Dynamic Supply Current Idd - - 120 mA

Power Up Ramp tpr 20,000 - 250 µS Measured between 0.3 and 3.0 volts

Input Pin Capacitance Cin - - 8 pF Per input

Power dissipation capacitance Cpd - 25 - pF Per output

VDD* =3.3V + 5%, TA = 0°C to +70°C

† VIN: Voltage of Signal applied to the input under test.

VDD* represents all VDD supplies tied together

PLL AC Parameters

Characteristic Symbol Min Typ Max Units Conditions

Maximum PLL Lock Time tLOCK 10 mS Stable power supply & valid clocks

presented on TCLK(0:1) pins.

VCO Lock Range fVCO 200 500 MHz FselFB(0:1) = /4 to /12

TCLK(0:1) input rise / fall

time Tinr, Tinf 3 nS

Input Reference frequency fREF 10 63 MHz At TCLK(0:1)*

Input Reference duty cycle fREFpw 25 75 %

VDD* = 3.3V + 5%, TA = 0°C to +70°C

*Input Reference Frequency is limited by the divider selection and the VCO lock range.

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 6 of 9

http://www.imicorp.com

AC Parameters

Characteristic Symbol Min Typ Max Units Conditions

Output Duty Cycle Tpw Tcycle/2

- 800 Tcycle/2

+ 500 Tcycle/2

+ 800 pSec Measured @ VDD/2

Rise Time / Fall Time Tr, Tf0.15 - 1.5 nSec Measured between 0.8V and 2.0V

Output Impedance Zo710

Ω

Output to Output Skew Ts- - 350 pSec All output equally loaded

Propagation Delay,

TCLK(0:1) to FBIN Tpd -250 - 100 pSec Measured for 50MHz at VDD/2

Cycle to Cycle Jitter tj - +100 - pSec Measured for 50 MHz at VDD/2

Output Disable Time tPLZ,

tPHZ 2 - 10 nSec After MR# goes low

Output Enable Time tPZL 2 - 10 nSec After MR# goes High

Maximum Output

Frequency FMAXQa

FMAXQb

FMAXQc

- - 125

125

MHz Fsel(a,b,c) = 000, VCO_sel = 0,

VDD* = 3.3V + 5%, TA = 0°C to +70°C

Note: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters

specified with loaded outputs. Z9974 outputs can drive series or parallel terminator 50 Ω (or 50 Ω to VDD/2).

Test Circuit Diagram

NOTE: All buffer outputs are tied to a common 3.3 Volt VDD (VDD*) for testing purposes

PROBE

VDD*

Impedance

7Ω

ΩΩ

Ω

Output under Test

43 50

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 7 of 9

http://www.imicorp.com

Package Drawing and Dimensions (52 TQFP)

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 8 of 9

http://www.imicorp.com

Package Drawing and Dimensions (Cont.) 52 Pin TQFP Dimensions

INCHES MILLIMETERS

SYMBOL MIN NOM MAX MIN NOM MAX

A - - 0.005 - - 1.20

A1 0.002 0.004 0.006 0.05 0.10 0.15

A2 0.037 0.039 0.041 0.95 1.00 1.05

e 0.026 BSC 0.65 BSC

D 0.472 BSC 12.00 BSC

D1 0.394 BSC 10.00 BSC

E 0. 472 BSC 12.00 BSC

E1 0.394 BSC 10.00 BSC

L 0.018 0.024 0.030 0.45 0.60 0.75

b 0.009 0.013 0.015 0.22 0.32 0.38

b1 0.009 0.012 0.013 0.22 0.30 0.33

ccc - - 0.004 - - 0.10

ddd - - 0.005 - - 0.13

Notes:

1. All dimensioning and tolerancing conform to ANSI

Y14.5-1982.

2. Datum Plane located at mold parting line

and coincident with lead. Where lead exits plastic

body at bottom of parting line.

3. Datums and to be determined at

centerline between leads where leads exit plastic

body at datum plane.

4. To be determined at seating plane

5. Dimensions D1 and E1 do not include mold

protrusion. Allowable mold protrusion is 0.254mm

on D1 and E1 dimensions.

6. “N” is the total number of terminals (in this case 52).

7. These dimensions to be determined at Datum

Plane

8. The top of package is smaller than the bottom of

package by 0.15mm.

9. A dimension “b” does not include Dambar

protrusion. Allowable Dambar protrusion shall be

0.08mm total in excess of the “b” dimension at

maximum material condition. Dambar cannot be

located on the lower radius or the foot.

10. Controlling dimension: millimeter.

11. Maximum allowable die thickness to be assembled

in this package family is 0.30mm.

12. This outline conforms to Jedec publication 95

registration MS026, variations ACB, ACC, ACD and

ACE.

13. A1 is defined as the distance from the seating plane

to the lowest point of the package body.

Z9974

Zero Delay Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.1 9/1/1999

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 9 of 9

http://www.imicorp.com

Ordering Information

Part Number Package Type Production Flow

Z9974AAB 52 TQFP Commercial, 0°C to +70°C

Note: The ordering part number is formed by a combination of device number, device revision, package style, and

screening as shown below.

Marking: Example: IMI

Z9974

Date Code, Lot #

Z9974AAB Flow

B = Commercial, 0°C to + 70°C

Package

A = TQFP

Revision

IMI Device Number