Reed-Solomon Decoder Page 1 of 3 Home > Products > Intellectual Property > Lattice IP Cores > Reed-Solomon Decoder Reed-Solomon Decoder Overview Reed-Solomon codes are used to perform Forward Error Correction. FEC encoders introduce redundancy in data before it is transmitted. The redundant data (check symbols) are transmitted along with the original data through the channel. A Reed-Solomon decoder at the receiver is used to recover any corrupted data. This type of error correction is widely used in data communications applications such as hard disk and media storage (CD) systems, Digital Video Broadcast (DVB) and Optical Carriers (e.g. OC-192). The codes are represented by the format RS(n,k) where n is the total number of s-bit wide symbols, and k is the number of s-bit wide information (data) symbols in a codeword. The Reed-Solomon Decoder performs detection and correction of encoded data available at the receiver after demodulation. The RS encoded data is then processed to determine whether any errors have occurred during transmission. Once the number of errors is determined, the decoder decides if they are within the range of correction. After determining this, the decoder corrects the errors in the received data. A typical application of space signal processing is shown in Figure 2. Features Forward Error Correction (FEC) for Communication and Common Applications Selectable Reed-Solomon Standards CCSDS (255,223) . Consultative Committee for Space Data Systems ATSC (207,187) . Advanced Television Systems Committee DVB (204,188) . Digital Video Broadcasting OC-192 (255,239) . Optical Carrier Shortened Codes Supported Errors/Erasures Supported Supports Symbol Widths From 3 to 12 Bits, Corresponding to GF(8) to GF(4096) Respectively User-Defined and Default Field and Generator Polynomials Supported Error Measurement Information http://www.latticesemi.com/products/intellectualproperty/ipcores/reedsolomondecoder.cfm 10/17/2011 Reed-Solomon Decoder Page 2 of 3 Evaluation Configurations 1 Performance and Resource Utilization for ORCA 4 Parameter File Mode PFUs LUTs2 Registers SysMEM EBRs fMAX (MHz) External Pins reeds_deco_o4_1_001.lpc OC192 321 1595 918 2 83 35 reeds_deco_o4_1_002.lpc CCSDS 621 2627 1565 2 76 36 reeds_deco_o4_1_003.lpc DVB 330 1764 911 2 85 35 reeds_deco_o4_1_004.lpc ATSC 423 2139 1072 2 84 35 1 Performance and utilization characteristics are generated using an OR4E042BA352 in ispLEVERTM software v.3.0. Synthesized using Synplicity Synplify, v.7.0.3. When using this IP core in different density, package, speed, or grade within the ORCA 4 family, performance may vary slightly. 2 LUT is a standard logic block of some Lattice devices. For more information, check the data sheet of the device. 1 Performance and Resource Utilization for XPGA Parameter File ispXPGA Mode 2 PFUs LUTs Registers SysMEM EBRs fMAX (MHz) External Pins reeds_deco_xp_1_001.lpc OC192 571 2034 1033 2 83 35 reeds_deco_xp_1_002.lpc CCSDS 1011 3660 1717 2 76 36 reeds_deco_xp_1_003.lpc DVB 586 2089 1049 2 84 35 reeds_deco_xp_1_004.lpc ATSC 712 2536 1286 2 80 35 1 Performance and Utilization characteristics are generated using LFX500B-04F516C. When using this IP core in different density, package, speed, or grade within the ispXPGA family, performance may vary slightly. 2 PFU is a standard logic block of some Lattice devices. For more information, refer to the data sheet of the device. 1 Performance and Resource Utilization for LatticeECP and LatticeEC Parameter File Mode SLICEs LUTs Registers I/Os2 sysMEM EBRs fMAX (MHz) reeds_deco_e2_1_001.lpc OC192 812 1188 792 35 2 110 reeds_deco_e2_1_002.lpc CCSDS 1389 1950 1419 36 2 102 reeds_deco_e2_1_003.lpc DVB 816 1202 793 35 2 113 reeds_deco_e2_1_004.lpc ATSC 1053 1491 991 35 2 103 1 Performance and utilization characteristics are generated using LFEC20E-5F672C in Lattice's ispLEVER v.4.1 software. When using this IP core in a different device, density, package, or speed grade, performance may vary. 2 The I/Os for these configurations include the optional signals d_del and err_cnt. The width of the err_cnt signal bus is 5 for the CCSDS configuration, and 4 for the other evaluation configurations. Ordering Information Part Numbers: For ORCA4: REEDS-DECO-O4-N1 For XPGA:REEDS-DECO-XP-N1 For LatticeECP/EC: REEDS-DECO-E2-N1 http://www.latticesemi.com/products/intellectualproperty/ipcores/reedsolomondecoder.cfm 10/17/2011 Reed-Solomon Decoder Page 3 of 3 To find out how to purchase the Reed-Solomon Decoder IP Core, please contact your local Lattice Sales Office. http://www.latticesemi.com/products/intellectualproperty/ipcores/reedsolomondecoder.cfm 10/17/2011