PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications f Description Features PD70211 is an advanced PD Interface IC with integrated switching (PWM) regulator control for Powered Devices in PoE applications. It supports IEEE802.3af, IEEE802at, HDBaseT and general 2/4-pair configurations. Supports IEEE802.3af/at, HDBaseT and other 2pair/4-pair configurations Wall-adapter support (Rear Aux method) PD detection & programmable classification 2,3,4, and 6 event classification Integrated 0.3 isolating (series-pass) FET Inrush current limiting The PD70211 front-end includes an advanced classification block that supports 2, 3, 4, and 6 event classification. Using the SUPP_Sx pins, it also identifies which of the four pairs of the cable actually receives power and generates appropriate flags. Less than 10A offset current during detection Advanced PWM section Lead-free MLPQ-36 (6 x 6 mm) package The IC features an internal bleeder for discharging the input capacitor of the DC/DC converter rapidly, so as to ensure fast re-detection and port power-up in case of sudden removal and re-insertion of the Ethernet cable into the RJ-45. The advanced PWM currentmode section supports synchronous Flyback and Active clamp Forward topologies, as well as Buck, Boost etc. . Applications HDBaseT up to 95 Watts IEEE802.3af and 802.3at Power Forwarding Indoor and outdoor PoE BOOST CONVERTER (FOR 0.6A, PoE Applications) STAND-ALONE PD SOLUTION FOR POWER FORWARDING 57V/0.6A VPP 120H/1.5A 10F/ 25V 0.1F/ 25V 0.1F/10V VCC VPortP1 31 32 0.1F/10V 0.1F/10V VPP 25 17 18 VH VAUX_VCC VL 330F/63V/ Aluminum PD70211 (PWM SECTION) PG CSP SS CSN SMAJ58A 0.1F/100V VPN 13 562k 562k 49.9k VPP 1nF 28 21 21.5k 2nF 330pF 215k 237k 4.99k 16 RFREQ 35 VPP SG 26 GND PGND SYNC 15 24 27 PD70211 (Front-End SECTION) 32 VAUX_VCC WA_EN 33 VPN RDET SUPP_S1 1 SUPP_S1 24.9k 1% 36 30.9k 243k 5 4 VPN Loop compensation will need to be tweaked 100pF 23 VINS VSN VSP DAO 22 19 20 VPN 29 18.7k HYST 14 SUPP_S2 VPortN2 ENABLE FB VPortP2 Si7852ADP 100 (Four 2.4/1W) 4 x ERJ-1TYJ2R4U COMP 12 10 30 RCLP SUPP_S1 VPortN1 3A/80V RCLASS RREF 8 , 9 VPN_IN EPAD (Pin 37) SUPP_S2 2 SUPP_S2 AT_FLAG 7 AT_FLAG 4P_AT_FLAG 3 HD_FLAG 6 4P_AT_FLAG 4P_HD_FLAG 34 4P_HD_FLAG HD_FLAG VPN_OUT 10 , 11 Figure 1: Typical Applications Diagram (PD70211) Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 1 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications RDET VPP 4P_HD_FLAG WA_EN VAUX_VCC VH PG CSP CSN Pin Configuration 36 35 34 33 32 31 30 29 28 PD70211 (Top view) 27 PGND 26 SG 25 VL 24 GND 23 FB 22 DAO 7 21 COMP VPN_IN 8 20 VSP VPN_IN 9 19 VSN 5 HD_FLAG 6 AT_FLAG 10 11 12 13 14 15 16 17 18 RCLP RCLASS EPAD (Pin 37) SS 4 RFREQ RREF SYNC 3 HYST 4P_AT_FLAG VINS 2 ENABLE SUPP_S2 VPN_OUT 1 VPN_OUT SUPP_S1 Figure 2: Pinout of PD70211 (top view) Ordering Information Ambient Type Temperature -40C to 85C Copyright (c) 2016 Rev. 1.4, July 2017 RoHS compliant, Pb-free Part Marking Ordering P/N Package MSCC Logo 70211 Assembly site and production revision identifiers Date/Lot Code PD70211ILQTR MLPQ-36 (6 mm x 6 mm, 0.5mm pitch) Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Note Page 2 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Description (PD70211) Pin Number Designator Description SUPP_S1 Input pin for sensing the voltage on the diode bridge connected to the data pairs. This pin along with the SUPP_S2 pin can be used to distinguish between 2-pair and 4-pair operation. (For PSEs that operate in 4 pairs but do not generate the classification procedure on both pair but one pair only). Signal is referenced to VPN_IN. Place a 10k resistor in the input of this pin. SUPP_S2 Input pin for sensing the voltage on the diode bridge connected to the data pairs. This pin along with the SUPP_S1 pin can be used to distinguish between 2-pair and 4-pair operation. (For PSEs that operate in 4 pairs but do not generate the classification procedure on both pair but one pair only) . Signal is referenced to VPN_IN. Place a 10k resistor in the input of this pin. 3 4P_AT_FLAG Open Drain Output. The pin gets actively pulled low when a 4-pair version of a (nonstandard) Type 2 PD-PSE mutually identifies each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT 4 RREF Bias current resistor. A 60.4k, 1% resistor is connected between RREF and IC ground (VPN_IN) RCLASS Sets the Class of the PD. Connect RCLASS (programming resistor) between this pin and IC ground (VPN_IN). Allowed values are 133 , 69.8 , 45.3 , and 30.9 for Class 1, 2, 3, and 4 respectively. If RCLASS is not present, the PD will draw up to 3 mA during classification, thus indicating Class 0 (default Type 1) to the PSE. Signal is referenced to VPN_IN HD_FLAG Open Drain Output. The pin gets actively pulled low when a 2-pair HDBaseT PD-PSE mutually identify each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT 7 AT_FLAG Open Drain Output. This pin gets actively pulled low when a Type 2 PD-PSE mutually identifies each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT 8, 9 VPN_IN Lower rail of the incoming PSE voltage rail - from the negative terminal of the two OR-ed bridge rectifiers (the corresponding upper PoE rail is VPP) 10, 11 VPN_OUT This is in effect, the switched ground for establishing continuity to the PWM section after successful detection, classification, and Power-up. It is connected to the Power ground and PWM controller IC's ground plane of the DC-DC converter section 1 2 5 6 Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 3 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Number 12 13 14 15 Copyright (c) 2016 Rev. 1.4, July 2017 Designator Description ENABLE A logic-level input to enable the converter. We can pull it constantly up, say with a 100k resistor to VDD, to forcibly enable the converter. Provided the input supply has exceeded any applicable UVLO thresholds, of course, as set on the VINS pin or on the VCC pin. Internally, the ENABLE pin actually goes to the input of an OR-gate, the other input terminal of which is tied to "POK" - a signal provided by the front-end. If the ENABLE pin is forced high, the output of the OR-gate goes high and the converter is allowed to start (provided all UVLO's are past of course). If the ENABLE pin is held low, the internal node "POK" goes active high when the PD's front end conducts (power OK), so the OR-gate goes high once again. In this case the switching converter turns ON naturally and correctly as required by the PoE standard. However, for supporting wall-adapters, injecting power after the frontend (at the input of the converter), we can forcefully turn the converter ON without the front-end signaling "PGOOD", by not tying the ENABLE pin low, but by tying it high (to VDD). That will turn ON the converter irrespective of the state of the front-end (conducting or not), and whether there is any incoming PoE power or not. VINS The VINS pin is a programmable UVLO pin. The converter will turn ON provided the voltage on the VINS pin is above 1.2V (and VCC is not in UVLO, and ENABLE pin is also high - connected to VDD for example). The converter will stop switching (turn OFF) when the voltage on the VINS pin falls below 1.2V (or if ENABLE is taken low, or if VCC falls outside its operating range). Thus by connecting a voltage divider between input rail and IC ground, we can set the UVLO threshold to enable switching. However, to have a smooth startup, it is advisable to have some hysteresis too, by means of a resistor between VINS and HYST as explained below. HYST This is the output of the UVLO comparator as shown in the Block Diagram. We connect a "hysteresis resistor" from HYST pin to VINS pin to create positive feedback (and hysteresis). Initially, as the input voltage is rising, the VINS pin voltage is below 1.2V and so the output of the UVLO comparator is low, and the hysteresis resistor falls in parallel to the lower resistor of the UVLO divider placed at the VINS pin, assisting it by pulling down the VINS pin voltage further. As soon as the rising UVLO threshold is exceeded (VINS > 1.2V), the output of the UVLO comparator suddenly goes high (up to VDD) and the hysteresis resistor, effectively comes partially across the upper resistor of the UVLO divider, assisting it in the act of pulling up on the VINS pin. This feedback therefore increases the voltage on the VINS pin. And so, now the input rail has to fall to a much lower level to allow the VINS pin voltage to fall below 1.2V. That is how hysteresis is created by positive feedback action through the hysteresis resistor. The exact math is in the applications information of this datasheet. Note that HYST pin always toggles high or low depending on whether the voltage on the VINS pin is above or below 1.2V respectively. This can always be used to simultaneously drive an opto, to indicate when the input rail is above the programmed rising threshold and when it falls below the programmed falling threshold. SYNC Used to synchronize the LX7309 to a frequency higher than its default value as set on RFREQ pin. The synchronizing clock must be 2x the desired sync frequency, with a maximum synchronizing clock frequency of 1MHz (for 500kHz PWM frequency). The PG pin's rising edge will occur at the same instant as the rising edge of the clock being applied on the SYNC pin. Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 4 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Number Designator Description Connect a programming resistor from this pin to IC ground (pin GND) to set the switching frequency. A typical value of the programming resistor is 49.9k, and this value will provide a frequency between 215kHz. Halving it will roughly double the frequency, whereas doubling it will halve the frequency. Note that the converter is designed to operate from 100 to 500 kHz based on this pin. Switching Frequency Equation: 16 RFREQ = 1 (90 x )+ 150 where Freq is [Hz] and RFREQ in [] For further information refer to Setting Switching Frequency. 17 18 19 20 Copyright (c) 2016 Rev. 1.4, July 2017 SS This is the soft-start pin. Typically a 0.1F cap, the "soft-start capacitor", is connected between this pin and IC ground (pin GND). The capacitor gets charged up to 1.2V by an internal resistor, and the voltage on the cap in effect forms the input voltage reference VREF of the error amplifier. But note that this capacitor serves other functions too; for example, it controls the rate of hiccupping under overcurrent fault conditions. So even if the internal reference is not being used (as in isolated topologies with a TL431 on the Secondary side), the soft-stat cap is always recommended to be in place. The actual capacitor used will be determined by the application. For further information refer to Setting Soft-Start. RCLP Low power clamp resistor. We can connect a resistor from this pin to IC ground (pin GND) to set the exact level at which pulse-skipping mode is entered at light loads. However, the usual default is to connect this pin directly to IC ground, in which case pulse-skipping mode is disabled. The method to select the threshold (and RCLP resistor value) is described in the Applications Information section of this datasheet. VSN The negative input of the internal differential-sense voltage amplifier. Note that the common-mode range of the differential voltage amplifier is 3.5V and its gain is 7. We can use this differential amplifier for implementing topologies where the "system (output) ground" is different from the IC ground. We can then step-down both output rails (output rail and its return), by equal amounts, using identical voltage dividers, to bring the voltage below 3.5V, then use differential sensing, and finally connect the output of the differential voltage amplifier (pin DAO) to FB pin. VSP The positive input of the internal differential-sense voltage amplifier. Note that it must always be connected in such a way that VSP is at a higher voltage than VSN. Also keep in mind that since the differential voltage amplifier has a gain of 7 and the output of that amp is connected to the feedback pin which compares that against a 1.2V reference, in effect, the difference between VSP and VSN stabilizes to 1.2V/7 = 0.171V in steady state. That is how we design the (identical) voltage dividers present on VSP and VSN. Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 5 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Number 21 22 23 24 25 26 27 Copyright (c) 2016 Rev. 1.4, July 2017 Designator Description COMP This is the output of the internal error amplifier, and the input of the PWM comparator. It is brought out to support isolated topologies because in such cases, there is an error amplifier already present on the Secondary side (for example a TL431 or equivalent). Therefore we want to bypass the error amplifier of the converter section. On the other hand, in nonisolated topologies, we want to use the error amplifier of the converter. We can do that directly, or through the differential voltage amplifier stage. DAO This is the output of the internal differential voltage amplifier (gain = 7). When this amplifier is used, we connect DAO to the feedback pin (FB). We have part of the compensation network between the two pins, and this network is typical of any Type 3 error amplifier input, with or without a differential amplifier present. FB This is the feedback pin of the IC. It is internally compared to a 1.2V reference. If the internal error amplifier is not used and the COMP pin is being used to inject the error signal (as in isolated topologies), the FB pin can be either tied high (to VDD), or connected to COMP. GND This is the IC ground. In more detail this is the analog (quiet) ground of the IC. Pin 20 is the Power ground (PGND). Typically, we can connect the analog ground and PGND together on a copper island on the component side, and then connect that through several vias very close to the chip on to a large ground plane which extends up to the lower side of the current sense resistor. All chip decoupling can then be very simply with respect to the copper island on the component side. VL This is created by an internal LDO and basically provides a housekeeping rail for the IC itself, which is 5V with respect to the IC ground. A 1F ceramic cap placed close to this pin, connected to IC ground is recommended for proper decoupling. This pin can also provide up to 5mA for external circuitry if required, thermal aspects (IC dissipation) being considered. SG Secondary Gate driver. We can use this to drive a synchronous FET or an active clamp FET. It is derived from VCC (~ 12V), and has a 10 limiting resistor. So it can be used to drive a Gate-drive transformer directly. It is usually complementary to the Primary Gate driver pin (PG). But there is a typical 110ns blanking time between the two to prevent crossconduction. SG is held firmly low in pulse-skip mode (if allowed). It is also low during softstart. It allows forced PWM (continuous conduction) mode by allowing negative inductor currents. It does not support diode-emulation mode (discontinuous conduction mode). However, in pulse-skip mode, since SG stays OFF, the converter automatically lapses into discontinuous conduction mode through the body-diode of the synchronous FET. We can leave this pin floating if unused. PGND Power ground (for internal SG and PG drivers). This is also best for VCC decoupling, and the Primary-side current sense resistor's lower terminal. We can also combine GND an PGND on to a single large ground plane. Note that Power ground plane is firmly connected to VPN_OUT, which is the Drain side of the PD's low-side pass-FET (it stands for Negative Port Voltage Out). Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 6 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Number Designator Description CSN The negative input of the internal current-sense voltage amplifier. Note that the commonmode range of the differential current-sense amplifier is 2V and its gain is 5. We can use this for high-side current sensing up to 2V. It is then placed on the (steady) output side of a Buck inductor, and the max output voltage is 1.8V for using this type of sensing. Ensure that CSN is at a lower voltage compared to the positive input of the current-sense amplifier (CSP). Current sensing can also be implemented in a more basic fashion for "low-side" sensing, with a resistor in the return (ground) of the Buck. In that case CSN is shown connected to IC ground. However, to avoid noise from ground bounce, it is best to route this on the PCB in Kelvin manner to the lower end of the sense resistor. This is important because the peak operating voltage on the sense resistor is only 200mV and PCB-related noise can cause jitter in the switching waveform in current-mode control. CSP The positive input of the internal current-sense voltage amplifier. See discussion for Pin 28 (CSN) above. Note that the output of the current-sense amplifier is amplified 5 times. So a 0.2V current-sense voltage translates to a 1V swing at the input of the PWM comparator. Higher voltages lead to hiccup mode protection. 30 PG This stands for Primary Gate driver. We can use this to drive the main FET, and it has a 5 or 10 limiting drive resistor switched between a voltage close to VCC rail and the IC ground. For guaranteeing proper shutdown during OFF time, it is necessary to add a 470k resistor from PG to VINS, as shown in Figure 1. 31 VH Internal rail of -5V with respect to VCC, brought out only for decoupling purposes. Connect a 0.1F ceramic cap very close, from this pin to VAUX_VCC pin. VAUX_VCC Auxiliary voltage rail from front-end to the VCC (supply) input of the PWM section. The front-end provides a few mA of startup current for the PWM controller (at typically 10.5V). Signal is referenced to VPN_OUT and is activated once front end power up sequence is end. After initial startup of PWM section, a bias winding can be connected to this pin through a diode, to sustain the PWM section. WA_EN While this input is low (referenced to VPN_IN) the chip work according to internal flow diagram. When this input is high, it enable wall adapter feature. Place 100nF/10V capacitor from WA_EN to VPN_IN pins, locate it close to device. When WA_EN is not used, connect it to VPN_IN. For further information, refer to External source connected to PD device output. 34 4P_HD_FLAG Open Drain Output. The pin gets actively pulled low when a 4-pair HDBaseT PD-PSE mutually identify each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT 35 VPP Upper rail of the incoming PSE voltage rail - from the positive terminal of the two OR-ed bridge rectifiers (the corresponding lower PoE rail is VPN_IN) 36 RDET Internally connects to VPN_IN during detection phase and disengages after it is over. A 25K (or 24.9K), 1% resistor is connected between this pin and VPP 37 EPAD Connected on PCB plane to VPN_IN 28 29 32 33 Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 7 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Functional Block Diagram +48V 10.5V regulator VPP 45mA RREF Vdd Bleeder control 4.8V regulator 1.2V Bandgap RREF WA_EN VPP UVLO RDET RDET AT_FLAG p m Te HD_FLAG 4P_AT_FLAG Enhanced Classification Block SUPP_S2 RCLS 80ms delay timer Detection control SUPP_S1 RCLASS VAUX_VCC Iclass Class control 4P_HD_FLAG Startup/ Inrush control VPN_OUT VPN_IN p m Te 48VRTN Rsense Figure 3: Block Diagram (PD70211 front-end section) Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 8 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications PD70211 (PWM section) Vin VDD VINS 13 Enable ENABLE 12 VREF HYST 14 VAUX_VCC 32 + - COMP 21 Csoftstart 5V LDO 5V drop VH 31 VL 25 UVLO/PFW select Soft-start / Logic 17 Decoupling for VH rail "High" Internal Rail "Low" Internal Rail (VDD) POK SS Chip Supply Decoupling for VL (VDD) rail VREF (1.2V) VIN SYNC DAO VIN VCC DAO 22 -+ offset + - - + FB 23 offset + - PG Vout_high 30 Differential amp output Vout_low PWM logic Dead time VCC SG CLK 26 CSP x5 Blanking and Limiting Differential Current sense amplifier RFREQ 16 Pulse skip Mode CSN 28 VSP 20 18 Rupper + - Rupper VSN 19 Clock RCLP Rfreq Differential Voltage sense amplifier Rsense + - x7 SYNC 15 29 GND 24 PGND 27 Rlower Rskip Rlower Figure 4: Block Diagram (PD70211 PWM section) Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 9 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Absolute Maximum Ratings Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating reliability. Voltages are with respect to IC ground (VPN_IN). VPP, VPN_OUT, RDET AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG SUPP_S1, SUPP_S2 RREF, RCLS, WA_EN VAUX_VCC PG, SG VL VH (with respect to VAUX_VCC) ENABLE All other pins Junction Temperature Lead Soldering Temperature (40s, reflow) Storage Temperature, MSL3 ESD rating HBM MM CDM Min -0.3 Max 74 Units V -0.3 20 V 0 -0.3 -0.3 -0.3 -0.3 0.3 VVPP + 1.5 5 20 20 6 -6 V V V V V V -0.3 -40 VL+0.3 150 260 150 1.5* 50 500 V C C C kV V V -65 *Pins VPP, VAUX/VCC , RREF pass 1kV HBM only. Operating Ratings (Front-End Section) Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. voltages are with respect to IC ground (VPN_IN). Min 0 -40 1.1 4.9 13.7 VPP Ambient Temperature* Detection Range Mark event range Class event range Max 57 85 10.1 10.1 20.9 Units V C V V V * Corresponding Max Operating Junction Temperature is 125C. Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 10 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Operating Ratings (PWM Section) Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. Voltages are with respect to IC ground. Min 7.8 100 VCC Fsw (adjustable frequency range) Max Duty Cycle fsw_synch (synchronization frequency range) 200 Max 20 500 44.5 1000 Units V kHz % kHz Max Units C/W C/W C/W Thermal Properties Thermal Resistance JA JP JC Min Typ 22.3 3 4 Note: The Jx numbers assume no forced airflow. Junction Temperature is calculated using T J = TA + (PD x JA). In particular, JA is a function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51 (JEDEC). Electrical Characteristics (Front-End Section) Unless otherwise specified under conditions, the Min and Max ratings stated below apply over the entire specified operating ratings of the device. Typ values stated, are either by design or by production testing at 25C ambient. Voltages are with respect to IC ground (VPN_IN). Symbol Parameter Input Voltage IC input current with IIN ICLASS off Detection phase VDET Detection range RDET disconnect RDET_TH threshold On-resistance of internal RDS_DET_ON FET during detection Copyright (c) 2016 Rev. 1.4, July 2017 Conditions Min Typ Max Units 1 3 mA 1.1 10.1 V 10.1 12.8 V 50 VPP=55V Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 11 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol RDS_DET_OFF IOFFSET_DET Parameter Off-resistance of internal FET after detection Conditions Max 5 A 4.85 V 11.4 13.7 V 20.9 23.9 V 2.8 3.0 1 V 10.1 11.4 V 0.25 4 mA 80 mA 50 RCLASS = not present (Class 0) RCLASS = 133 (Class 1) RCLASS = 69.8 (Class 2) RCLASS = 45.3 (Class 3) RCLASS = 30.9 (Class 4) Units M 1.1V VPP 10.1V, TJ 85C Input offset current Classification current sink Typ 2 RDET reconnection VR_DET_ON threshold when VPP goes low Classification phase Classification sink turnVCLS_ON on threshold Classification sink turnVCLS_OFF off threshold Hysteresis of VCLS_ON VHYS_CLS_ON threshold Mark detection VMARK_TH threshold (VPP falling) Current sink in Mark IMARK event region Current limit of class ICLASS_CLIM current ICLASS Min 68 3 9.5 17.5 26.5 38.0 10.5 18.5 28.0 40.0 11.5 19.5 29.5 42.0 mA Isolation FET RDSON On resistance ICLIM_INRUSH OCP Inrush current limit Overcurrent protection Copyright (c) 2016 Rev. 1.4, July 2017 Total resistance between VPN_IN to VPN_OUT; ILOAD < 600mA, -40oC <TA < 85oC 105 2.2 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA 240 0.3 325 mA A Page 12 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol ILOAD Parameter Continuous operation load Undervoltage Lockout Threshold that marks UVLOON start of Inrush phase Threshold where passUVLOOFF FET turns off as VPP collapses DC-DC Input Cap Discharger ICAP_DIS Discharge current Conditions tdis Discharge time timerdis Discharge timer CDC_DC 264 F (by design, not tested) Time for which discharge circuit is activated 7V VPP 30V References, Rails and Logic VAUX Auxiliary voltage Max continuous current IAUX from VAUX IAUX_CLIM Aux current limit Bandgap reference VREF voltage tFLAG_LO IFLAG tFLAG VSUPP_HI Copyright (c) 2016 Rev. 1.4, July 2017 Low level flag Flag Current driving capability Delay timer between start of inrush and flags declared SUPP_Sx high voltage threshold 0mA < IAUX < 4mA Min Typ Max Units 2 A 36 42 V 30.5 34.5 V 22.8 60 mA 500 ms 430 9.8 ms 10.5 12.0 4 mA 10 1.17 For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG, IFLAG= 3mA For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG V 1.2 32 mA 1.23 V 0.4 V 5 mA For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG 80 ms For SUPP_S1 and SUPP_S2 25 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA 35 V Page 13 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Wall Adapter VIH Input high logic VIL Input low logic Min 2.4 Typ Max 0.8 Units V V Truth Table for Status of Flags Number of Fingers "N" (N-Event classification) 1 SUPP_S1 SUPP_S2 AT_FLAG HD_FLAG 4P_AT_FLAG 4P_HD_FLAG X X Hi Z Hi Z Hi Z Hi Z 2 H L 0V Hi Z Hi Z Hi Z 2 L H 0V Hi Z Hi Z Hi Z 2 H H 0V Hi Z 0V Hi Z 3 L H 0V 0V Hi Z Hi Z 3 H L 0V 0V Hi Z 3 H H 0V 0V 0V Hi Z 4 X X 0V 0V 0V Hi Z 0V 0V 5 6 RESERVED FOR FUTURE X X 0V 0V Electrical Characteristics (PWM Section) Unless otherwise specified under conditions, the Min and Max ratings stated below apply over the entire specified operating ratings of the device. Typ values stated, are either by design or by production testing at 25C ambient. Voltages are with respect to IC ground (VPN_IN). Symbol Parameter Input Voltage Current UVLO threshold with VCC_UVLO_UP input rising UVLO threshold with VCC_UVLO_DN input falling IC input current (no IVCC_SD switching) Copyright (c) 2016 Rev. 1.4, July 2017 Conditions Min Typ Max Units VCC rise time > 0.5 ms 8.85 9.15 9.5 V VCC rise time > 0.5 ms 7 7.3 7.6 V 1 2000 A VENABLE = Low, or VVCC < VCC_UVLO_UP Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 14 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter IC input current IVCC_Q (switching, no load on SG, PG, VDD) Input UVLO/PFW VINS_TH Threshold on VINS pin Hysteresis pin high VHYST_HIGH voltage Hysteresis pin low VHYST_LOW voltage LDOs Rising or falling IHYST_SOURCING = 1mA Min 1.171 Typ 1.200 Max Units 3 mA 1.229 V 2.8 V IHYST_SINKING = 3mA IVDD_EXT < 5mA (current out of pin) VL VH Conditions VENABLE = High, and VVCC > VCC_UVLO_UP, fsw = 500kHz 4.75 VH rail (with respect to VCC) 5 0.4 V 5.25 V -5V V Soft Start ISS_CH ISS_DISCH VSS_CH VSS_DISCH RSS_DISCH Copyright (c) 2016 Rev. 1.4, July 2017 Current out of SS pin during charging phase Current into SS pin during discharging phase Soft start charge completed threshold Soft start discharge completed threshold Soft-start pin discharge FET resistance RFREQ=33.3k, VSS=0.5V 32 RFREQ=33.3k, VSS=0.5V By design only Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA 36 40 % of ISS_CH 10 90 A 95 % of VREF 50 mV 50 Page 15 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter Conditions Soft-start discharge FET tDISCH on-time Switching Frequency and Synchronization Switching frequency fsw_range RFREQ=33.2k accuracy Max synchronization fsync_max frequency SYNC pin high VSYNC_HI threshold VSYNC_LO SYNC pin low threshold Minimum pulse width tsync of SYNC pulse Max SYNC pulse duty Dsync_max cycle Error Amplifier VREF Reference voltage GainDC_OPL DC Open-loop gain Rload=100k Cload=10pF (By design AVUGBW Unity Gain Bandwidth only) Output sourcing ICOMP_OUT 0.2V< VCOMP < 1.3V current ICOMP_IN Output sinking current 0.2V< VCOMP < 1.3V Max of input commonVEA_CMR_MAX mode range VCLAMP COMP pin high clamp Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Min Typ Max Units Switch cycles 345 kHz 32 285 315 1 MHz 2.4 V 0.8 100 V ns 1.171 70 1.200 100 2 5 90 % 1.229 V dB MHz 110 620 A 145 495 A 2 1.8 V 2.1 2.6 V Page 16 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter PWM Comparator Inserted offset in VOFFSET inverted input Voltage set on RCLP pin VRCLP by external resistor to GND Current Sense Amplifier GainCSA DC Gain Max continuous IAUX current from VAUX Max input commonVCSA_CMR_MAX mode range tBLANK Blanking time Current limit threshold VILIM on output of current sense amplifier Current Limit threshold on output of current VILIMHICCUP sense amplifier capability Differential Voltage Amplifier DC gain of differential GainDA voltage amp Unity Gain Bandwidth AVUGBW_DA of differential voltage amp Max of input commonVDA_CMR_MAX mode range Drivers Drive resistance when RPG_HI PG is high Drive resistance when RPG_LO PG is low Minimum on-time of tPG_MIN PG DMAX PG max duty cycle Copyright (c) 2016 Rev. 1.4, July 2017 Conditions Min Max Units 200 300 mV 0 1 V 5.25 V 4.75 Typ 5 4 mA 2 V 50 100 ns Where PWM pulses start to get truncated 1.1 1.2 1.3 V Where PWM pulses start to get omotted in hiccup mode 1.7 1.8 1.9 V 6.68 7.0 7.14 5 MHz 3.5 44.5 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA V 10 5 120 ns 50 % Page 17 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol RSG_HI RSG_LO tDEAD Parameter Drive resistance when SG is high Drive resistance when SG is low Deadtime Conditions PG low to SG high or PG high to SG low Logic Levels on VINS and ENABLE VHI Input high threshold VLO Input low threshold Thermal Protection Thermal shutdown TSD (rising) Thermal shutdown THYST hysteresis Min 60 Typ Max Units 10 10 110 190 ns 0.8 V V 2 157 15 C 30 C Thermal Protection PD70211 is protected from excessive internal temperatures that may occur during various operating procedures. Two temperature sensors are located on the chip, monitoring the temperatures of the following: Isolating Switch (pass-FET) Classification Current Sink Each of the over temperature sensor activates a protection mechanism that will disconnect the Isolation (pass) FET or the classification circuit respectively. This protects the device from being permanently damaged or even from long-term degradation. Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 18 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Truth Table for Status of Flags Number of Fingers "N" (N-Event Classification) 1 SUPP_S1 SUPP_S2 AT_FLAG HD_FLAG 4P_AT_FLAG 4P_HD_FLAG X X Hi Z Hi Z Hi Z Hi Z 2 H L 0V Hi Z Hi Z Hi Z 2 L H 0V Hi Z Hi Z Hi Z 2 H H 0V Hi Z 0V Hi Z 3 L H 0V 0V Hi Z Hi Z 3 H L 0V 0V Hi Z 3 H H 0V 0V 0V Hi Z 4 X X 0V 0V 0V Hi Z 0V 0V 5 6 RESERVED FOR FUTURE X X 0V 0V Wall Adapter mode PD70211 support wall adapter functionality, i.e. by setting WA_EN pin high it will give priority to the wall adapter jack to supply the load. WA_EN pin is used while connecting a wall-adapter voltage between VPP and VPN_OUT by means of an ORing diode. While WA_EN, Wall-adapter enable pin, is held low (referenced to VPN_IN), the front-end works as a normal PD. When WA_EN is raised high (referenced to VPN_IN) three internal operations are forced: The Isolation FET is turned OFF. All output flags AT_FLAG, HD_FLAG, 4P_AT_FLAG and 4P_HD_FLAG are activated (low state). Vaux output voltage is turned ON. While activating WA_EN pin, the wall-adapter will supply input voltage for the DC-DC converter. Having WA_EN at high state does not disable detection and classification modes. Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 19 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Applications Information Peripheral devices An 100nF/100V capacitor should be placed between device VPP and VPNI pins, and located as close as possible to the device. An 58V TVS should be placed between device VPP and VPNI pins. An 10K ohm resistor should be placed on SUPP_S1 and SUPP_S2 lines between diode bridge and PD70211 device. When WA_EN is used, an 100nF/10V Capacitor should be placed between WA_EN and VPNI pin close to PD70211 device. When not used, WA_EN should be connected to VPNI pin. Setting Switching Frequency A resistor, RFREQ, is connected from RFREQ pin to IC ground. Based on that, we get the following frequency = 1 (90 x ) + 150 where Freq is [Hz] and Rfreq in For example, by setting RFREQ=49900, we get = 1 = ~215000 (90 x 49900) + 150 We can set any frequency between 100 to 500 kHz. Note that when synchronizing, the default frequency (as set by RFREQ) must be lower than the synchronization clock. In case the synchronization breaks, the converter will lapse back to the default value. When synchronizing, we can increase the frequency to 1MHz. Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 20 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Setting Soft-Start A capacitor is connected between SS pin and IC ground. The current charging the capacitor is ISS_CHG 1.2V (in seconds) RFREQ For example, if RFREQ=49.9k, we get ISS_CHG 1.2V 49.9 103 (in Amperes) = 2.4 105 24A So, charging a 0.1F ceramic cap on the soft-start pin from 0 to 1.2V will take t SS C V ISS_CHG (in seconds) = 0.1 1.2 0.12 (in seconds) = (in seconds) = 5 103(in seconds) 5ms 24 24 This is the soft-start time in this case. Setting Pulse-skip Mode threshold If a programming resistor RCLP is placed between RCLP pin and IC ground, the clamping voltage level is given by VCLP 0.3 RCLP (in Volts) RFREQ For example, if RCLP = RFREQ, say both are 49.9k, then the converter will enter pulse skipping when the output of the current sense amplifier drops to 0.3V. Note that the gain with this current amplifier is 5, so in terms of the voltage on the sense resistor (input of the current amp), we get 0.3V/5 = 0.06V. Since we usually design the converter so that its peak is around 0.2V (the peak of Rsense voltage before it starts to current limit), we are getting a ratio of 0.06V/0.2V = 0.3. In other words, the converter will enter pulse-skipping when the output current is 30% of the max designed output current. Setting UVLO/Hysteresis thresholds Note: A 470k resistor from PG pin to VINS pin is required for guaranteeing proper termination of Gate drive pulse during UVLO. Suppose we have a divider connected to input at the VINS pin. Suppose we call the resistors R UPPER and RLOWER. We also have a hysteresis resistor, RHYST, from the output of the UVLO comparator, which provides positive feedback on to the VINS pin, as explained in the Pin Description section. So, when the input voltage is rising, in Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 21 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications effect the hysteresis resistor is in parallel to the lower resistor R LOWER. When the voltage on the VINS pin rises above 1.2V, the UVLO comparator flips and the hysteresis resistor appears connected to 5V (output of the UVLO comparator). The equivalent configurations are shown in Figure 5. After solving the equations, the following example indicates the set thresholds. The values are as used in Figure 3. R UPPER 270k; R LOWER 8.66k; R HYST 270k Part 1: (VINS less than 1.2V) Equivalent lower resistor is a parallel combination of R LOWER and R HYST R LOWER _ EQUIV R LOWER R HYST 8.66k 270k 8.391k R LOWER R HYST 8.66k 270k The rising voltage threshold is VUVLO_ UP VREF R UPPER R LOWER _ EQUIV R LOWER _ EQUIV 1.2V 270k 8.391k 39.8V 8.391k Part 2: (VINS greater than 1.2V) R R VUVLO_ DN VREF UPPER VDD VREF UPPER VREF R LOWER R HYST 1.2V 270k 270k 3.8V 1.2 34.8V 8.66k 270k So with the selected resistors, we get a rising threshold of 39.8V, and a falling threshold of 34.8V. Rising Input VIN RUPPER VVINS < 1.2V RHYST RLOWER Falling Input VIN 5V RUPPER VVINS > 1.2V RLOWER RHYST Figure 5: Equivalent Diagrams for UVLO and Hysteresis Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 22 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Setting the Voltage Divider for Output Rails Generically, we can state the equation to be VOUT VX R UP R LOW R LOW Where RUP is the name we have given to the upper resistor (connected to output rail) and RLOW is the name we have given here to the resistor connected to lower rail (usually IC ground). However, there are so many topologies, we have in effect thress cases in all the typical schematics presented so far. a) Non-isolated topologies with simple divider connected directly to FB pin. For this use VX = 1.2V. b) Isolated topologies with divider to another reference (such as TL431 with an internal reference of 2.5V). For this use VX = 2.5V. c) Non-isolated topologies with a differential divider connected to differential voltage amplifier of the LX7309 . Here we use the same divider equation provided above, but using VX = 0.171V (that is 1.2V divided down by the gain of the diff-amp, i.e. by 7). We need two identical dividers. Selecting the Sense Resistor In a Buck topology, the center of the switch current ramp equals the output current. To that we need to add about 30% for the peak current "IPEAK+" because of the rising ramp caused by the inductor. That is a factor of 1.3. We also need to include some headroom for proper transient response at max load. Since the peak voltage on the sense resistor is 0.2V, to leave headroom, we should plan that the switch current peak stays at around 0.18V max at max load. This means that: IPEAK 1.3 IO , So RSENSE RSENSE = 0.18 0.138 = 1.3 IO IO 0.138 (Buck) IO Assuming we have designed the converter to operate up to 44% max duty cycle, we can quickly estimate the peak current as follows. Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 23 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications For example, if we have a Buck application for 5A output, irrespective of the input and output voltage conditions (as long as they are not violating the min and max duty cycle limits of the converter), and assuming we have selected inductance appropriately, we should pick a sense resistor of RSENSE 0.138 =0.028 5A We may need to put an adjust resistor in parallel (such as the "22" placeholder) we have shown in all the typical application schematics. For a Forward converter (Buck with a transformer), instead of the load current I OR in the above equation, use the reflected load current of IO/n, where n is the turns ratio (number of Primary-side turns divided by number of Secondary-side turns). You will also need to lower the sense resistance further (by means of the adjust resistor), to account for the magnetization current component on the switch side. So roughly: RSENSE 0.138 NP (Forward) IO NS For a Boost or Buck-Boost, we have to account for the fact that the peak current is not just 1.3 times max load current, but is actually IPEAK 1.3 IO (where D can be as high as 44%) 1D So we should use the following equation for sense resistor RSENSE RSENSE 0.18 1 D 1.3 IO = 0.101 1 = 1.3 IO 13 IO 0.077 (Boost, Buck-Boost) IO For example, if the max load current is 5A, the sense resistor value to use is RSENSE 0.077 =0.015 5A As we can see, this is roughly half of what we got for the Buck (same load current). For a Flyback topology (Buck-Boost with a transformer), we have to use the reflected output current. So we get: RSENSE 0.077 NP (Flyback) IO NS Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 24 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Operation with an External DC Source PD applications utilizing PD70211 IC may be operated with an external power source (DC wall adaptor). There are two cases of providing power with an external source, the cases are presented in. Figure 6 and Figure 7. External source connected to application's low voltage supply rails. External source voltage level is dependent on DCDC output characteristics. Described in Figure 6 External source connected to PD device output connection toward the application (VPP to VPN OUT). External source voltage level is dependent on DCDC input requirements. Described in Figure 7 D1 (+) Input Data+ from line XFMR IN1A (-) Input Isolated DCDC Application + OUTP SUPP_S1 Data- from line XFMR Bootstrap Winding Isolated Output Supp_S1 Supp_S2 Rref 10K IN2B controller VCC PGND PD70211 Rcls - OUTN VAUX_VCC SUPP_S1 SUPP_S2 WA_EN 100nF 100V TVS Vpp IN1B SUPP_S2 Spare- from line XFMR Rdet Spare+ from line XFMR Primary DC(+) 10K IN2A Isolated Output Primary DC (-) VPNI VPNo VPNo VPNI Figure 6: External Power Input connected to Application supply Rails D1 (+) Input R1 Q1 R2 Data+ from line XFMR IN1A (-) Input Isolated DCDC Application + OUTP SUPP_S1 Data- from line XFMR Bootstrap Winding Isolated Output IN2A 100nF 10K 100nF 100V SUPP_S1 Supp_S1 SUPP_S2 Supp_S2 Rref VAUX_VCC TVS WA_EN R3 Vpp IN1B SUPP_S2 Spare- from line XFMR Rdet Spare+ from line XFMR Primary DC(+) 10K PGND PD70211 Rcls R4 IN2B - OUTN VPNo VPNo Copyright (c) 2016 Rev. 1.4, July 2017 Isolated Output Primary DC (-) VPNI VPNI controller VCC Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 25 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Figure 7: External Power Input connected to PD70211 Output External source connected to PD device output (Figure 7) PD70211 WA_EN pin is used for disabling the isolation switch and thus PSE input power, when an external adapter is connected. WA_EN resistors divider depends on the VinH threshold of the PD70211. Figure 8 is zooming into the resistors to be selected in external adapter connection. (+) Input R1 Q1 (-) Input R2 VPNo R3 PD IC EN R4 100nF VPNin Figure 8: External Power Input resistors dividers R1 and R2 sets a rough threshold for Pfet Q1 enable, to detect whether external adapter exists or not. It should be set to be lower threshold than PD70211 disable levels. R3 and R4 sets PD70211 disable threshold. So in case of 36V-57V external adapter. The disable setting can be selected as follows: Pfet enable threshold = 30V. R1 and R2 setting should be so that the value of Q1 VGS < 20V at max voltage condition of external adapter. While external adapter voltage is above 30V, Q1 will be above its VGSth value. = _ x R1 is selected as 2k. 2 = 1 x 1 1 + 2 _ - Using R1=2k, Vext_adapter=30V and VGS= maximum VGSth =3.5V. we get R2 value. 2 = 15 Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 26 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications R3 and R4 are set to the range of few k- 10's of k using the equation below: (I) = 70211__ = __70211 x 4 (3+4) Using R3=15k, Vext_adapter=33.7V and from data sheet we use PD70211_WA_EN=2.4V as turn Off min threshold. Solving the equation , we get the valid resistors values for an adapter of 36V and above. 3 = 15 4 = 1.15 Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 27 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Package Dimensions LQ 36-Pin QFN 6x6mm Dim A A1 A3 e L b D2 E2 D E D b e K 28 1 D2 E2 E L 19 10 A MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.50 BSC 0.45 0.65 0.18 0.30 4.00 4.25 4.00 4.25 6.00 BSC 6.00 BSC INCHES MIN MAX 0.031 0.039 0 0.002 0.008 REF 0.019 BSC 0.018 0.026 0.007 0.011 0.157 0.167 0.157 0.167 0.236 BSC 0.236 BSC Note: A1 1. A3 2. Copyright (c) 2016 Rev. 1.4, July 2017 Dimensions do not include protrusions; these shall not exceed 0.155mm (.006") on any side. Lead dimension shall not include solder coverage. Dimensions are in millimeters, inches for reference only. Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 28 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications PD70211 Recommended PCB layout Recommended PCB layout pattern for PD70211 is described in the following figures. 4.3 4.2 0.5 0.3 1.0 4.2 4.3 Figure 9: PD70211 Top layer Copper Recommended PCB Layout (mm) 4.3 3.9 0.5 0.3 1.0 3.9 4.3 1.8 mask Solder past Solder 1.8 Figure 10: PD70211 Top layer Solder Mask, Solder Paste and Vias Recommended PCB Layout (mm) Solder past Solder mask Solder PAD 0.3 0.6 0.6 1.0 3.9 4.2 1.0 3.9 4.2 Figure 11: PD70211 Bottom layer Copper and Solder Paste Recommended PCB Layout for Thermal Pad Array (mm) Copyright (c) 2016 Rev. 1.4, July 2017 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 29 PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications The information contained in the document (unless it is publicly available on the Web without access restrictions) is PROPRIETARY AND CONFIDENTIAL information of Microsemi and cannot be copied, published, uploaded, posted, transmitted, distributed or disclosed or used without the express duly signed written consent of Microsemi. If the recipient of this document has entered into a disclosure agreement with Microsemi, then the terms of such Agreement will also apply. This document and the information contained herein may not be modified, by any person other than authorized personnel of Microsemi. No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the information, either expressly, by implication, inducement, estoppels or otherwise. Any license under such intellectual property rights must be approved by Microsemi in writing signed by an officer of Microsemi. Microsemi reserves the right to change the configuration, functionality and performance of its products at anytime without any notice. This product has been subject to limited testing and should not be used in conjunction with life-support or other mission-critical equipment or applications. Microsemi assumes no liability whatsoever, and Microsemi disclaims any express or implied warranty, relating to sale and/or use of Microsemi products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Any performance specifications believed to be reliable but are not verified and customer or user must conduct and complete all performance and other testing of this product as well as any user or customers final application. User or customer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the customer's and user's responsibility to independently determine suitability of any Microsemi product and to test and verify the same. The information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the User. Microsemi specifically disclaims any liability of any kind including for consequential, incidental and punitive damages as well as lost profit. The product is subject to other terms and conditions which can be located on the web at http://www.microsemi.com/company/terms-and-conditions Revision History Revision Level / Date Para. Affected Description 0.1 / Feb 2, 2012 - Initial Release 0.2 / March 2012 - Class Values - Typo's Editing 0.3 -0.5/ March 2013 - General update 0.6/ July 2014 - Reduce flags maximum voltage, Add WA_EN information 1.0/ August 2014 - Add freq setting information 1.1/ Jan 2015 - Add PCB footprint recommendation 1.2 / June 2015 - Updating typo in part marking definition 1.3 / Oct 2015 Page 7 Page 13 Page 31 Page 2 All Pages Fix Vaux pin description. Add UVLO_ON missing information. Fidure 9, 10, 11 Typo (cnage PD70224 to PD70211) Clarified Ordering Information table Fix typo descibing the IC marking (remove the initial "PD") Remove the name of the front end die in functional block diagram (Remove PD70210A) Update Rev number and date in the footer. Page 2, 10 Updated marking and MSL3 per PCN 157021 1.31 / July 2016 Page 8 1.4 / July 2017 (c) 2016 Microsemi Corp. All rights reserved. For support contact: PoEsupport@microsemi.com Visit our web site at: www.microsemi.com Copyright (c) 2016 Rev. 1.4, July 2017 Catalog Number: DS_PD70211 Microsemi CPG - PoE BU One Enterprise Aliso Viejo, CA 92656 USA Page 30