MB90F568PMC - Fujitsu Limited

FUJITSU MICROELECTRONICS

DATA SHEET

2008.9

The information fo r microcontroller support s is shown in the following homepage.

Be sure to refer to the "Check Sheet" for the latest cautions on development.

"Check Sheet" is seen at the following support page

"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in

system development. http://edevice.fujitsu.com/micom/en-support/

16-bit Proprietary Microcontrollers

CMOS

F2MC-16LX MB90560/565 Series

MB90561A/562A/F562B/V560/567/568/F568

■DESCRIPTION

The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and process

control applications that require high-speed real-time processing. The device f eatures a multi-function timer able

to output a pr ogrammable waveform.

The microcontroller inst ruction set is based on the same AT architecture as the F 2MC-8L and F2MC-16L families

with additional instructions for high-lev el languages, extended addressing modes, enhanced signed multiplication

and division instructions, and a complete range of bit manipulation instructions. The microcontroller has a

32-bit accumulator for processing long word (32-bit) data.

Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.

■FEATURES

•Clock

• Internal oscillator circuit and PLL clock multiplication circuit

• Oscillation clock

Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the oscillation

clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation

clock multiplied by one to four (4 MHz to 16 MHz for a 4 MHz base oscillation) .

• Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V)

• Maximum CPU memor y space : 16 MB

• 24-bit addressing

• Bank addressing (Continued)

DS07-13715-5E

MB90560/565 Series

2DS07-13715-5E

(Continued)

• Instruction set

• Bit, byte, word, and long word data types

• 23 different addressing modes

• Enhanced calculation precision using a 32-bit accumulator

• Enhanced signed multiplication and division instructions and RETI instruction

• Instruction set designed for high level language (C) and multi-tasking

• Uses a system stack pointer

• Symmetric instruction set and barr el sh ift inst ructions

• Program patch function (2 address pointers) .

• 4-byte instruction queue

• Interrupt function

• Prio rity levels are programmable

• 32 interrupts

• Data transfer function

• Extended intelligent I/O service function : Up to 16 channels

• Low-power consumption modes

• Sleep mode (CPU operating clock stops.)

• Timebase timer mode (Only oscillation clock and timebase timer continue to operate.)

• Stop mode (Oscillation clock stops.)

• CPU intermittent operation mode (The CPU operates intermittently at the specified interval.)

• Package

• LQFP-64P (FTP-64P-M23 : 0.65 mm pin pitch)

• QFP-64P (FTP-64P-M06 : 1.00 mm pin pitch)

• SH-DIP (DIP-6 4P-M01 : 1.778 mm pin pitch)

• Process : CMOS technology

■PERIPHERAL FUNCTIONS (RESOURCES)

• I/O ports : 51 ports (max.)

• Timebase timer : 1 channel

• Watchdog timer : 1 channel

• 16-bit reload timer : 2 channels

• Multi-function timer

• 16-bit free-run timer : 1 chan ne l

• Output compare : 6 channels

Can output an inter rupt request when a match occur s between t he count in the 16-bit freerun timer and the

value set in the compare register.

• Input capture : 4 channels

On detecting an activ e edge on th e input signal from an e xternal input pin, copies the count v alue of the 16-

bit freerun timer to the input capture data register and generates an interrupt request.

• 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) The period and duty of the output pulse can

be set by the program.

• Waveform generator (8-bit timer : 3 channels)

•UART : 2 channels

• Full-duplex, double-buffered (8-bit)

• Can be set to asynchronous or clock synchronous serial transfer (I/O expansion serial) operation

• DTP/external interrupt circuit (8 channels)

• External interr upts can ac tivate the extended intelligent I/O service.

• Generates interrupts in response to external interrupt inputs.

MB90560/565 Series

DS07-13715-5E 3

• Delayed interrupt generation module

• Generates an interrupt request for task switching.

• 8/10-bit A/D converter : 8 channels

• 8-bit or 10-bit resolution selectable

MB90560/565 Series

4DS07-13715-5E

■PRODUCT LINEUP

1. MB90560 Series

* : DIP switch setting (S2) when using the emulation pod (MB2145-507) .

Refer to “2.7 Dedicated Emulator P ower Supply” in the “MB2145-507 Hardware Manual” for details.

Part Number MB90F562B MB90562A MB90561A MB90V560

Classification Internal flash memory

product Internal mask ROM product Evaluation product

ROM size 64 Kbytes 32 Kbytes No ROM

RAM size 2 Kbytes 1 Kbytes 4 Kbytes

Dedicated emula-

tor power supp ly*⎯⎯No

CPU functions

Number of instructions : 351

Minimum instruction execution time : 62.5 ns for a 4 MHz oscillation (with ×4 multiplier)

Addressing modes : 23 modes

Program patch function : 2 address pointers

Maximum memory space : 16 Mbytes

Ports I/O ports (CMOS) : 51

UART

Full-duplex, double-buffered

Clock synchronous or asynchronous operation selectable

Can be used as I/O serial

Internal dedicated baud rate generator

2 channels

16-bit reload timer 16-bit reload timer operation

2 channels

Multi-function

timer

16-bit free-run timer × 1 channel

Output compare × 6 channe ls

Input capture × 4 channels

8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels)

Waveform generator (8-bit timer × 3 channels) 3-phase waveform output, deadtime output

8/10-bit

A/D converter

8 channels (multiplexed inpu t)

8-bit or 10-bit resolution selectable

Conversion time : 6.13 µs (min.) (for maximum machine clock speed 16 MHz)

DTP/external

interrupts

8 channels (8 channels available, shared with A/D input)

Interrupt triggers :

“L” → “H” edg e, “H” → “L ” ed ge , “L ” leve l, “H” leve l (sele ct ab le)

Low power

consumption

modes Sleep mode, timebase timer mode, stop mode, and CPU int ermittent operation mode

Process CMOS

Operating vo ltage 5 V ± 10%

MB90560/565 Series

DS07-13715-5E 5

2. MB90565 Series

* : DIP switch setting (S2) when using the emulation pod (MB2145-507) .

Refer to “2.7 Dedicated Emulator P ower Supply” in the “MB2145-507 Hardware Manual” for details.

Part Number MB90F568 MB90568 MB90567

Classification Internal fl ash memory product Internal mask ROM product

ROM size 128 Kbytes 96 Kbytes

RAM size 4 Kbytes 4 Kbytes

Dedicated emula-

tor power supp ly*⎯⎯

CPU functions

Number of instructions : 351

Minimum instruction execution time : 62.5 ns for a 4 MHz oscillation (with ×4 multiplier)

Addressing modes : 23 modes

Program patch function : 2 address pointers

Maximum memory space : 16 Mbytes

Ports I/O ports (CMOS) : 51

UART

Full-duplex, double-buffered

Clock synchronous or asynchronous operation selectable

Can be used as I/O serial

Internal dedicated baud rate generator

2 channels

16-bit reload timer 16-bit reload timer operation

2 channels

Multi-function

timer

16-bit free-r un ti me r × 1 channel

Output compare × 6 chan nels

Input captur e × 4 channels

8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channe ls)

Waveform generat or (8-bit timer × 3 channels) 3-phase waveform output, deadtime output

8/10-bit A/D

converter

8 channels (multiplexed input)

8-bit or 10-bit resolution selectable

Conversion time : 6.13 µs (min.) (for maximum machine clock speed 16 MHz)

DTP/external

interrupts

8 channels (8 channels available, shared with A/D input)

Interrupt triggers :

“L” → “H” edge, “H” → “L” edge, “L” level, “H” level (selectable)

Low power con-

sumption modes Sleep mode, timebase timer mode, stop mode, and CPU intermittent operation mode

Process CMOS

Operating voltage 3.3 V ± 0.3 V

MB90560/565 Series

6DS07-13715-5E

■PACKAGE AND CORRESPONDING PRODUCTS

: Available : Not available

Note : See the “Package Dimensions” section for details of each package.

Package MB90561A MB90562A MB90F562B MB90567 MB90568 MB90F568 MB90V560

FPT-64P-M23

(LQFP-0.65 mm)

FPT-64P-M06

(QFP-1.00 mm)

DIP-64P-M01

(SH-DIP)

PGA-256C-A01

(PGA)

×× × ×

×× ××××

MB90560/565 Series

DS07-13715-5E 7

■PIN ASSIGNMENTS

(Continued)

(TOP VIEW)

(FPT-64P-M06)

* : N.C. on the MB90F568, MB90567, and MB90568.

P44/PPG3

P45/PPG4

P46/PPG5

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AVCC

AVR

AVSS

P60/SIN1

P61/SOT1

P62/SCK1

P63/INT7/DTTI

MD0

P30/RTO0

VSS

P27/IN3

P26/IN2

P25/IN1

P24/IN0

P23/TO1

P22/TIN1

P21/TO0

P20/TIN0

P17/FRCK

P16/INT6

P15/INT5

P14/INT4

P13/INT3

P12/INT2

P11/INT1

P10/INT0

P07

P43/PPG2

P42/PPG1

P41/PPG0

P40/SCK0

P37/SOT0

P36/SIN0

VCC

P35/RTO5

P34/RTO4

P33/RTO3

P32/RTO2

P31/RTO1

RST

MD1

MD2

VSS

P00

P01

P02

P03

P04

P05

P06

MB90560/565 Series

8DS07-13715-5E

(Continued)

(TOP VIEW)

(FPT-64P-M23)

* : N.C. on the MB90F568, MB90567, and MB90568.

P45/PPG4

P46/PPG5

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AVCC

AVR

AVSS

P60/SIN1

P61/SOT1

P62/SCK1

P27/IN3

P26/IN2

P25/IN1

P24/IN0

P23/TO1

P22/TIN1

P21/TO0

P20/TIN0

P17/FRCK

P16/INT6

P15/INT5

P14/INT4

P13/INT3

P12/INT2

P11/INT1

P10/INT0

P44/PPG3

P43/PPG2

P42/PPG1

P41/PPG0

P40/SCK0

P37/SOT0

P36/SIN0

VCC

P35/RTO5

P34/RTO4

P33/RTO3

P32/RTO2

P31/RTO1

P30/RTO0

VSS

P63/INT7/DTTI

MD0

RST

MD1

MD2

VSS

P00

P01

P02

P03

P04

P05

P06

P07

MB90560/565 Series

DS07-13715-5E 9

(Continued)

(TOP VIEW)

(DIP-64P-M01)

(Only support MB90F562B, MB90561A, and MB90562A.)

* : Not support on the MB90F568, MB90567, and MB90568.

P36/SIN0

P37/SOT0

P40/SCK0

P41/PPG0

P42/PPG1

P43/PPG2

P44/PPG3

P45/PPG4

P46/PPG5

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AVCC

AVR

AVSS

P60/SIN1

P61/SOT1

P62/SCK1

P63/INT7/DTTI

MD0

RST

MD1

MD2

VSS

VCC

P35/RTO5

P34/RTO4

P33/RTO3

P32/RTO2

P31/RTO1

P30/RTO0

VSS

P27/IN3

P26/IN2

P25/IN1

P24/IN0

P23/TO1

P22/TIN1

P21/TO0

P20/TIN0

P17/FRCK

P16/INT6

P15/INT5

P14/INT4

P13/INT3

P12/INT2

P11/INT1

P10/INT0

P07

P06

P05

P04

P03

P02

P01

P00

MB90560/565 Series

10 DS07-13715-5E

■PIN DESCRIOTIONS

(Continued)

Pin No. Pin

Name Circuit

Type*1

State/

Function

at Reset Description

QFP*3 LQFP*4 SDIP*5

23, 24 22, 23 30, 31 X0, X1 A Oscillator Connect oscillator to these pins.

If using an ex ternal clock, leave X1 open.

20 19 27 RST HReset

input External reset input pin

26 to 33 25 to 32 33 to 40 P00 to

P07 C

Port

inputs

(Hi-Z

outputs)

I/O ports

34 to 40 33 to 39 41 to 47

P10 to

P16

I/O ports

INT0 to

INT6

Can be used as interrupt request inputs ch0 to ch6.

In standby mode, these pins can operate as inputs

by setting the bits corresponding to EN0 to EN6 to

“1” and setting as input ports. When used as a port,

set the correspond ing bits in the analog input

enable register ( ADER) to “port”.

41 40 48

P17

I/O port

FRCK

External clock input pin for the freerun timer.

This pin can be used as an input when set as the

clock input for t he freerun timer an d set as an input

port. When used as a port, set the corresponding

bit in the analog input enable register (ADER) to

“port”.

42 41 49

P20

I/O port

TIN0 External clock input pin for reload timer ch0. This

pin can be used as an input when set as the exter-

nal clock input and set as an input port.

43 42 50 P21 DI/O port

TO0 Event output pin f or reload t imer ch 0. Out put oper -

ates when event output is enabled.

44 43 51

P22

I/O port

TIN1 External clock input pin for reload timer ch1. This

pin can be used as an input when set as the exter-

nal clock input and set as an input port.

45 44 52 P23 DI/O port

TO1 Event output pin f or reload t imer ch 1. Out put oper -

ates when event output is enabled.

46 to 49 45 to 48 53 to 56

P24 to

P27 D

I/O ports

IN0 to

IN3

Trigger input pins for input capture ch0 to ch3.

These pins can be used as an input when set as an

input capture tr igger input and set as an input port.

MB90560/565 Series

DS07-13715-5E 11

(Continued)

Pin No. Pin

Name Circuit

Type*1

State/

Function

at Reset Description

QFP*3 LQFP*4 SDIP*5

51 to 56 50 to 55 58 to 63

P30 to

P35

Port

inputs

(Hi-Z)

I/O ports

RTO0

RTO5

Event output pins for the output compare and

waveform generator output pi ns. The pins output

the specified waveform generated by the waveform

generator. If not using waveform genera tion, these

terminals enab le out pu t c om p ar e ev en t ou tp ut to

use as output compare outputs. When used as a

port, set the corr espondin g bits in th e analog inp ut

enable register (ADER) to “port”.

59 58 2

P36

I/O port

SIN0

Serial data input pin for UART ch0.

This pin is used conti nuously when inpu t operation

is enabled for UART ch0. In this case, do not use

as a general input pin.

60 59 3

P37

I/O port

SOT0 Serial data output pin for UART ch0.

Output operates when UART ch0 output is en-

abled.

61 60 4

P40

I/O port

SCK0 Serial clock I/O pin for UART ch0 .

Output operates when UART ch0 clock output is

enabled.

62 to 64,

1 to 3 61 to 64,

1, 2 5 to 10

P41 to

P46 D

I/O ports

PPG0

PPG5

Output pins for PPG ch 0 to ch 5.

The outputs operate when output is enabled for

PPG ch0 to ch5.

4 to 11 3 to 10 11 to 18

P50 to

P57 FAnalog

inputs

I/O ports

AN0 to

AN7

Analog input pins for the A/D converter. Input is

available when the corresponding analog input en-

able register bits are set. (ADER : bit0 to bit7)

12 11 19 AVCC ⎯Power

supply

input VCC power supply input pin for A/D converter.

13 12 20 AVR G Refer-

ence volt-

age input

Reference vo ltage input pin for A/D converter.

Ensure that the voltage does not exceed VCC.

14 13 21 AVSS ⎯Power

supply

input VSS power supply input pin for A/D converter.

MB90560/565 Series

12 DS07-13715-5E

(Continued)

*1 : See “■ I/O CIRCUITS” for details of the circuit types.

*2 : N.C. on the MB90F568, MB90567 , and MB90568

*3 : FPT-64P-M06

*4 : FPT-64P-M23

*5 : DIP-64P-M01

Pin No. Pin

Name Circuit

Type*1

State/

Function

at Reset Description

QFP*3 LQFP*4 SDIP*5

15 14 22

P60

Port input

(Hi-Z)

I/O port

SIN1

Serial data input pin f or UART ch1.

This pin is used continuously when input opera-

tion is enabled for UART ch1. In this case, do not

use as a general input pin.

16 15 23

P61

I/O port

SOT1 Serial data output pin for UART ch1.

Output operates when UART ch1 output is en-

abled.

17 16 24

P62

I/O port

SCK1 Serial clock I/O pin for UART ch1.

Output opera tes wh en UART ch1 clo ck out put is

enabled.

18 17 25

P63

I/O port

INT7

This pin can be used as interrupt request input

ch7. In stand by mode, this pin can operate as an

input by setting the bit corresponding to EN7 to

“1” and setting as an input port.

DTTI Fixed pin level input pin when RTO0 to RTO5

pins are used. Input is enabled when “input en-

abled” set in the waveform ge nerator.

58 57 1 C*2 ⎯

Capacitor

pin,

power

supply

input

Capacitor pin for stabilizing the power supply.

Connect an exte rnal ceramic capacitor of approx-

imately 0.1 µF.

19 18 26 MD0 B

Mode

input pins

Input pin for setting the operation mode.

Connect directly to VCC or VSS.

21 20 28 MD1 B Input pin for setting the operation mode.

Connect directly to VCC or VSS.

22 21 29 MD2 B/I

Input pin for setting the operation mode.

Connect directly to VSS. Mask ROM products

have a built-in pull-up re si st or and its circuit typ e

is “I”.

25, 50 24, 49 32, 57 VSS ⎯Power

supply

inputs

Power supply (GND) input pin

57 56 64 VCC ⎯MB90560 series is power supply (5 V) input pin

MB90565 series is power supp ly (3.3 V) inp ut pin

MB90560/565 Series

DS07-13715-5E 13

■I/O CIRCUITS

(Continued)

Type Circuit Remarks

• Oscillation circuit

Internal oscillation feedback

resistor (Rf)

B• CMOS hysteresis input

• CMOS hysteresis I/O pin with pull-up

control

CMOS output

CMOS hysteresis input (with input cut-

off function in standby mode)

Internal pull-up resistor (Rp)

< Note >

• The pull-up resistor is activ e when the

port is set as an input.

• CMOS hysteresis I/O pin

CMOS output

CMOS hysteresis input (with input cut-

off function in standby mode)

< Notes >

• The I/O port output an d internal

resource output share the same out-

put buffer.

• The I/O port input and internal

resource input share the same input

buffer.

Xout

Nch

Pch Pch

Standby control signal

CMOS

hysteresis input

Pout

Pull-up control

Nout

CMOS hysteresis input

Standby control signal

Pch

Nch

Pout

Nout

CMOS hysteresis input

Standby control signal

Pch

Nch

MB90560/565 Series

14 DS07-13715-5E

(Continued)

Type Circuit Remarks

• CMOS I/O pin

CMOS output

CMOS hysteresis input (with input cut-

off function in standby mode)

< IOL = 12 mA >

• Analog/CMOS hysteresis I/O pin

CMOS output

CMOS hysteresis input (with input cut-

off function in standby mode)

Analog input (Analog input to A/D con-

v erter is enabled wh en “1” is set in the

corresponding bit in the analog input

enable register (ADER) .)

• The I/O port output and int ernal

resource output share the same out-

put buffer.

• The I/O port input and internal

resource input share the same input

buffer.

• A/D converter (AVR) voltage input pin

• CMOS hysteresis input

• Pull-up resistor

• CMOS hysteresis input

• Pull-down resistor

Pout

Nout

CMOS hysteresis input

Standby control signal

Pch

Nch

Pout

Nout

CMOS hysteresis input

Standby control signal

A/D converter analog input

Pch

Nch

Pch

Nch

Pch AVR input

Analog input

enable signal

from A/D converter

Nch

RCMOS hysteresis input

Pull-up resistor

RCMOS hysteresis input

Pull-down resistor

MB90560/565 Series

DS07-13715-5E 15

■HANDLING DEVICES

Take note of the following nine points when handling devices :

• Do not exceed maximum rated voltage (to prevent latc h- up )

• Supply voltage stability

• Power-on precautions

• Treatment of unused pins

• Treatment of A/D conv erter power supply pins

• Notes on using an external clock

• Power supply pins

• Sequence for connecting and disconnecting the A/D converter power supply and analog input pins

• Notes on using the DIV A, Ri and DIVW A, RWi instructions

• Device Handling Precautions

(1) Do not ex ceed maximum rated voltage (to prevent latch-up)

Do not apply a voltage grater t han VCC or less than VSS to the MB90560/565 series input or output pins. Also

ensure that the voltage between VCC and VSS does not exceed the rating. Applying a voltage in excess of the

ratings may result in latch-up causing thermal damage to circuit el ements.

Similarly, when connecting or disconnecting the power to the analog power supply (AVCC, AVR) and analog

inputs (AN0 to AN7) , ensure that the analog power supply voltages do not exceed the digital voltage (VCC) .

(2) Supply voltage stability

Rapid changes in t he VCC supply v olt age ma y cau se the device to misopera te . Accordingly, ensu re that th e VCC

power supply is stable. The standard for power supply voltage stability is a peak-to-peak VCC r ipple voltage at

the supply frequency (50 to 60 Hz) of 10% or less of VCC and a transient fluctuation in the voltage of 0.1 V/ms

or less when turning the power supply on or off.

(3) Power-on precautions

To prev ent miso perat ion of the internal regulator circuit, en sure that the v oltag e rise time at power -on is at least

50 µs (between 0.2 V to 2.7 V) .

(4) Treatment of unused pins

Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to

latchup. Always pull-up or pull-down unused pins using a 2 kΩ or larger resistor.

If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same

way as input pins.

(5) Treatment of A/D converter po wer supply pins

If not using the A/D con verter, connect the analog power supply pins so that AVCC = AVR = VCC and AVSS = VSS.

(6) Notes on using an external clock

Even if using an ex ternal clock, an oscillation stabilization delay time occurs after a power-on reset and when

recov e ring from stop mode in the same wa y as when an oscillator is connected. When using an e xternal clock,

drive the X0 pin only and leave the X1 pin open.

MB90560/565 Series

16 DS07-13715-5E

Example of using an external clock

(7) Power supply pins

The multiple VCC and VSS pins are connected together in the internal device design so as to pre vent misoperation

such as latch-up. However, always connect all VCC and VSS pins to the same potential externally to minimize

spurious radiation, pre v ent misoperation of strobe signals due to increases in th e ground le vel, and maintain the

overall output current rating.

Also, ensure that the impedance of the VCC and VSS connections to the power supply is as low as possible.

To minimize these problems, connect a bypass capacitor of approximately 0.1 µF between VCC and VSS. Connect

the capacitor close to the VCC and VSS pins.

(8) Sequence for connecting and disconnecting power supply

Do not apply voltage to the A/D converter power supply pins (AVCC, AVR , AVSS) or a na log in pu ts (AN0 to AN7)

until the digital power supply (VCC) is turn ed on. When turning the device off, tur n off the digital power supply

after disconnecting the A/D converter po wer supply and analog inputs . When turning the pow er on or off, ensure

that AVR does not exceed AVCC.

When using the I/O ports that share pins with t he ana log in put s, ensure that the inp ut voltage does not exceed

AVCC (turning the analog and digital power supplies on and off simultaneously is OK) .

(9) Conditions when output from ports 0 and 1 is undefined

After turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabilization

delay time controlled by the regulator circuit (dur ing the power-on reset) if the RST pin level is “H”. When the

RST pin level is “L”, ports 0 and 1 go to high impedance.

Figures 1 and 2 show the timing (for the MB90F562B and MB90V560) .

Note that this und ef ined o ut put p eriod does no t occu r on p rodu cts with out a n in ternal regulator circ uit as the se

products do not have an oscillation stabiliz ation delay time.

(MB90561A, MB90562A, MB90F568, MB90567 and MB90568)

X1OPEN

MB90560/565 series

MB90560/565 Series

DS07-13715-5E 17

•Figure 1 Timing chart for undefined output from ports 0 and 1 (When RST pin level is “H”)

Oscillation stabilization delay time*2

Regulator circuit

stabilization delay time*1

VCC (Power supply pin)

PONR (Power-on reset) signal

RST (External asynchronous reset) signal

RST (Internal reset) signal

Oscillation clock signal

KA (Internal operating clock A) signal

KB (Internal operating clock B) signal

PORT (port output) signal Undefined output time

*1 : Regulator circuit oscillation stabilization delay time :

217/Oscillation clock frequency (approx. 8.19 ms for a 16 MHz oscillation clock frequency)

*2 : Oscillation stabilization delay time :

218/Oscillation clock frequency (approx. 16.38 ms for a 16 MHz oscillation clock frequency )

MB90560/565 Series

18 DS07-13715-5E

•Figure 2 Timing chart for ports 0 and 1 going to high impedance state (When RST pin level is “L”)

(10) Notes on using the DIV A, Ri and DIVW A, RWi instructions

The location in which the remainder value produced by the signed division instructions “DIV A, Ri” and “DIVW

A, RWi” is stored depends on the bank register. The remainder is stored in an address in the memory bank

specified in the bank register.

Set the bank register to “00H” when using the “DIV A, Ri” and “DIVW A, RWi” instructions.

(11) Notes on using REALOS

The extended intelligent I/O service (EI2OS) cannot be used when using REALOS.

(12) Caution on Operations during PLL Clock Mode

If the PLL cloc k m ode is selected in the microcont roller, it may at tempt to cont inue the operat ion using the f ree-

running frequency of the self oscillation circuit in the PLL circuitry even if the oscillator is out of place or the clock

input is stopped. Performance of this operation, however, cannot be guaranteed.

Oscillation stabilization delay time*2

Regulator circuit

stabilization delay time*1

VCC (Power supply pin)

PONR (Power-on reset) signal

RST (External asynchronous reset) signal

RST (Internal reset) signal

Oscillation clock signal

KA (Internal operating clock A) signal

KB (Internal operating clock B) signal

PORT (port output) signal High impedance

*1 : Regulator circuit oscillation stabilization delay time :

217/Oscillation clock frequency (approx. 8.19 ms for a 16 MHz oscillation clock frequency)

*2 : Oscillation stabilization delay time :

218/Oscillation clock frequency (approx. 16.38 ms for a 16 MHz oscillation clock frequency)

MB90560/565 Series

DS07-13715-5E 19

■BLOCK DIAGRAM

F2MC-16LX

CPU

RAM

ROM

UART

ch0

UART

ch1

P00

P07

P10

P17

P20

P27

P30

P37

P40

P46

P50

P57

P60

P63

X0, X1

RST

MD0 to MD2

SIN0

SOT0

SCK0

SIN1

SOT1

SCK1

INT0 to INT7

AVCC

AVR

AVSS

AN0 to AN7

TO1

TIN1

TO0

TIN0

PPG0 to PPG5

FRCK

IN0 to IN3

RTO0

RTO1

RTO2

RTO3

RTO4

RTO5

DTTI

Clock

control circuit

Interrupt controller

8/16-bit

PPG timer

ch0 to ch5*

Input

capture

ch0 to ch3

16-bit

freerun

timer

Output

compare

ch0 to ch5

Waveform generator circuit

8/10-bit

A/D converter

16-bit

reload timer

ch0

16-bit

reload timer

ch1

DTP/

external interrupts

Internal data bus

I/O ports (Ports 0, 1, 2, 3, 4, 5, and 6)

* : Channel number s when used as 8-bit timers . Three channels (ch1, ch 3, and ch5) are a vailab le when used

as 16-bit timers.

Note: The I/O ports share pins with the various peripheral functions (resou rces) .

See the Pin Assignment and Pin Description sections for details.

Note that, if a pin is used by a peripheral function (resource) , it may not be used as an I/O port.

MB90560/565 Series

20 DS07-13715-5E

■MEMORY MAP

Memory map of MB90560/565 series

Notes : • When specified in the ROM mirror function register, the upper part of 00 bank (“004000H to 00FFFFH”)

contains a mirror of the data in the upper part of FF bank (“FF4000 H to FFFFFFH”) .

• See “10. ROM Mirror Function Selection Module” in the Peripheral Functions section for details of the

ROM mirror function settings.

Remarks : • The ROM mirror function is provided so the C compiler’s small memory model can be used.

• The lower 16 bits of the FF bank and 00 bank addresses are the same. However, as the FF bank ROM

area exceeds 48 KBytes, the entire ROM dat a area cannot be mirrored in 00 bank.

• When using the C compiler’s small memory model, locating data tables in the area “FF4000H to

FFFFFFH” makes the image of the data visible in the “004000H to 00FFFFH” area. Th is me an s th at

data tables located in ROM can be referenced without needing to declare far pointers.

FFFFFFH

FF0000H

010000H

004000H

000100H

0000C0H

000000H

Single chip mode

(with ROM mirror function)

ROM area

Address #1

ROM area

(image of FF bank)

Address #2

Address #3 RAM

area Registers

Peripherals Access prohibited

* : “V” products do not contain internal ROM. Treat this address as the ROM decode area

used by the tools.

Part No. Address#1 Address#2 Address#3

MB90561A FF8000H008000H000500H

MB90562A FF0000H004000H000900H

MB90F562B FF0000H004000H000900H

MB90567 FE8000H004000H001100H

MB90568 FE0000H004000H001100H

MB90F568 FE0000H004000H001100H

MB90V560 FE0000H*004000H*001100H

MB90560/565 Series

DS07-13715-5E 21

■I/O MAP

(Continued)

Address Abbreviat-

ed Register

Name Register name Read/

Write Resource Name Initial Value

000000HPDR0 Port 0 data register R/W Port 0 XXXXXX XXB

000001HPDR1 Port 1 data register R/W Port 1 XXXXXX XXB

000002HPDR2 Port 2 data register R/W Port 2 XXXXXX XXB

000003HPDR3 Port 3 data register R/W Port 3 XXXXXX XXB

000004HPDR4 Port 4 data register R/W Port 4 XXXXXX XXB

000005HPDR5 Port 5 data register R/W Port 5 XXXXXX XXB

000006HPDR6 Port 6 data register R/W Port 6 XXXXXX XXB

000007H

00000FHAccess prohibited

000010HDDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0B

000011HDDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0B

000012HDDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0B

000013HDDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0B

000014HDDR4 Port 4 direction register R/W Port 4 X 0 0 0 0 0 0 0B

000015HDDR5 Port 5 direction register R/W Port 5 0 0 0 0 0 0 0 0B

000016HDDR6 Port 6 direction register R/W Port 6 XXXX 0 0 0 0B

000017HADER Analog input enable register R/W Port 5,

A/D converter 1 1 1 1 1 1 1 1B

000018H

00001FHAccess prohibited

000020HSMR0 Mode register ch0 R/W

UART0

0 0 0 0 0 X 0 0B

000021HSCR0 Control register ch0 W, R/W 0 0 0 0 0 1 0 0B

000022HSIDR0 Input data register ch0 R XXXXXXXXB

SODR0 Output data register ch0 W

000023HSSR0 Status register ch0 R, R/W 0 0 0 0 1 0 0 0B

000024HSMR1 Mode register ch1 R/W

UART1

0 0 0 0 0 X 0 0B

000025HSCR1 Control register ch1 W, R/W 0 0 0 0 0 1 0 0B

000026HSIDR1 Input data register ch1 R XXXXXXXXB

SODR1 Output data register ch1 W

000027HSSR1 Status register ch1 R, R/W 0 0 0 0 1 0 0 0B

000028HAccess prohibited

000029HCDCR0 Communication prescaler

control register ch0 R/W Communication

prescaler 0 XXX 0 0 0 0B

MB90560/565 Series

22 DS07-13715-5E

(Continued)

Address Abbreviat-

ed Register

Name Register name Read/

Write Resource Name Initial Value

00002AHAccess prohibited

00002BHCDCR1 Communication prescaler

control register ch1 R/W Communication

prescaler 0 XXX 0 0 0 0B

00002CH

00002FHAccess prohibited

000030HENIR DTP/externa l interrupt enable register R/W

DTP/external

interrupts

0 0 0 0 0 0 0 0B

000031HEIRR DTP/external interrupt request register R/W XXXXXXXXB

000032HELVR Requ est level setting register (lower) R/W 0 0 0 0 0 0 0 0B

000033HRequ est level setting register (upper) R/W 0 0 0 0 0 0 0 0 B

000034HADCS0 A/D control status register (lower) R/W

8/10-bit

A/D converter

0 0 0 0 0 0 0 0B

000035HADCS1 A/D control status register (upper) W, R/W 0 0 0 0 0 0 0 0B

000036HADCR0 A/D data register (lower) R XXXXXXXXB

000037HADCR1 A/D data register (upper) R, W 0 0 0 0 0 XXXB

000038HPRLL0 PPG reload register ch0 (lower) R/W

8/16-bit PPG timer

XXXXXXXXB

000039HPRLH0 PPG reload register ch0 (upper) R/W XXXXXXXXB

00003AHPRLL1 PPG reload register ch1 (lower) R/W XXXXXXXXB

00003BHPRLH1 PPG reload register ch1 (upper) R/W XXXXXXXXB

00003CHPPGC0 PPG control register ch0 (lower) R/W 0 0 0 0 0 0 0 1B

00003DHPPGC1 PPG control register ch1 (upper) R/W 0 0 0 0 0 0 0 1B

00003EHPCS01 PPG clock control register ch0, ch1 R/W 0 0 0 0 0 0 XXB

00003FHAccess prohibited

000040HPRLL2 PPG reload register ch2 (lower) R/W

8/16-bit PPG timer

XXXXXXXXB

000041HPRLH2 PPG reload register ch2 (upper) R/W XXXXXXXXB

000042HPRLL3 PPG reload register ch3 (lower) R/W XXXXXXXXB

000043HPRLH3 PPG reload register ch3 (upper) R/W XXXXXXXXB

000044HPPGC2 PPG control register ch2 (lower) R/W 0 0 0 0 0 0 0 1B

000045HPPGC3 PPG control register ch3 (upper) R/W 0 0 0 0 0 0 0 1B

000046HPCS23 PPG clock control register ch2, ch3 R/W 0 0 0 0 0 0 XXB

000047HAccess prohibited

000048HPRLL4 PPG reload register ch4 (lower) R/W

8/16-bit PPG timer

XXXXXXXXB

000049HPRLH4 PPG reload register ch4 (upper) R/W XXXXXXXXB

00004AHPRLL5 PPG reload register ch5 (lower) R/W XXXXXXXXB

00004BHPRLH5 PPG reload register ch5 (upper) R/W XXXXXXXXB

00004CHPPGC4 PPG control register ch4 (lower) R/W 0 0 0 0 0 0 0 1B

MB90560/565 Series

DS07-13715-5E 23

(Continued)

Address Abbreviat-

ed Register

Name Register name Read/

Write Resource Name Initial Value

00004DHPPGC5 PPG control regist er ch5 (upper) R/W 8/16-bit PPG timer 0 0 0 0 0 0 0 1B

00004EHPCS45 PPG clock control register ch4, ch5 R/W 0 0 0 0 0 0 XXB

00004FHAccess prohibited

000050HTMRR0 8-bit reload register ch0 R/W

Waveform

generator

XXXXXXXXB

000051HDTCR0 8-bit timer control register ch0 R/W 0 0 0 0 0 0 0 0B

000052HTMRR1 8-bit reload register ch1 R/W XXXXXXXXB

000053HDTCR1 8-bit timer control register ch1 R/W 0 0 0 0 0 0 0 0B

000054HTMRR2 8-bit reload register ch2 R/W XXXXXXXXB

000055HDTCR2 8-bit timer control register ch2 R/W 0 0 0 0 0 0 0 0B

000056HSIGCR Waveform control register R/W 0 0 0 0 0 0 0 0B

000057HAccess prohibited

000058HCPCLR Compare clear register (lower) R/W

16-bit freerun

timer

XXXXXXXXB

000059HCompare clear register (upper) R/W XXXXXXXXB

00005AHTCDT Timer data register (lower) R/W 0 0 0 0 0 0 0 0B

00005BHTimer data register (upper) R/W 0 0 0 0 0 0 0 0B

00005CHTCCS Timer control/st atus register (lower) R/W 0 0 0 0 0 0 0 0B

00005DHTimer control/st atus register (upper) R/W 0 XX 0 0 0 0 0B

00005EHAccess prohibited

00005FH

000060HIPCP0 Input capture data regi ster ch0 (lower) R

Input capture

XXXXXXXXB

000061HInput capture data register ch0 (upper) R XXXXXXXXB

000062HIPCP1 Input capture data register ch1 (lower) R XXXXXXXXB

000063HInput capture data register ch1 (upper) R XXXXXXXXB

000064HIPCP2 Input capture data register ch2 (lower) R XXXXXXXXB

000065HInput capture data register ch2 (upper) R XXXXXXXXB

000066HIPCP3 Input capture data register ch3 (lower) R XXXXXXXXB

000067HInput capture data register ch3 (upper) R XXXXXXXXB

000068HICS01 Input capture control register 01 R/W 0 0 0 0 0 0 0 0B

000069HAccess prohibited

00006AHICS23 Input capture control register 23 R/W Input capture 0 0 0 0 0 0 0 0B

00006BH

00006EHAccess prohibited

MB90560/565 Series

24 DS07-13715-5E

(Continued)

Address Abbreviat-

ed Register

Name Register name Read/

Write Resource Name Initial Value

00006FHROMM ROM mirror function selection register W ROM mirror

function selection

module XXXXXXX 1B

000070HOCCP0 Compare register ch0 (lower) R/W

Output compare

XXXXXXXXB

000071HCompare register ch0 (upper) R/W XXXXXXXXB

000072HOCCP1 Compare register ch1 (lower) R/W XXXXXXXXB

000073HCompare register ch1 (upper) R/W XXXXXXXXB

000074HOCCP2 Compare register ch2 (lower) R/W XXXXXXXXB

000075HCompare register ch2 (upper) R/W XXXXXXXXB

000076HOCCP3 Compare register ch3 (lower) R/W XXXXXXXXB

000077HCompare register ch3 (upper) R/W XXXXXXXXB

000078HOCCP4 Compare register ch4 (lower) R/W XXXXXXXXB

000079HCompare register ch4 (upper) R/W XXXXXXXXB

00007AHOCCP5 Compare register ch5 (lower) R/W XXXXXXXXB

00007BHCompare register ch5 (upper) R/W XXXXXXXXB

00007CHOCS0 Compare control register ch0 (lower) R/W 0 0 0 0 XX 0 0B

00007DHOCS1 Compare control register ch1 (upper) R/W XXX 0 0 0 0 0B

00007EHOCS2 Compare control register ch2 (lower) R/W 0 0 0 0 XX 0 0B

00007FHOCS3 Compare control register ch3 (upper) R/W XXX 0 0 0 0 0B

000080HOCS4 Compare control register ch4 (lower) R/W 0 0 0 0 XX 0 0B

000081HOCS5 Compare control register ch5 (upper) R/W XXX 0 0 0 0 0B

000082HTMCSR0 : L Timer co ntrol status register ch0 (l ower) R/W

16-bit reload timer

0 0 0 0 0 0 0 0B

000083HTMCSR0 : H Timer control status register ch0 (upper) R/W XXXX 0 0 0 0B

000084HTMR0 16-bit timer register ch0 (lower) R XXXXXXXXB

TMRLR0 16-bit reload register ch0 (lower) W XXXXXXXXB

000085HTMR0 16-bit timer register ch0 (upper) R XXXXXXXXB

TMRHR0 16-bit reload register ch0 (upper) W XXXXXXXXB

000086HTMCSR1 : L Timer control status regist er ch1 (lower) R/W 0 0 0 0 0 0 0 0B

000087HTMCSR1 : H Timer control status register ch1 (upper) R/W XXXX 0 0 0 0B

000088HTMR1 16-bit timer register ch1 (lower) R XXXXXXXXB

TMRLR1 16-bit reload register ch1 (lower) W XXXXXXXXB

000089HTMR1 16-bit timer register ch1 (upper) R XXXXXXXXB

TMRHR1 16-bit reload register ch1 (upper) W XXXXXXXXB

MB90560/565 Series

DS07-13715-5E 25

(Continued)

Address Abbreviat-

ed Register

Name Register name Read/

Write Resource Name Initial Value

00008AH

00008BHAccess prohibited

00008CHRDR0 Port 0 pull-up resistor setting register R/W Por t 0 0 0 0 0 0 0 0 0 B

00008DHRDR1 Port 1 pull-up resistor setting register R/W Por t 1 0 0 0 0 0 0 0 0 B

00008EH

00009DHAccess pr ohibited

00009EHPACSR Program add ress detection

control status register R/W Address match

detection 0 0 0 0 0 0 0 0 B

00009FHDIRR Delayed interrupt request/clear register R/W Delayed interrupt XXXXXXX 0B

0000A0HLPMCR Low power consu mption mode register W, R/W Low power

consumption

control circuit 0 0 0 1 1 0 0 0B

0000A1HCKSCR Clock selection register R, R/W Clock 1 1 1 1 1 1 0 0B

0000A2H

0000A7HAccess prohibited

0000A8HWDTC Watchdog control register R/W Watchdog timer 1 XXXX 1 1 1B

0000A9HTBTC Timebase timer control register W, R/W Timebase timer 1 XX 0 0 1 0 0B

0000AAH

0000ADHAccess prohibited

0000AEHFMCS Flash memory control status register R, W,

R/W Flash memory 0 0 0 0 0 0 0 0B

0000AFHAccess prohibited

0000B0HICR00 Interrup t control register 00 (for writing) W, R/W

Interrupts

XXXX 0 1 1 1B

Interrupt cont rol register 00 ( for reading) R, R/W XX 0 0 0 1 1 1 B

0000B1HICR01 Interrup t control register 01 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt cont rol register 01 ( for reading) R, R/W XX 0 0 0 1 1 1 B

0000B2HICR02 Interrup t control register 02 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt cont rol register 02 ( for reading) R, R/W XX 0 0 0 1 1 1 B

0000B3HICR03 Interrup t control register 03 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt cont rol register 03 ( for reading) R, R/W XX 0 0 0 1 1 1 B

0000B4HICR04 Interrup t control register 04 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt cont rol register 04 ( for reading) R, R/W XX 0 0 0 1 1 1 B

0000B5HICR05 Interrup t control register 05 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt cont rol register 05 ( for reading) R, R/W XX 0 0 0 1 1 1 B

MB90560/565 Series

26 DS07-13715-5E

(Continued)

Address Abbreviat-

ed Register

Name Register name Read/

Write Resource Name Initial Va lue

0000B6HICR06 Interrupt control register 06 (for writing) W, R/W

Interrupts

XXXX 0 1 1 1B

Interrupt control register 06 (for reading) R, R/W XX 0 0 0 1 1 1B

0000B7HICR07 Interrupt control register 07 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 07 (for reading) R, R/W XX 0 0 0 1 1 1B

0000B8HICR08 Interrupt control register 08 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 08 (for reading) R, R/W XX 0 0 0 1 1 1B

0000B9HICR09 Interrupt control register 09 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 09 (for reading) R, R/W XX 0 0 0 1 1 1B

0000BAHICR10 Interrupt control register 10 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 10 (for reading) R, R/W XX 0 0 0 1 1 1B

0000BBHICR11 Interrupt control register 11 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 11 (for reading) R, R/W XX 0 0 0 1 1 1B

0000BCHICR12 Interrupt control register 12 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 12 (for reading) R, R/W XX 0 0 0 1 1 1B

0000BDHICR13 Interrupt control register 13 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 13 (for reading) R, R/W XX 0 0 0 1 1 1B

0000BEHICR14 Interrupt control register 14 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 14 (for reading) R, R/W XX 0 0 0 1 1 1B

0000BFHICR15 Interrupt control register 15 (for writing) W, R/W XXXX 0 1 1 1B

Interrupt control register 15 (for reading) R, R/W XX 0 0 0 1 1 1B

0000C0H

0000FFHUnused area

000100H

#HRAM area

001FEFHReserved area

001FF0H

PADR0

Program address detection register ch0

(lower) R/W

Address match

detection

XXXXXXXXB

001FF1HProgram address detection register ch0

(middle) R/W XXXXXXXXB

001FF2HProgram address detection register ch0

(lower) R/W XXXXXXXXB

MB90560/565 Series

DS07-13715-5E 27

(Continued)

• Read/write notation

• Initial value notation

Address Abbreviat-

ed Register

Name Register name Read/

Write Resource Name Initial Va lue

001FF3H

PADR1

Program address detection register ch1

(lower) R/W

Address match

detection

XXXXXXXXB

001FF4HProgram address detection register ch1

(middle) R/W XXXXXXXXB

001FF5HProgram address detection register ch1

(lower) R/W XXXXXXXXB

001FF6H

001FFFHUnused area

R/W : Reading and writing permitted

R : Read-only

W : Write-only

0 : Initial value is “0”.

1 : Initial value is “1”.

X : Initial value is undefined.

MB90560/565 Series

28 DS07-13715-5E

■INTERRUPTS, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt EI2OS

Sup-

port

Interrupt Vector Inte rrupt Control

No.*Address ICR Address

Reset #08 08HFFFFDCH⎯⎯High

INT 9 instruction #09 09HFFFFD8H⎯⎯

Exception #10 0AHFFFFD4H⎯⎯

A/D converter conver sion complete #11 0BHFFFFD0HICR00 0000B0H

Output compare channel 0 match #13 0DHFFFFC8HICR01 0000B1H

8/16-bit PPG timer 0 counter borrow #14 0EHFFFFC4H

Output compare channel 1 match #15 0FHFFFFC0HICR02 0000B2H

8/16-bit PPG timer 1 counter borrow #16 10HFFFFBCH

Output compare channel 2 match #17 11HFFFFB8HICR03 0000B3H

8/16-bit PPG timer 2 counter borrow #18 12HFFFFB4H

Output compare channel 3 match #19 13HFFFFB0HICR04 0000B4H

8/16-bit PPG timer 3 counter borrow #20 14HFFFFACH

Output compare channel 4 match #21 15HFFFFA8HICR05 0000B5H

8/16-bit PPG timer 4 counter borrow #22 16HFFFFA4H

Output compare channel 5 match #23 17HFFFFA0HICR06 0000B6H

8/16-bit PPG timer 5 counter borrow #24 18HFFFF9CH

DTP/external interr upt channel 0/1 detection #25 19HFFFF98HICR07 0000B7H

DTP/external interr upt channel 2/3 detection #26 1AHFFFF94H

DTP/external interr upt channel 4/5 detection #27 1BHFFFF90HICR08 0000B8H

DTP/external interr upt channel 6/7 detection #28 1CHFFFF8CH

8-bit ti mer 0/1/2 counter borrow #29 1DHFFFF88HICR09 0000B9H

16-bit reload ti mer 0 underflow #30 1EHFFFF84H

16-bit freerun timer overflow #31 1FHFFFF80HICR10 0000BAH

16-bit reload ti mer 1 underflow #32 20HFFFF7CH

Input capture channel 0/1 #33 21HFFFF78HICR11 0000BBH

16-bit freerun timer clear #34 2 2HFFFF74H

Input capture channel 2/3 #35 23HFFFF70HICR12 0000BCH

Timebase timer #36 24HFFFF6CH

UART1 receive #37 25HFFFF68HICR13 0000BDH

UART1 send #38 26HFFFF64H

UART0 receive #39 27HFFFF60HICR14 0000BEH

UART0 send #40 28HFFFF5CH

Flash memory status #41 29HFFFF58HICR15 0000BFH

Delay interrupt output module #42 2AHFFFF54HLow

MB90560/565 Series

DS07-13715-5E 29

: Supported

: Not supported

: Supported, includes EI2OS stop function

: Available if the interrupt that shares the same ICR is not used.

* : If two or more interrupts with the same level occur simultaneously, the interrupt with the lower interrupt vector

number has priority

MB90560/565 Series

30 DS07-13715-5E

■PERIPHERAL FUNCTIONS

1. I/O Ports

• The I/O ports can be used as general-purpose I/O por ts (parallel I/O ports) . The MB90560/565 series have

7 ports (51 pins) . The ports share pins with the inputs and out puts of the peripheral functions.

• The port data registers (PDR) are used to output data to the I/O pins and read the data input from the I/O

ports. Similarly, the port direction registers (DDR) set the I/O direction (input or output) f or each individual port

bit.

• The following table list s t he I/O ports and the peripheral functions with which they share pins.

Notes : • Pins P30 to P35 of po rt 3 can dr ive a maximum of IOL = 12 mA.

• P ort 5 shares pins with the analog inputs . When using port 5 pins as a gener al-purpose ports, ensure that

the corresponding analog input enable register (ADER) bits are set to “0B”. ADER is initialized to “FFH”

after a reset.

•Block diagram for port 0 and 1 pins

Pin Name (P ort) Pin Name (Periphera l) Peripheral Function that Shares Pin

Port 0 P00-P07 ⎯Not shared

Port 1 P10-P16 INT0-INT6 External interrupts

P17 FRCK Freerun timer external input

Port 2 P20-P23 TIN0, TO0, TIN1, TO1 16-bit reload t imer 0 and 1

P24-P27 IN0-IN3 Input capture 0 to 3

Port 3 P30-P35 RTO0-RTO5 Output compare

P36, P37 SIN0, SOT0 UART0

Port 4 P40 SCK0 UART0

P41-P46 PPG0-PPG5 8/16-bit PPG timer

Port 5 P50-P57 AN0-AN7 8/10-bit A/D converter

Port 6

P60-P62 SIN1, SOT1, SCK1 UART1

P63 INT7 External interrupts

DTTI Waveform generat or

Internal data bus

Pull-up resistor

setting register

(PDRx)

PDRx read

PDRx

write

Port data

(PDRx)

Port direction

(DDRx)

Input/output

selection circuit

Input

buffer

Output

buffer

Standby control (LPMCR : SPL = "1")

Port pin

Internal

pull-up resistor

MB90560/565 Series

DS07-13715-5E 31

• Block diagram for port 2, 3, 4, and 6 pins

•Block diagram for port 5 pins

Notes: • When using as an input port, set the corresponding bit in the port 5 direction register (DDR5) to “0” and

set the corresponding bit in the analog input enable register (ADER) to “0”.

• When using a s an analog input pin, set the corresponding bit in the port 5 direction regi ster (DDR5) to “0”

and set the corr esponding bit in the analog input enable register (ADER) to “1”.

Internal data bus

PDRx read

PDRx

write

Port data

(PDRx)

Port direction

(DDRx)

Resource input

Input/output

selection circuit

Resource output control signal

Resource output

Input

buffer

Output

buffer

Standby control (LPMCR : SPL = "1")

Port

Internal data bus

Analog input

enable register

(ADER)

PDR5 read

PDR5

write

Port data

(PDR5)

Port direction

(DDR5)

Input/output

selection circuit

Analog converter

analog input signal

Input

buffer

Output

buffer

Standby control (LPMCR : SPL = "1")

Port 5

MB90560/565 Series

32 DS07-13715-5E

2. Timebase Timer

• The timeba se timer is an 18-bit free run tim er (timebase timer/ counter) tha t counts up synchronized with th e

main clock (oscillation clock : HCLK divided into 2) .

• The timer can generate interrupt requests at a specified interval, with four different interval time settings

available.

• The timer supplies the operating cloc k for peripheral functions including the oscillation stabilization delay timer

and watchdog timer.

•Timebase timer interval settings

Notes : • HCLK : Oscillation clock frequency

• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.

•Period of clocks supplied from timebase timer

Notes : • HCLK : Oscillation clock frequency

• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.

Internal Count Clock Period Interval Time

2/HCLK (0.5 µs)

212/HCLK (approx. 1.024 ms)

214/HCLK (approx. 4.096 ms)

216/HCLK (approx. 16.384 ms)

219/HCLK (approx. 131.072 ms)

Peripheral Function Clock Period

Oscillation stabilization delay for

the main clock

210/HCLK (approx. 0.256 ms)

213/HCLK (approx. 2.048 ms)

215/HCLK (approx. 8.192 ms)

217/HCLK (approx. 32.768 ms)

Watchdog timer

212/HCLK (approx. 1.024 ms)

214/HCLK (approx. 4.096 ms)

216/HCLK (approx. 16.384 ms)

219/HCLK (approx. 131.072 ms)

MB90560/565 Series

DS07-13715-5E 33

•Block diagram

The actual inte rrupt request number for the timebase timer is :

Interrupt request number : #36 (24H)

TBIE TBOF TBR TBC1 TBC0

× 21× 22× 23× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218

OF OF OF OF

To PPG timer To watchdog timer

Timebase timer/counter

HCLK

divided into 2

To oscillation stabilization

delay time selector

in clock controller

Reset*1

Clear stop mode, etc.*2

Switch clock mode*3

Counter

clear circuit

TBOF clear TBOF set

Interval

timer selector

Timebase timer control register

(TBTC)

Timebase timer interrupt signal

OF : Overflow

HCLK : Oscillation clock frequency

*1 : Power-on reset, watchdog reset

*2 : Recovery from stop mode and timebase timer mode

*3 : Main → PLL clock

MB90560/565 Series

34 DS07-13715-5E

3. Watchdog Timer

• The watchdog timer is a timer/counter used to dete ct faults such as program run away.

• The watchdog timer is a 2-bit coun ter that counts the clock signal from the timebase timer or watch timer.

• Once started, the watchdog timer must be cleared before the 2-bit counter overflows. If an overflow occurs,

the CPU is reset.

•Interval time for the watchdog timer

Notes : • The difference between the maximum and minimum watchdog timer interval times is due to the timing when

the counter is cleared.

• As the w atchdog timer is a 2- bit counter th at counts the carry-up signal from the t imebase t imer or w atch

timer, clearing the timebase timer (when operating on HCLK) or the watch timer (when operating on SCLK)

lengthens the time un til the watchdog timer reset is generated.

•Watchdog timer cou nt clock

• Events that stop the watchdog timer

1 : Stop due to a power-on reset

2 : Watchdog reset

• Events that clear the watchdog timer

1 : External reset input from the RST pin.

2 : Writing “0” to the software reset bit.

3 : Writing “0” to the watchdog control bit (second and subsequent times) .

4 : Changing to sleep mode (clears the watchdog timer and temporarily halts the count) .

5 : Changing to timebase timer mode (clears the watchdog timer and temporarily halts the count) .

6 : Changing to stop mode (clears the watchdog time r and temporarily halts the count) .

HCLK : Oscillati on Clock (4 MHz)

Min. Max. Clock Period

Approx. 3.58 ms Approx. 4.61 ms 214 ± 211 / HCLK

Approx. 14.33 ms Approx. 18.30 ms 216 ± 213 / HCLK

Approx. 57.23 ms Approx. 73.73 ms 218 ± 215 / HCLK

Approx. 458.75 ms Approx. 589.82 ms 218 ± 215 / HCLK

WTC : WDCS HCLK : Oscillation clock

PCLK : PLL clock

“0” Prohibited setting

“1” Count the timebase timer output.

MB90560/565 Series

DS07-13715-5E 35

•Block diagram

PONR STBR WRST ERST SRST WTE WT1 WT0

× 21× 22× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218

Watchdog timer control register (WDTC)

Watchdog timer

Reset

Change to sleep mode

Change to stop mode

Change to timebase

timer mode

Counter clear

control circuit Counter clock

selector 2-bit counter

Start

Clear

Watchdog timer

reset generation

circuit

To internal

reset circuit

Main clock

(HCLK divided into 2)

(Timebase timer/counter)

HCLK : Oscillation clock frequency

MB90560/565 Series

36 DS07-13715-5E

4. 16-Bit Reload Timers 0 and 1 (With Event Count Function)

• The 16-bit reload timers have the following functions.

• The count clock can be selected from three internal clocks or the external event clock.

• An interrupt to the CPU can be generated when an underflow occurs on 16-bit reload timer 0 or 1. This interrupt

allows the timers to be used as interval timers.

• Two different operation modes can be selected when an underflow occurs on 16-bit reload timer 0 or 1: one-

shot mode in which timer operation halts when an underflow occurs or reload mode in which the value in the

reload register is loaded into the timer and counting continues.

• Extended intelligent I/O service (EI2OS) is supported.

• The MB90560/565 series contains two 16-bit reload timer channels.

•16-bit reload timer operation modes

•Interval times for the 16-bit reload timers

Note : The values enclosed in ( ) and the example of interval t imes is for a machine clock frequency of 16 MHz.

φ is the machine clock frequency value for the calculation.

Remarks : 16-bit reload timer 0 can be used to generate the baud rate for UART0.

16-bit reload timer 1 can be used to generate the baud rate for UART1 and activati on trigger for the

A/D converter.

Count Clock Start Trigger Operation When an

Underflow Occurs

Internal clock

Software trigg er One-shot mode

Reload mode

External trigger One-shot mode

Reload mode

Event count mode

(external clock mode) Software trigg er One-shot mode

Reload mode

Count Clock Count Clock Period Example of Interval Times

Internal clock

21/φ (0.125 µs) 0.125 µs to 8.192 ms

23/φ (0.5 µs) 0.5 µs to 32.768 ms

25/φ (2.0 µs) 2.0 µs to 131.1 ms

Event count mode 23/φ or longer 0.5 µs or longer

MB90560/565 Series

DS07-13715-5E 37

•Block diagram

TMRLR0*1

TMRLR1*2

TMR0*1

TMR1*2

CLK

TIN0*1

TIN1*2

EN TO0*1

TO1*2

CLK

⎯⎯⎯⎯CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD UFINTE CNTE TRG

Internal data bus

16-bit reload register

Reload signal Reload

control circuit

16-bit timer register

Count clock generation circuit

Machine

clock φPrescaler Gate input Clock

pulse

detection

circuit

Clear

trigger Internal

clock

Pin Input

control

circuit

External clock

Clock

selector

Select

signal

Function selection

Timer control status register (TMCSR)

Wait signal

To UART0*1

To UART1 and

A/D converter trigger*2

Output control circuit

Output signal

generation circuit Pin

Operation

control circuit

Interrupt

request output

#30 (1EH) *1, *3

#32 (20H) *2, *3

*1 : Channel 0

*2 : Channel 1

*3 : Interr upt number

*4 : Underflow

MB90560/565 Series

38 DS07-13715-5E

5. Multi-Function Timer

• Based on the 16- bit freerun timer, t he multi-f unction time r can be used t o gener ate 12 indepen dent w a v ef orm

outputs and to measure inpu t pulse widths and exter nal clock periods.

•Structure of multi-function timer

• 16-bit freerun timer (1 channel)

The 16-bit freerun timer consists of a 16-bit up-counter (timer data register (TCDT) ) , compare clear register

(CPCLR) , timer control status register (TCCS) , and prescaler.

The count output value from the 16-bit freerun timer provides the base time for the input capture and output

compare functions.

• The count clock can be selected from the following eight clocks :

1/φ, 2/φ, 4/φ, 8/φ, 16/φ, 32/φ, 64/φ, 128/φ

φ : Machine clock frequency

• An interrupt can be gener at ed when t he 1 6-bit freerun timer overflows or when the 16-bit freerun timer count

is cleared to “0000 H” due t o a match occurring betw een th e value in the compare clear r egist er (CPCLR) and

the count in the 16-bit freerun timer (TCCS : ICRE = “1”, MODE = “1”) .

• The 16-bit freerun timer is clea red to “0000H” whe n a reset occurs , on se tting the timer clear bit (SCLR) in t he

timer contro l status reg ister (T CCS) , when a c ompare match o ccurs b etween the 16-bit f reer un timer coun t

and the value in the compare clear register (CPCLR) (TCCS : MODE = “1”) , or by writing “0000H” to the timer

data register (TCDT) .

• Output compare (6 channels)

The output compare unit consists of compare registers (OCCP0 to OCCP5) , compare control registers (OCS0

to OCS5) , and compare output latches.

When a match occurs between a compare register (OCCP0 to OCCP5) value and the count from the 16-bit

freerun timer, the output compare can inver t the level of the corresponding output compare pin and generate

an interrupt.

• The compare registers (OCCP0 to OCCP5) operate independently for each channel. Each of the compare

registers (OCCP0 to OCCP5) has a corresponding output pin and an interrupt request flag in the channel’s

compare control regist er (lower) (OCS0, OCS2, OCS4) .

• Two channels of the compare registers (O CCP0 to OCCP5) can be used to invert the output pins.

• An interrupt can be output when a match occurs between a compare register (OCCP0 to OCCP5) and the

count from the 16-b it freer un timer (O CS0, OCS2, OCS4 : IOP0 = “1”, IOP1 = “1”) . (OCS0, OCS2, OCS4 :

IOE0 = “1”, IOE1 = “1”)

• The initial output levels for the output compare pins can be set.

•Input capture (4 channels)

The input capture consists of e xternal input pins (IN0 to IN3) , corresponding input capture data registers (IPCP0

to IPCP3) , and input capture control status registers (ICS01, ICS23) .

The input capture can transfer the count value from the 16-bit freerun timer to the input capture data register

(IPCP0 to IPCP3) and ou tput an interrupt on detecting an activ e edge on the signal inp ut from the e xternal input

pin.

• Each channel of the input cap ture operates independently.

• The active edge (rising edge, falling edge, or either edge) on the external signal can be specified.

16-bit

freerun timer 16-bit

output compare 16-bit

input capture 8/16-bit

PPG timer Waveform

generator

1 ch 6 ch 4 ch 8 bit × 6 ch

16 bit × 3 ch 8-bit timer × 3 ch

MB90560/565 Series

DS07-13715-5E 39

• An interrupt can be generated when an active edge is detected on the exter nal signal (ICS01, ICS23 : ICE0

= “1”, ICE1 = “1”, ICE2 = “1”, ICE3 = “1”) .

•8/16-bit PPG timer (8-bit : 6 channels, 16-bit : 3 channels)

The 8/16-bit PPG timer consists of an 8-bit down counter (PCNT) , PPG control registers (PPGC0 to PPGC

5) , PPG cloc k control registers (PCS01, PCS23, PCS45) , and PPG reload registers ( PRLL0 to PRLL5, PRLH0

to PRLH5) .

When used as an 8/16-bit reload timer, the PPG operates as an ev ent timer. The PPG can also be used to output

pulses with specified frequency and duty ratio.

• 8-bit PPG mode

Each channel operates as an independent 8-bit PPG.

• 8-bit prescaler + 8-bit PPG mode

ch0 (ch2, ch4) operates as an 8-bit prescaler and ch1 (ch3, ch5) operat es as a variable frequency PPG by

counting up on the borrow output from ch0 (ch2, ch4) .

• 16-bit PPG mode

ch0 (ch2, ch4) and ch1 (ch3, ch5) operate together as a 16-bit PPG.

• PPG operation

Outputs pulses with the specifie d frequency and duty ratio (ratio of “H” level period and “L” level period), and

can also be used as a D/A converter when combined with an external circuit.

•Waveform generator

The w av ef orm gener ator consists of an 8-bit timer, 8- bit timer contro l registers (DTCR0 to DTCR2) , 8-bit re load

registers (TMRR0 to TMRR2) , and waveform control register (SIGCR) .

The waveform generator can generate a DC chopper output or non-overlapping three-phas e wavefor m output

for inverter control using the realtime outputs (RT0 to RT5) and 8/16-bit PPG timer.

• A non-o verlapping w av ef orm can be gener ated b y using the 8-bit timer as a deadtime timer and adding a non-

overlap time delay to the PPG timer pulse output. (Deadtime timer function)

• A non-o verlapping w av ef orm can be gener ated b y using the 8-bit timer as a deadtime timer and adding a non-

overlap time delay to the realtime outputs (RT1, RT3, RT5) . (Deadtime timer function)

• A GATE signal can be generated when a match occurs between the count fr om the 16-bit freerun timer and

compare registe r in the out put compare (OCCP0 to O CCP5) (rising edge on rea ltime out put (RT) ) to contro l

the PPG timer operation. (GATE function)

• Can control the RTO0 to RTO5 pin outputs using the DTTI pin input.

By making the DTTI pin input clockless, the pins can be controlled externally even when the oscillation clock

is halted. (The lev el for each pin can be set by the program.) However , the I /O po rts (P30 to P35) must have

been set beforehand as outputs and the output values set in the port 3 data register (PDR3) .

MB90560/565 Series

40 DS07-13715-5E

•Block diagram

•16-bit freerun timer, input capture, and output compare

IVF

8IVFE STOP MODE SCLR CLK2 CLK1 CLK0

ICLR

IOP1 IOP0 IOE1 IOE0

ICP0 ICP1 ICE0 ICE1

EG11 EG10 EG01 EG00

IN0/2

IN1/3

CMOD

ICRE

MS13 to 0

Internal data bus

To interrupt

#31 (1FH) *

Divider

Clock

16-bit freerun timer

16-bit compare clear register Compare circuit

Compare registers 0, 2, 4

Compare circuit

Compare registers 1, 3, 5

Compare circuit

To interrupt

#34 (22H) *

To A/D trigger

To RT0, 2, 4

waveform generator

To RT1, 3, 5

waveform generator

To interrupts

Capture registers 0, 2 Edge detection

Capture registers 1, 3 Edge detection

To interrupts

#13 (0DH) *, #17 (11H) *,

#21 (15H) *

#15 (0FH) *, #19 (13H) *,

#23 (17H) *

#33 (21H) *, #35 (23H) *

* : Interrupt number

φ : Machine clock frequency

MB90560/565 Series

DS07-13715-5E 41

•Block diagram of 8/16-bit PPG timer

PC02 PC01

PCNT0

PC00 POS0 OEN0 SST0 POE0 PUF0 PIE0

PC12 PC11 PC10 POS1 OEN1 SST1 POE1 PUF1 PIE1

GATE0/1

GATE1

PRLL0/2/4

PRLH0/2/4

PRLBH0/2/4

PRLL1/3/5

PRLH1/3/5

PRLBH1/3/5

Internal data bus

To interrupt

#14 (0EH) *

Selector Divider Operation

control

Operation

control

(Down counter) Selector Selector To PPG0, 2, 4

Reload ch1, 3, 5 borrow

L/H selector

To interrupt

#16 (10H) *

ch0, 2, 4 borrow

Selector Divider

(Down counter) Selector Selector To PPG1, 3, 5

Reload

L/H selector

PCNT1

* : Interrupt number

φ : Machine clock frequency

MB90560/565 Series

42 DS07-13715-5E

•Block diagram of waveform generator

φDCK2 DCK1 DCK0 TMD1 TMD0 NRSL DTIL DTIE

DTTI

TO0

TO1

RTO0/U

RTO1/X

RTO2/V

RTO3/Y

RTO4/W

RTO5/Z

TO2

TO3

TO4

TO5

RT4

RT5

RT2

RT3

RT0

RT1

Internal data bus

Divider

Clock

DTTI control circuit

To GATE0, 1 (To PPG timer)

Waveform

generator

8-bit timer Compare circuit Selector Selector

8-bit timer register 0 Deadtime generation

To GATE2, 3 (To PPG timer)

Waveform

generator

Waveform

generator

8-bit timer Compare circuit Selector Selector

8-bit timer register 1 Deadtime generation

To GATE4, 5 (To PPG timer)

8-bit timer Compare circuit Selector Selector

8-bit timer register 2 Deadtime generation

φ : Machine clock frequency

MB90560/565 Series

DS07-13715-5E 43

6. UART

(1) Overview

• The UART is a general-purpose serial communications interface f or performing synchronous or asynchronous

(start-stop synchronization) communications with external devices.

• The interface provides both a bi-directional communication function (normal mode) and a master-slave com-

munication function (multi-processor mode) .

• The U ART can generate interrupt requests at receiv e complete, receiv e error detected, and transmit complete

timings. Also the UART supports EI2OS.

•UART functions

The U AR T is a general-p urpose serial communications int erface f or send ing serial data t o and from other CPUs

and peripheral devices.

Note : The UART does not add th e start and stop bits in clock synchronous mode. In this case, only data is

transmitted.

Function

Data buffer Full-duplex double-buffered

Transmission modes • Clock synchronous (no start and stop bits)

• Clock asynchronous (start-stop synchronization)

Baud rate

• Max. 2 MHz (for a 16 MHz machine clock)

• Baud rate generated by dedicated baud rate generator

• Baud rate gener ated b y ext ernal cloc k (clock input fr om SCK0 and SCK1 pins)

• Baud rate generated by internal clock (clock supplied from 16-bit reload timer)

• Eight different baud rate settings are available.

Number of data bits • 7 bits (asynchronous normal mode only)

• 8 bits

Signal format Non return to zero (NRZ) format

Receive error detection • Framing errors

• Overrun errors

• Parity errors (not available in multi-processor mode)

Interrupt requests • Receive interrupt (Receive complete or receive error detected)

• Transmit interrupt (Transmission complete)

• Both transmit and receiv e support the extended intelligent I/O service (EI2OS) .

Master/slave

communication function

(multi-pro cessor mode)

Used for 1 (master) to n (slave) communications.

(Can only be used as m ast er )

MB90560/565 Series

44 DS07-13715-5E

•UART operation modes

⎯ : Not available

*1 : The “+1” represents the address/data (A/D) bit used for communication control.

*2 : Only 1 stop bit supported for receiving.

•UART interrupts and EI2OS

: The UART has a function to halt EI2OS if a receive error is detected.

: Available when the interrupt shared with ICR13 or ICR14 is not used.

Operation Mode No. of Data Bits Synchronization No. of Stop Bits

No Pa rity Wit h Pa rity

0 Normal mode 7 or 8 bits Asynchronous 1 or 2 bits*2

1 Multi-processo r m od e 8 + 1*1 ⎯Asynchronous

2 Clock synchronous mode 8 ⎯Synchronous None

Interrupt Interrupt

No.

Interrupt Control

Name Address Lower Upper Bank

UART1

receive interrupt #37 (25H) ICR13 0000BDHFFFF68HFFFF69HFFFF6AH

UART1

send interrupt #38 (26H) ICR13 0000BDHFFFF64HFFFF65HFFFF66H

UART0

receive interrupt #39 (27H) ICR14 0000BEHFFFF60HFFFF61HFFFF62H

UART0

send interrupt #40 (28H) ICR14 0000BEHFFFF5CHFFFF5DHFFFF5EH

MB90560/565 Series

DS07-13715-5E 45

(2) UART structure

The UART consists of the following 11 blocks:

•Block diagram

• Clock selector • Mode registers (SMR0, SMR1)

• Receive control circuit • Control registers (SCR0, SCR1)

• Transmission control circuit • Status registers (SSR0, SSR1)

• Receive status evaluation circuit • Input data registers (SIDR0, SIDR1)

• Receive shift register • Output data register s (SODR0, SODR1)

• Transmission shift register

MD1

MD0

CS2

CS1

CS0

SCKE

SOE

PEN

SBL

A/D

REC

RXE

TXE

ORE

FRE

RDRF

TDRE

BDS

RIE

TIE

SIDR0/SIDR1

P40/SCK0

P37/SOT0

#39 (27H)*

<#37 (25H)*>

#40 (28H)*

<#38 (26H)*>

P36/SIN0

SODR0/SODR1

Control bus

Dedicated baud

rate generator

16-bit reload timer

Clock

selector Receive

clock Receive

control circuit

Start bit

detection circuit Transmission

start circuit

Transmit bit

counter

Receive parity

counter Transmit parity

counter

Receive

shift register

Receive bit

counter

Receive

complete

Receive status

evaluation circuit

Internal data bus

Transmit clock

Receive

interrupt signal

Transmit

interrupt signal

Transmission

control circuit

Transmission

shift register

Transmission start

Receive error detection

signal for EI2OS

(to CPU)

SMR0/SMR1 SCR0/SCR1 SSR0/SSR1

* : Interrupt number

MB90560/565 Series

46 DS07-13715-5E

•Clock selector

Selects the send/receive clock from either the dedicated baud rate generator, exter nal input clock (clock input

to SCK0 or SCK1 pin) , or internal clock (clock supplied by 16-bit reload timer) .

•Receive control circuit

The receive control circuit consists of a receiv e bit counter, start bit detection circuit, and receive parity counter .

The receiv e bi t counter counts th e receiv ed data bits an d outputs a re ceiv e int errupt request wh en the requir ed

number of data bits have been received. The star t bit detection circuit detects the star t bit on the serial input

signal. On detecting a start bit, the receive data is shifted to the input data register (SIDR0 or SIDR1) in

accordance with the specified transfer speed. The receive parity counter calculates the parity of the received

data if parity is selected.

•Transmission control circuit

The transmission control circuit consists of a transmission bit counter , transmission start circuit, and transmission

parity counter. The transmission bit counter counts the transmitted data bits and outputs a transmit interrupt

request when the required number of data bits hav e been sent. The transmission start circuit starts transmission

when data is written to the o utput data register (SODR0 or SODR1) . The transmission parity counter gener ates

the parity bit for the transmitted data when parity is selected.

•Receive shif t re g is te r

The receive shift register captures the data input from the SIN0 or SIN1 pin by shifting one bit at a time then

transfers the received data to the input data register (SIDR0 or SIDR1) when reception comple tes.

•Transmission shift register

The transm ission data is tr ansferred from th e output dat a register (SODR0 o r SODR1) to the tr ansmission shif t

•Mode register (SMR0, SMR1)

Set the operation mode, baud rate clock and serial clock input/output control, and enables output for the

serial da ta pi n.

•Control register (SCR0, SCR1)

Specifies whether to use par ity, the type of parity, number of stop bits and data bits and the frame data format

for operation mode 1, to clear the receive er ror flag bit, and to enab le or disable send and receive operation.

•Status register (SSR0, SSR1)

Stores the send/receive and error status information, set the serial data transfer direction, and enables or disables

the send and receive interrupt requests.

•Input data register (SIDR0, SIDR1)

Stores the received data.

•Output data register (SODR0, SODR1)

Set the transmission data. The data set in the output data register is converted to serial format and output.

MB90560/565 Series

DS07-13715-5E 47

7. DTP/External Interrupt Circuit

(1) Overview of the DTP/external interrupt circuit

The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input to the external

interrupt input pins (INT7 to INT0) and outputs interrupt requests.

•DTP/external interrupt circuit functions

The DTP/e xte rnal interrupt function detects edge or level signals inpu t to the e x ternal interrupt input pins (INT7

to INT0) and outp uts interrupt requests.

The interrupt request is received by the CPU and, if the extended intelligent I/O service (EI2OS) is enabled,

EI2OS perfor ms automatic data transfer (DTP function) then passes control to the interrupt handler routine on

completion. If EI2OS is disabled, control passes directly to the interrupt handler routine without performing

automatic data transfer (DTP funct ion) .

•Overview of the DTP/external interrupt circuit

•DTP/external interrupt circuit interrupts and EI2OS

: Available when the interrupt shared with ICR07 or ICR08 is not used.

Channel Interrupt

No. Interrupt Control Register Vector Table Addres s EI2OS

INT0/INT1 #25 (19H) ICR07 0000B7HFFFF98HFFFF99HFFFF9AH

INT2/INT3 #26 (1A H) FFFF94HFFFF95HFFFF96H

INT4/INT5 #27 (1B H) ICR08 0000B8HFFFF90HFFFF91HFFFF92H

INT6/INT7 #28 (1CH) FFFF8CHFFFF8DHFFFF8EH

ICR : Interrupt control register

External Interrupt DTP Function

Input pins 8 channels (P10/INT0 to P16/INT6, P63/INT7)

Interrupt co nd itio ns The level or edge to dete ct can be set independent ly for each pin in the de tection lev-

el setup register (ELVR) .

“L” level, “H” level, rising edge, or falling edge input

Interrupt nu m be r #25 (19H) to #28 (1CH)

Interrupt co nt ro l Interrupts can be enabled or disabled in the DTP/external interrupt enable register

(ENIR) .

Interrupt flag The DTP/external interrupt request register (ENRR) stores interrupt requests.

Processing selection Set EI2OS to disabled (ICR : ISE = 0) Set EI2OS to enabled (ICR : ISE = 1)

Operation Jumps to interrupt handler routine Jumps to interrupt handler routine after

automatic data transfer by EI2OS com-

pletes.

MB90560/565 Series

48 DS07-13715-5E

(2) Structure of the DTP/external interrupt circuit

The DTP/external int errupt circuit co ns ists of the following four blocks :

• DTP/interrupt detection circuit

• DTP/interrupt request register (EIRR)

• DTP/interrupt enable register (ENIR)

• Request level setting register (ELVR)

•Block diagram

LB7

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

P63/INT7 P10/INT0

LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

P16/INT6 P11/INT1

P12/INT2

P13/INT3

P15/INT5

P14/INT4

#25 (19H)*

#26 (1AH)*

#27 (1BH)*

#28 (1CH)*

22222222

Internal data bus

Request level setting register (ELVR)

Selector

Selector Selector

Selector

Selector Selector

DTP/external interrupt input detection circuit

DTP/interrupt

request register

(EIRR)

DTP/interrupt

enable register

(ENIR)

Interrupt request signal

* : Interrupt number

MB90560/565 Series

DS07-13715-5E 49

8. Delayed Interrupt Generation Module

• The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this

hardware interrupt can be specifie d by software.

•Delayed interrupt generation module functions

•Block diagram

Function and Control

Interrupt trigger

• Writing “1” to bit R0 of the delayed interrupt request generation/clear register

(DIRR : R0 = 1) generates an interrupt request.

• Writing “0” to bit R0 of the delayed interrupt request generation/clear register

(DIRR : R0 = 1) clears the inter rupt request.

Interrupt con tr ol • No enable/disable register is pro vided for this interrupt.

Interrupt flag • Set in bit R0 of the delayed interrupt request generation/clear register

(DIRR : R0) .

EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .

⎯⎯⎯⎯⎯⎯⎯R0

Internal data bus

Delayed interrupt request generation/

clear register (DIRR)

RInterrupt

request signal

Interrupt request

latch

⎯ : Undefined

MB90560/565 Series

50 DS07-13715-5E

9. 8/10-Bit A/D Converter

•Overview of the 8/10-bit A/D converter

• The 8/10-bit A/D co nverter uses RC successive a ppr oximation to convert analog input voltages to an 8-bit or

10-bit digital value.

• The input signals can be selected from the eight an alog input pin channels.

•8/10-bit A/D converter functions

•8/10-bit A/D converter con version modes

•8/10-bit A/D converter interrupts and EI2OS

: Available

A/D conversion time The minimum conversion time is 6.13 µs (for a 16 MHz machine clock, including samplin g

time) .

The minimum sampling time is 2.0 µs (for a 16 MHz machine clock)

Conversion method RC successive approximation with sample & hold circuit

Resolution 8-bit or 10-bit, selectable

Analog input pins Eight analog input pin channels are available. The input pin can be selected by the program.

Interrupts An interrupt request can be genera ted and EI2OS invoked when A/D conversion completes.

The conversion data protection function operates when A/D conversion is performed with

the interrupt enabled.

A/D conversion

start trigger The conversion start trigger can be set from the following options : software, output of 16-

bit reload ti mer 1 (rising edg e) , or zero detection edge from 16-bit freerun timer.

EI2OS support Supported by the extended intelligent I/O service (EI2OS) .

Conversion Mode Single Conversion Mode Operation Scan Conversion Mode Operation

Single-shot conversion mode 1

Single-shot conversion mode 2 Performs one conversion for the spec-

ified channel (1 channel) then halts.

Sequentially performs one conversion

for multiple channels (up to 8 channels

can be set) , then halts.

Continuous conversion mode Performs repeated conversions for the

specified channel (1 channel) .

Performs repe ated conversions for the

specified channels (up to 8 channels

can be set) .

Incremental conversion mode Performs one conversion for the spec-

ified channel (1 channel) then halts

and waits for the next activation.

Sequentially performs one conversion

for multiple channels (up to 8 channels

can be set) , then halts and waits for

the next activatio n.

Interrupt No. Interrupt Control Register Vector Table Address EI2OS

#11 (0BH) ICR00 0000B0HFFFFD0HFFFFD1HFFFFD2H

MB90560/565 Series

DS07-13715-5E 51

•Block diagram

BUSY INT INTE PAUS STS1 STS0 STRT Rese-

rved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

S10 ST1 ST0 CT1 CT0 D9 D7 D6 D4 D3 D2 D1 D0

P57/AN7

P56/AN6

P55/AN5

P54/AN4

P53/AN3

P52/AN2

P51/AN1

P50/AN0 AVR

AVCC

AVSS

D8 D5

⎯

A/D control status register

(ADCS0, ADCS1)

A/D data register

(ADCR0, ADCS1)

Interrupt request signal #11 (0BH) *

16-bit reload timer 1 output

16-bit freerun timer zero-detect Clock selector Decoder

Internal data bus

Analog

channel

selector

Sample &

hold circuit

Comparator

Control circuit

D/A converter

φ : Machine clock

* : Interrupt number

MB90560/565 Series

52 DS07-13715-5E

10. ROM Mirror Function Selection Module

• The ROM mirror function selection module enables ROM data in FF bank to be read by accessing 00 bank.

•ROM mirror function selection module functions

•Relationship between addresses in the ROM mirror function

•Block diagram

Function

Mirror setting address • Data in FFFFFFH to FF4000H in FF bank can be read from 00FFFFH to 004000H

in 00 bank.

Interrupts • None

EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .

FE0000

FE8000

FF8000

FF0000

FF4000

FEFFFF

FFFFFF

FF bank

Mirrored ROM

data area

ROM area in MB90568 and MB90F568

ROM area in MB90567

ROM area in MB90562A and MB90F562B

ROM area in MB90561A

⎯⎯⎯⎯⎯⎯⎯MI

ROM

ROM mirror function selection register (ROMM)

Internal data bus

FF bank

Address

Data

00 bank

Address space

MB90560/565 Series

DS07-13715-5E 53

11. Low Power Consumption (Standby) Modes

• The pow er consumption of F2MC-16LX devices can be redu ced by various settings th at contr ol the oper ating

cloc k selection.

•Functions of each CPU operation mode

CPU Operation

Clock Operation

Mode Function

PLL clock

Normal Run The CPU and peripheral functions operate using the oscillation clock (HCLK)

multiplied by the PLL circuit.

Sleep The peripheral functions only operate using the oscillation clock (HCLK) mul-

tiplied by the PLL circu it.

Pseudo-clock The timebase timer only operates using the oscillation clock (HCLK) multi-

plied by the PLL circuit.

Stop The oscillation clock is stopped and the CPU and peripherals halt operation.

Main clock

Normal Run The CPU and peripheral functions operate using the oscillation clock (HCLK)

divided into 2.

Sleep The peripheral functions only operate using the oscillation clock (HCLK) di-

vided into 2.

Stop The oscillation clock is stopped and the CPU and peripherals halt operation.

CPU intermittent

operation Normal Run The oscillation clock (HCLK) divided into 2 operates intermittently for fixed

time intervals.

MB90560/565 Series

54 DS07-13715-5E

12. 512 Kbit Flash Memory

• This section describes the flash memory on the MB90F562B and does not apply to e valuation and mask ROM

versions.

• The flash memory is located in bank FF in the CPU memory map.

•Flash memory functions

•Sector configuration of flash memory

Function

Memory size • 512 Kbit (64 KBytes)

Memory configuration • 64 KWords × 8 bits or 32 KWords × 16 bits

Sector configuration • 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes

Sector protect function • Selectable for each sector

Programming algorithm • A utomatic programming alg orithm (Embedded Algorithm : Equivalent to

MBM29F400TA)

Operation command s

• Compatible with JEDEC standard comm ands

• Includes an era se pause and restart function

• Write/erase completion detection by data polling or toggle bit

• Erasing by sector available (sectors can be combined in any combination)

No. of write/ erase cycles • Min. 10,000 guaranteed

Memory write/ er ase method

• Can be written and erased using a parallel writer

(Ando Denki AF9704, AF9705, AF9706, AF9708, and AF9709)

• Can be written and erased using a ded icated serial writer

(Yokogawa Digital Computer Corporation AF200, AF210, AF120, and AF110)

• Can be written and erased by the program

Interrupts • Write and erase completio n int er rupts

EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .

SA1 (32 Kbyte)

SA2 (8 Kbyte)

SA3 (8 Kbyte)

SA4 (16 Kbyte)

FF0000

FF7FFF

FF8000

FF9FFF

FFA000

FFBFFF

FFC000

FEFFFF

70000

77FFF

78000

79FFF

7A000

7BFFF

7C000

7FFFF

Flash memory CPU address Writer address

* : The writer add ress is the address to be used inst ead of the CPU address when writing d ata from a parallel

flash memory writer. Use the writer address when programming or erasing with a general-purpose parallel

writer.

MB90560/565 Series

DS07-13715-5E 55

13. 1 Mbit Flash Memory

• This section describes the flash memory on the MB90F568 and does not apply to e valuation and mask R OM

versions.

• The flash memory is located in banks FE to FF in the CPU memory map.

•Flash memory functions

•Sector configuration of flash memory

Function

Memory size • 1 Mbit (128 KBytes)

Memory configuration • 128 KWords × 8 bits or 64 KWords × 16 bits

Sector configuration • 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes + 64 KBytes

Sector protect function • Selectable for each sector

Programming algorithm • A utomatic programming alg orithm (Embedded Algorithm : Equivalent to

MBM29F400TA)

Operation command s

• Compatible with JEDEC standard comm ands

• Includes an era se pause and restart function

• Write/erase completion detection by data polling or toggle bit

• Erasing by sector available (sectors can be combined in any combination)

No. of write/ erase cycles • Min. 10,000 guaranteed

Memory write/ er ase method • Can be written and erased using a parallel writer

• Can be written and erased using a ded icated serial writer

• Can be written and erased by the program

Interrupts • Write and erase completio n int er rupts

EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .

SA0 (64 Kbyte)

SA1 (32 Kbyte)

SA2 (8 Kbyte)

SA3 (8 Kbyte)

SA4 (16 Kbyte)

FE0000

FEFFF

FF0000

FF7FFF

FF8000

FF9FFF

FFA000

FFBFFF

FFC000

FEFFFF

60000

6FFFF

70000

77FFF

78000

79FFF

7A000

7BFFF

7C000

7FFFF

Flash memory CPU address Writer address

* : Th e writer address is the address to be used in stead of the CPU addr ess when writing data from a para llel

flash memory writer. Use the writer address when progr amming or er asing with a gener al-purpose para llel

writer.

MB90560/565 Series

56 DS07-13715-5E

■ELECTRICAL CHARACTERISTICS (MB90560 SERIES)

1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V)

*1 : AVCC and AVR must not exceed VCC. Also, AVR must not exceed AVCC.

*2 : VI and VO must not exceed VCC + 0. 3 V.

*3 : The maximum output current is the peak value for a single pin.

*4 : Pins other than P30/RTO0 to P35/RTO5

*5 : P30/RTO0 to P35/RTO5 pins

WARNING: Semiconductor devices can be permanently damaged b y application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Rating Unit Remarks

Min. Max.

Power supply voltage

VCC VSS − 0.3 VSS + 6.0 V

AVCC VSS − 0.3 VSS + 6.0 V VCC ≥ AVCC*1

AVR VSS − 0.3 VSS + 6.0 V AVCC ≥ AVR ≥ 0 V *1

Input voltage VIVSS − 0.3 VSS + 6.0 V *2

Output voltage VOVSS − 0.3 VSS + 6.0 V *2

“L” level maximum output

current IOL1 ⎯15 mA *3, *4

IOL2 ⎯20 mA *3, *5

“L” level average output

current

IOLAV1 ⎯4mA

Average value

(operating current × operating ratio) *4

IOLAV2 ⎯12 mA Average value

(operating current × operating ratio) *5

“L” level total maximum

output current ΣIOL ⎯100 mA

“L” level total average

output current ΣIOLAV ⎯50 mA Average value

(operating current × operating ratio)

“H” level maximum output

current IOH ⎯−15 mA *3

“H” level average output

current IOHAV ⎯−4mA

Average value

(operating current × operating ratio)

“H” level total maximum

output current ΣIOH ⎯−100 mA

“H” level total average

output current ΣIOHAV ⎯−50 mA Average value

(operating current × operating ratio)

Power consumption Pd ⎯300 mW

Operating temperature TA−40 +85 °C

Storage temperature Tstg −55 +150 °C

MB90560/565 Series

DS07-13715-5E 57

2. Recommended Operating Conditions (VSS = AVSS = 0.0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconducto r device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data shee t. Users consider ing application outside th e listed cond itions are advised t o contact

their representatives beforehand.

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VCC 3.0 5.5 V Normal operation (MB90562A, MB90561A,

and MB90V560)

4.5 5.5 V Normal operation (MB90F562B)

VCC 3.0 5.5 V Maintaining state in stop mode

Input “H” voltage

VIH 0.7 VCC VCC + 0.3 V CMOS input pin

VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin

VIHM VCC − 0.3 VCC + 0.3 V MD input pin

Input “L” voltag e

VIL VSS − 0.3 0.3 VCC V CMOS input pin

VILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin

VILM VSS − 0.3 VSS + 0.3 V MD input pin

Smoothing capacitor CS0.1 1.0 µF

Use a ceramic capacitor or other capacitor

with equivalent frequency characteristics.

The capacitance of the smoothing capacitor

connected to the VCC pin must be greater

than CS.

Operating

temperature TA−40 +85 °C

• C pin diagram

MB90560/565 Series

58 DS07-13715-5E

3. DC Characteristics (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

* : Value when low power mode bits (LPM0, 1) is set to “01” with an internal operating frequency of 4 MHz.

Note : Current values are provisional and are su bje ct to chang e with o ut no tic e to allow for improvement s to th e

characteristics. The power supply current is measured with an external clock.

Parameter Sym-

bol Pin Name Condition Value Unit Remarks

Min. Typ. Max.

Output “H”

voltage VOH All output

pins VCC = 4.5 V

IOH = −2.0 mA VCC − 0.5 ⎯⎯V

Output “L”

voltage

VOL1

Pins other

than P30/

RTO0 to

P35/RTO5

VCC = 4.5 V

IOL1 = 2.0 mA ⎯⎯0.4 V

VOL2 P30/RTO0

to P35/

RTO5

VCC = 4.5 V

IOL2 = 12.0 mA ⎯⎯0.8 V

Input leak

current IIL All output

pins VCC = 5.5 V

VSS < VI < VCC −5⎯5µA

Power supply

current*

ICC

VCC

For VCC = 5 V,

internal frequency = 16 MHz,

normal oper a tion

⎯50 80 mA MB90562A,

MB90561A

⎯40 50 mA MB90F562B

For VCC = 5 V,

internal frequency = 16 MHz,

A/D operation in progress

⎯55 85 mA MB90562A,

MB90561A

⎯45 55 mA MB90F562B

Flash write or erase ⎯45 60 mA MB90F562B

ICCS For VCC = 5 V,

internal frequency = 16 MHz,

sleep mod e ⎯15 20 mA MB90562A,

MB90561A,

MB90F562B*

ICCH Stop mode, TA = 25 °C⎯520µA

Input

capacitance CIN

Other than

AVCC,

AVSS, C,

VCC, and

VSS

⎯⎯10 80 pF

Pull-up

resistor RUP P00 to P07

P10 to P17

RST ⎯15 30 100 kΩ

Pull-down

resistor RDOWN MD2 ⎯15 30 100 kΩOnly for mask

ROM products

MB90560/565 Series

DS07-13715-5E 59

4. AC Characteristics

(1) Clock Timings (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Parameter Sym

bol Pin Name Condi-

tion Value Unit Remarks

Min. Typ. Max.

Clock frequency fCX0, X1

⎯

3⎯16 MHz With a PLL circuit

1⎯16 Without a PLL circuit

Clock cycle time tHCYL X0, X1 62.5 ⎯333 ns With a PLL circuit

62.5 ⎯1000 Without a PLL circuit

Input clock pulse width PWH

PWL X0 10 ⎯⎯ns Recommended duty

ratio = 30% to 70%

Input clock rise/fall time tcr

tcf X0 ⎯⎯ 5ns

When using an

external clock

Internal oper at ing cl oc k

frequency fCP ⎯1.5 ⎯16 MHz When using a main

clock

Internal oper at ing cl oc k

cycle time tCP ⎯62.5 ⎯333 ns When using a main

clock

0.8 VCC

0.2 VCC

tcf tcr

tHCYL

PWH PWL

•X0 and X1 clock timing

MB90560/565 Series

60 DS07-13715-5E

The AC ratings are specified for the following measurement reference voltages.

•PLL guaranteed operation range

Relationship be tw ee n internal operating clock fr eq ue n cy an d po we r su pp ly volt ag e

Relationship between oscillation frequency and internal operating clock frequency

5.5

4.5

3.3

3.0

13812 16

Guaranteed operation range

for MB90F562B PLL guaranteed operation range

PLL guaranteed

operation range

A/D converter guaranteed

operation range

Guaranteed operation range

for MB90561A and MB90562A

Guaranteed operation range for MB90V560

Supply V oltage V

(V)

Internal Clock f

(MHz)?

1234 6 8 12 16

×4×3×2×1

No multiplier

Internal Clock f

(MHz)

Source Oscillation Clock f

(MHz)

0.5

0.8 VCC

0.2 VCC

2.4 V

0.8 V

0.7 VCC

0.3 VCC

•Input signal waveform

Hysteresis input pin

Pins other than hysteresis input or MD input pins

•Output signal wavef orm

Output pin

MB90560/565 Series

DS07-13715-5E 61

(2)Reset (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

*: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to se veral

dozen ms; for a ceramic oscillator, this is several hundred µs to a f ew ms, and fo r an external clock this is 0 ms.

Parameter Symbol Pin Name Condition Value Unit Remarks

Min. Max.

Reset input time tRSTH RST ⎯

16 tCP ⎯ns In normal

operation

Oscillator oscillation

time* + 16 tCP ⎯ms In stop mode

RST

0.2 VCC

tRSTL

0.2 VCC

• In normal operation

RST

16 tcp

tRSTL

0.2Vcc 0.2Vcc

Internal

operation

clock

Internal

reset

90 % of

amplitude

Oscillator

oscillation time

Oscillator stabilization wait time

Execution of the instruction

• In stop mode

MB90560/565 Series

62 DS07-13715-5E

(3) Power-On Reset (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Note: VCC must be less than 0.2 V before power-on.

Notes : • The above rating values are fo r generating a po wer-on reset.

• Some internal registers are only initialized by a power-on reset. Always apply the power supply in

accordance with the abo ve ratings if you wish to initialize these registers.

Parameter Symbol Pin Name Condi-

tion Value Unit Remarks

Min. Max.

Power supply rise time tRVCC ⎯0.05 30 ms

Power supply cu to ff tim e tOFF VCC 4⎯ms For repeated operation

VCC

3.0 V

VSS

0.2 V0.2 V

2.7 V

tOFF

0.2 V

Maintain RAM data

Recommended rate of voltage

rise is 50 mV/ms or less.

Sudden changes in the power supply voltage may cause a power-on reset.

The recommended practice if you wish to change the power supply voltage while the device is

operating is to raise the voltage smoothly as shown below . Also, changes to t he supply volta ge

should be perfor med when th e PLL clock is not in use. Th e PLL clock may b e used, however, if

the rate of voltage change is 1 V/s or less.

MB90560/565 Series

DS07-13715-5E 63

(4) UART0, UART1, and I/O Expansion Serial Timings

(TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Notes : • These are the A C ratings for CLK synchronous mode.

• CL is the load capacitor connected to the pin for testing.

• tCP is the machine cycle period (unit = ns)

Parameter Symbol Pin Name Condition Value Unit Remarks

Min. Max.

Serial clock cycle time tSCYC SCK0, SCK1

Internal shift clock

mode, output pin load is

CL = 80 pF + 1 TTL

8 tCP ⎯ns

SCK ↓ → SOT delay

time tSLOV SCK0, SCK1

SOT0, SOT1 −80 80 ns

Valid SIN → SCK ↑tIVSH SCK0, SCK1

SIN0, SIN1 100 ⎯ns

SCK ↑ → valid

SIN hold time tSHIX SCK0, SCK1

SIN0, SIN1 60 ⎯ns

Serial clock “H” pulse

width tSHSL SCK0, SCK1

External shift clock

mode, output pin load is

CL = 80 pF + 1 TTL

4 tCP ⎯ns

Serial clock “L” pulse

width tSLSH SCK0, SCK1 4 tCP ⎯ns

SCK ↓ → SOT delay

time tSLOV SCK0, SCK1

SOT0, SOT1 ⎯150 ns

Valid SIN → SCK ↑tIVSH SCK0, SCK1

SIN0, SIN1 60 ⎯ns

SCK ↑ → valid

SIN hold time tSHIX SCK0, SCK1

SIN0, SIN1 60 ⎯ns

MB90560/565 Series

64 DS07-13715-5E

•Internal shift clock mode

•External shift clock mode

SCK

SOT

SIN

tSCYC

tSLOV

tIVSH tSHIX

0.8 V 0.8 V

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SCK

SOT

SIN

tSLSH tSHSL

tSLOV

tIVSH tSHIX

0.2 VCC 0.2 VCC

0.8 VCC 0.8 VCC

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

MB90560/565 Series

DS07-13715-5E 65

(5) Timer Input Timings (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

(6) Timer Output Timings (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0. 0 V)

(7) Trigger Input Timings (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0. 0 V)

Parameter Symbol Pin Name Condi-

tion Value Unit Remarks

Min. Max.

Input pulse width tTIWH, tTIWL FRCK, IN0, IN1, TIN0, TIN1 ⎯4 tCP ⎯ns

Parameter Symbol Pin Name Condi-

tion Value Unit Remarks

Min. Max.

CLK ↑ → TOUT change time tTO RTO0 to RTO5,

PPG0 to PPG5, TO0 to TO1 ⎯30 ⎯ns

Parameter Symbol Pin Name Condition Value Unit Remarks

Min. Max.

Input pulse width tTRGL INT0 to INT7, IN0 to IN3 ⎯5 tCP ⎯ns In normal

operation

1⎯µs In stop mode

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tTIWH tTIWL

CLK

TOUT

2.4 V

0.8 V

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tTRGH tTRGL

MB90560/565 Series

66 DS07-13715-5E

5. Electrical Characteristics for the A/D Converter

(TA = −40 °C to +85 °C, 3.0 V ≤ AVR, VCC = AVCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

* : Current when A/D converter is not used and CPU is in stop mode (VCC = AVCC = AVR = 5.0 V)

Notes : • The L reference voltage is fixed to AVSS. The relative error increases as AVR becomes smaller.

• Ensure that the output impedance of the e xternal circuit connected to the analog input meets the f ollowing

condition :

Output impedance of external circuit ≤ 10 kΩ (Sampling Time = 4.0 µs)

• If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short.

Parameter Symbol Pin Name Value Unit Remarks

Min. Typ. Max.

Resolution ⎯⎯ ⎯10 ⎯bit

Total error ⎯⎯ ⎯⎯±5.0 LSB

Non-linearity error ⎯⎯ ⎯⎯±2.5 LSB

Differential linearity error ⎯⎯ ⎯⎯±1.9 LSB

Zero transition voltage VOT AN0 to AN7 AVSS

−3.5 LSB AVSS

+0.5 LSB AVSS

+4.5 LSB V1 LSB = (AVR−AVSS)/

1024

Full-scale transition

voltage VFST AN0 to AN7 AVR

−6.5 LSB AVR

−1.5 LSB AVR

+1.5 LSB V

Conversion time ⎯⎯ ⎯176 tCP ⎯ns

Sampling time ⎯⎯ ⎯64 tCP ⎯ns

Analog port input

current IAIN AN0 to AN7 ⎯⎯10 µA

Analog input voltage VAIN AN0 to AN7 0 ⎯AVR V

Reference voltage ⎯AVR 2.7 ⎯AVCC V

Power supply current IAAVCC ⎯5⎯mA

IAH AVCC ⎯⎯ 5µA*

Reference voltage

supply current IRAVR ⎯400 ⎯µA

IRH AVR ⎯⎯ 5µA*

Variation between

channels ⎯AN0 to AN7 ⎯⎯ 4LSB

• Equivalent circuit of analog input circuit

CRON

Analog input

Comparator

MB90561A, MB90562A

RON = 2.2 kΩ approx.

C = 45 pF approx.

MB90F562B

RON = 2.6 kΩ approx.

C = 28 pF approx.

Note : The values listed are an indication only.

MB90560/565 Series

DS07-13715-5E 67

6. Flash Memory Erase and Programming Performance

Parameter Condition Value Units Remarks

Min Typ Max

Sector erase tim e

TA = + 25 °C

Vcc = 5.0 V

⎯115s

Excludes 00H programming prior

erasure

Chip erase time ⎯5⎯sExcludes 00H programming prior

erasure

Word (16 bit width)

programming time ⎯16 3,600 µs Excludes system-level overhead

Erase/Program cycle ⎯10,000 ⎯⎯cycle

Data holding time ⎯100,000 ⎯⎯h

MB90560/565 Series

68 DS07-13715-5E

■ELECTRICAL CHARACTERISTICS (MB90565 SERIES)

1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V)

*1 : AVCC and AVR must not exceed VCC. Also, AVR must not exceed AVCC.

*2 : VI and VO must not exceed VCC + 0. 3 V.

*3 : The maximum output current is the peak value for a single pin.

WARNING: Semiconductor devices can be permanently damaged b y application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Rating Unit Remarks

Min. Max.

Power supply voltage

VCC VSS − 0.3 VSS + 4.0 V

AVCC VSS − 0.3 VSS + 4.0 V VCC ≥ AVCC*1

AVR VSS − 0.3 VSS + 4.0 V AVCC ≥ AVR ≥ 0 V *1

Input voltage VIVSS − 0.3 VSS + 4.0 V *2

Output voltage VOVSS − 0.3 VSS + 4.0 V *2

“L” level maximum output

current IOL ⎯15 mA *3

“L” level average output

current IOLAV ⎯4mA

Average value

(operating current × operating ratio)

“L” level total maximum

output current ΣIOL ⎯100 mA

“L” level total average

output current ΣIOLAV ⎯50 mA Average value

(operating current × operating ratio)

“H” level maximum output

current IOH ⎯−15 mA *3

“H” level average output

current IOHAV ⎯−4mA

Average value

(operating current × operating ratio)

“H” level total maximum

output current ΣIOH ⎯−100 mA

“H” level total average

output current ΣIOHAV ⎯−50 mA Average value

(operating current × operating ratio)

Power consumption Pd ⎯300 mW

Operating temperature TA−40 +85 °C

Storage temperature Tstg −55 +150 °C

MB90560/565 Series

DS07-13715-5E 69

2. Recommended Operating Conditions (VSS = AVSS = 0.0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconducto r device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data shee t. Users consider ing application outside th e listed cond itions are advised t o contact

their representatives beforehand.

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VCC

3.0 3.6 V Normal operation (MB90V560)

2.7 3.6 V Normal operation (MB90F568, MB90567

and MB90568)

2.5 3.6 V Maintaining state in stop mode

Input “H” voltage

VIH 0.7 VCC VCC + 0.3 V CMOS input pin

VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin

VIHM VCC − 0.3 VCC + 0.3 V MD input pin

Input “L” voltage

VIL VSS − 0.3 0.3 VCC V CMOS input pin

VILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin

VILM VSS − 0.3 VSS + 0.3 V MD input pin

Operating temperature TA−40 +85 °C

MB90560/565 Series

70 DS07-13715-5E

3. DC Characteristics (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

* : Value when low power mode bits (LPM0, 1) are set to “01” with an internal opera ting frequency of 8 MHz.

(Continued)

Parameter Sym

bol Pin Name Condition Value Unit Remarks

Min. Typ. Max.

Output “H”

voltage VOH All output

pins VCC = 3.0 V

IOH = −2.0 mA VCC − 0.5 VCC − 0.3 ⎯V

Output “L”

voltage VOL All output

pins VCC = 3.0 V

IOL = 2.0 mA ⎯0.2 0.4 V

Input leak

current IIL All output

pins VCC = 3.0 V

VSS < VI < VCC −5−15µA

Power

supply

current*

ICC

VCC

For VCC = 3.3 V,

internal frequency = 8 MHz,

normal operation ⎯14 22 mA MB90567/568

For VCC = 3.3 V,

internal frequency = 16 MHz,

normal operation ⎯27 40 mA MB90567/568

For VCC = 3.3 V,

internal frequency = 8 MHz,

A/D operation in progress ⎯18 27 mA MB90567/568

For VCC = 3.3 V,

internal frequency = 16 MHz,

A/D operation in progress ⎯32 45 mA MB90567/568

For VCC = 3.3 V,

internal frequency = 8 MHz,

normal operation ⎯18 28 mA MB90F568

For VCC = 3.3 V,

internal frequency = 16 MHz,

normal operation ⎯36 45 mA MB90F568

For VCC = 3.3 V,

internal frequency = 8 MHz,

A/D operation in progress ⎯23 33 mA MB90F568

For VCC = 3.3 V,

internal frequency = 16 MHz,

A/D operation in progress ⎯41 50 mA MB90F568

Flash write or era se ⎯40 50 mA MB90F568

ICCS

For VCC = 3.3 V,

internal frequency = 8 MHz,

sleep mode ⎯610mA

MB90567/568

MB90F568*

For VCC = 3.3 V,

internal frequency = 16 MHz,

sleep mode ⎯14 20 mA MB90567/568

MB90F568*

ICCH Stop mode, TA = 25 °C⎯520µA

MB90560/565 Series

DS07-13715-5E 71

(Continued)

Note : Current values are provisional and are su bje ct to chang e with o ut no tic e to allow for improvement s to th e

characteristics. The power supply current is measured with an external clock.

Parameter Sym-

bol Pin Name Condition Value Unit Remarks

Min. Typ. Max.

Pull-up

resistor RUP P00 to P07

P10 to P17

RST ⎯20 65 200 kΩ

Pull-down

resistor RDOWN MD2 ⎯20 65 200 kΩOnly for

mask ROM

products

MB90560/565 Series

72 DS07-13715-5E

4. AC Characteristics

(1) Clock Timings (MB90567/568/F568 : TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

(MB90V560 : TA = +25 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Parameter Sym

bol Pin Name Condi-

tion Value Unit Remarks

Min. Typ. Max.

Clock frequency fCX0, X1

⎯

3⎯12 MHz MB90V560

3⎯16 MHz MB90567/568

MB90F568

Clock cycle time tHCYL X0, X1 83.3 ⎯333 ns MB90V560

62.5 ⎯333 ns MB90567/568

MB90F568

Input clock pulse width PWH

PWL X0 10 ⎯⎯ns Recommended duty

ratio = 30% to 70%

Input clock rise/fall time tcr

tcf X0 ⎯⎯ 5ns

When using an

external clock

Internal oper at ing cl oc k

frequency fCP ⎯

1.5 ⎯12 MHz MB90V560

1.5 ⎯16 MHz MB90567/568

MB90F568

Internal oper at ing cl oc k

cycle time tCP ⎯

83.3 ⎯666 ns MB90V560

62.5 ⎯666 ns MB90567/568

MB90F568

0.8 VCC

0.2 VCC

tcf tcr

tHCYL

PWH PWL

• X0 and X1 clock timing

MB90560/565 Series

DS07-13715-5E 73

The AC ratings are specified for the following measurement reference voltages.

• PLL guaranteed oper ation range

Relationship between internal operating clock frequency and power supply voltage

Relationship between oscillation frequency and internal operating clock frequency

3.6

3.0

2.7

1.5 3 8 12 16

PLL guaranteed operation range

(MB90567/568/F568 : 3.0 V to 3.6 V, fCP =3 MHz to 16 MHz)

(MB90V560 : 3.0 V to 3.6 V, fCP =3 MHz to 12 MHz)

PLL guaranteed

operation range A/D converter

guaranteed

operation rang

Guaranteed operation range for MB90567/568/F568

(3.0 V to 3.6 V, fCP =1.5 MHz to 16 MHz)

(2.7 V to 3.6 V, fCP =1.5 MHz to 8 MHz)

Supply Voltage VCC (V)

Internal Clock fCP (MHz)

Guaranteed operation range

for MB90V560

(3.0 V to 3.6 V,

fCP =1.5 MHz to 12 MHz)

1.5

34 6 8 12 16

×4×3×2×1

No multiplier

Internal Clock fCP (MHz)

Source Oscillation Clock fC (MHz)

0.8 VCC

0.2 VCC

2.4 V

0.8 V

0.7 VCC

0.3 VCC

•Input signal waveform

Hysteresis input pin

Pins other than hy steresis in put or MD inp ut pins

•Output signal wavef orm

Output pin

MB90560/565 Series

74 DS07-13715-5E

(2) Reset (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

*: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to se veral

dozen ms; for a ceramic oscillator, this is several hundred µs to a few ms, a nd for an external clock this is 0 ms.

Parameter Symbol Pin Name Condition Value Unit Remarks

Min. Max.

Reset input time tRSTL RST ⎯

16 tCP ⎯ns In normal

operation

Oscillator oscillation

time* + 16 tCP ⎯ms In stop

mode

RST

0.2 VCC

tRSTL

0.2 VCC

• In normal operation

RST

16 tcp

tRSTL

0.2Vcc 0.2Vcc

Internal

operation

clock

Internal

reset

90 % of

amplitude

Oscillator

oscillation time

Oscillator stabilization wait time

Execution of the instruction

• In stop mode

MB90560/565 Series

DS07-13715-5E 75

(3) Power-On Reset (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

* : VCC must be less than 0.2 V before power-on.

Notes : • The above rating values are fo r generating a po wer-on reset.

• Some internal registers are only initialized by a power-on reset. Always apply the power supply in

accordance with the above ratings if you wish to initialize these registers.

Parameter Symbol Pin Name Condi-

tion Value Unit Remarks

Min. Max.

Power supply rise time tRVCC*⎯0.05 30 ms

Power supply cutoff time tOFF VCC 4⎯ms For repeated operation

VCC

2.5 V

VSS

0.2 V0.2 V

2.7 V

tOFF

0.2 V

Maintain RAM data

Recommended rate of voltage

rise is 50 mV/ms or less.

Sudden changes in the power supply voltage may cause a power-on reset.

The recommended practice if you wish to change the power supply voltage while the device is

operating is to raise the voltage smoothly as sho wn below. Also, chang es to th e supply volta ge

should be perf ormed when the PLL clock is not in use. The PLL clock ma y be used , however, if

the rate of voltage change is 1 V/s or less.

MB90560/565 Series

76 DS07-13715-5E

(4) UART0 and UART1 (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Notes : • These are the A C ratings for CLK synchronous mode.

• CV is the load capacitor connected to the pin for testing.

• tCP is the machine cycle period (unit = ns)

Parameter Symbol Pin Name Condition Value Unit Remarks

Min. Max.

Serial clock cycle time tSCYC SCK0, SCK1

Internal shift clock

mode, output pin

load is

CL = 80 pF + 1 TTL

8 tCP ⎯ns

SCK ↓ → SOT delay time tSLOV SCK0, SCK1

SOT0, SOT1 −80 80 ns

Valid SIN → SCK ↑tIVSH SCK0, SCK1

SIN0, SIN1 100 ⎯ns

SCK ↑ → valid SIN hold time tSHIX SCK0, SCK1

SIN0, SIN1 60 ⎯ns

Serial clock “H” pulse width tSHSL SCK0, SCK1

External shift clock

mode, output pin

load is

CL = 80 pF + 1 TTL

4 tCP ⎯ns

Serial clock “L” pulse width tSLSH SCK0, SCK1 4 tCP ⎯ns

SCK ↓ → SOT delay time tSLOV SCK0, SCK1

SOT0, SOT1 ⎯150 ns

Valid SIN → SCK ↑tIVSH SCK0, SCK1

SIN0, SIN1 60 ⎯ns

SCK ↑ → valid SIN hold time tSHIX SCK0, SCK1

SIN0, SIN1 60 ⎯ns

MB90560/565 Series

DS07-13715-5E 77

•Internal shift clock mode

•External shift clock mode

SCK

SOT

SIN

tSCYC

tSLOV

tIVSH tSHIX

0.8 V 0.8 V

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SCK

SOT

SIN

tSLSH tSHSL

tSLOV

tIVSH tSHIX

0.2 VCC 0.2 VCC

0.8 VCC 0.8 VCC

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

MB90560/565 Series

78 DS07-13715-5E

(5) Timer Input Timings (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

(6) Timer Output Timings (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

(7) Trigger Input Timings (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0. 0 V)

Parameter Symbol Pin Name Condi-

tion Value Unit Remarks

Min. Max.

Input pulse width tTIWH, tTIWL FRCK, TIN0, TIN1 ⎯4 tCP ⎯ns

Parameter Symbol Pin Name Condition Value Unit Remarks

Min. Max.

CLK ↑ → TOUT change

time tTO RTO0 to RTO5, PPG0 to PPG5

TO0, TO1 ⎯30 ⎯ns

Parameter Symbol Pin Name Condition Value Unit Remarks

Min. Max.

Input pulse width tTRGL INT0 to INT7, IN0 to IN3 ⎯5 tCP ⎯ns In normal

operation

1⎯µs In stop mode

0.8 VCC

FRCK

TIN0 to 1

0.8 VCC

0.2 VCC 0.2 VCC

tTIWH tTIWL

CLK

TOUT

2.4 V

0.8 V

0.8 VCC

INT0 to INT7

IN0 to IN3

0.8 VCC

0.2 VCC 0.2 VCC

tTRGH tTRGL

MB90560/565 Series

DS07-13715-5E 79

5. Electrical Characteristics for the A/D Converter

(MB90567/568/F568 : TA = −40 °C to +85 °C, 2.7 V ≤ AVR, VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0. 0 V)

(MB90V560 : TA = +25 °C, 3.0 V ≤ AVR, VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V)

* : Current when A/D converter is not used and CPU is in stop mode (VCC = AVCC = AVR = 3.3 V)

Notes : • The L reference voltage is fixed to AVSS. The relative error increases as AVR becomes smaller.

• Ensure that the output impedance of the e xternal circuit connected to the analog input meets the f ollowing

condition :

Output impedance of MB90F568 external circuit ≤ 14 kΩ (Sampling Time = 4 µs)

Output impedance of MB90567/568 external circuit ≤ 7 kΩ (Sampling Time = 4 µs)

• If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short.

Parameter Symbol Pin Name Value Unit Remarks

Min. Typ. Max.

Resolution ⎯⎯ ⎯⎯10 bit

Total error ⎯⎯ ⎯⎯±3.0 LSB

Non-linearity error ⎯⎯ ⎯⎯±2.5 LSB

Differential linearity

error ⎯⎯ ⎯⎯±1.9 LSB

Zero tran sition

voltage VOT AN0 to AN7 AVSS

−1.5 LSB AVSS

+0.5 LSB AVSS

+2.5 LSB V1 LSB = (AVR−AVSS/

1024

Full-scale transition

voltage VFST AN0 to AN7 AVR

−3.5 LSB AVR

−1.5 LSB AVR

+0.5 LSB V

Conversion time ⎯⎯ ⎯66 tCP ⎯ns

Sampling time ⎯⎯ ⎯32 tCP ⎯ns

Analog port input

current IAIN AN0 to AN7 ⎯⎯10 µA

Analog input voltage VAIN AN0 to AN7 0 ⎯AVR V

Reference voltage ⎯AVR 2.7 ⎯AVCC V

Power supply current IAAVCC ⎯15mA

IAH AVCC ⎯⎯ 5µA*

Reference voltage

supply current IRAVR ⎯100 200 µA

IRH AVR ⎯⎯ 5µA*

Variation between

channels ⎯AN0 to AN7 ⎯⎯ 4LSB

MB90560/565 Series

80 DS07-13715-5E

•Equivalent circuit of analog input circuit

CRON

Analog input

Comparator

MB90567/568/F568

RON = 7.1 kΩ approx.

C = 48.3 pF approx.

Note : The values listed are an indication only.

MB90560/565 Series

DS07-13715-5E 81

6. Flash Memory Erase and Programming Performance

• Points to note regarding the MB90F568, 567, and 568 specifications

This section describes the specification differences between the MB90F568/567/568 and the MB90F562B/562A/

561A.

(1) Functional differences

1) The 5 V to 3 V regulator has been removed in the MB96565 series.

The C pin has been changed to an N.C. pin.

2) The A/D converter unit in the MB96565 series has changed from a 5 V version to a 3 V version.

However, the conversion time an d sampling time remain the same.

3) The maximum voltage that can be applied to I/O pins has changed from 5 V to 3 V in the MB96565 series.

4) Added transfer counter clear function to UART in the MB96565 series.

This function restores the UART to its initial state when “0” is written to the UART reset bit.

(2) Points to note when using the devices

The MB90F562B, and F5 68 use P60 (14) as SIN1, P61 (15) as SO T1, and P40 (60) as SCK0 when pe rf orming

on-board programming.

Use the following pin settings when performing on-board programming.

* : These settings are f or usin g a Yokogaw a Digital Com puter Corporation writer for on-board pr og ra mming. Alter-

natively, writing can be performed from a PC, but a special write program is required.

Parameter Condition Value Units Remarks

Min Typ Max

Sector erase tim e

TA = + 25 °C

Vcc = 3.3 V

⎯115s

Excludes 00H programming prior

erasure

Chip erase time ⎯5⎯sExcludes 00H programming prior

erasure

Word (16 bit width)

programming time ⎯16 3,600 µs Excludes system-level overhead

Erase/Program cycle ⎯10,000 ⎯⎯cycle

Data holding time ⎯100,000 ⎯⎯h

Pin Name Pin I/O Level* Remark s

MD2 “H” lev el

Serial write mode settingsMD1 “H” lev el

MD0 “L” level

SIN1 Serial data input Normally shared with P60

SOT1 Serial data output Normally shared with P61

SCK0 Serial clock Normally shared with P40

P00 “L” level

P01 “H” level Input “L” level for PC writing

MB90560/565 Series

82 DS07-13715-5E

■EXAMPLE CHARACTERISTICS

(Continued)

MB90F568 ICC − VCC

MB90568 ICC − VCC

MB90F568 ICCS − VCC

02 2.5 3 3.5

(V)

(mA)

4 4.5

16 MHz

12 MHz

8 MHz

4 MHz

2 MHz

TA = +25 °C

02 2.5 3 3.5

VCC (V)

CC3

(mA)

4 4.5

16 MHz

12 MHz

8 MHz

4 MHz

2 MHz

= +25 °C

02 2.5 3 3.5

VCC (V)

ICCS

(mA)

4 4.5

16 MHz

12 MHz

8 MHz

4 MHz

2 MHz

= +25 °C

MB90560/565 Series

DS07-13715-5E 83

(Continued)

MB90568 ICCS − VCC

MB90F562 ICC − VCC

MB90562 ICC − VCC

02 2.5 3 3.5

VCC (V)

ICCS

(mA)

4 4.5

16 MHz

12 MHz

8 MHz

4 MHz

2 MHz

= +25 °C

2.5 3 3.5 4 4.5

VCC (V) 5 5.5 6 6.5

ICC

(mA)

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

TA = +25 °C

2.5 3 3.5 4 4.5

VCC (V) 5 5.5 6 6.5

ICC (mA)

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

TA = +25 °C

MB90560/565 Series

84 DS07-13715-5E

(Continued)

MB90F562 ICCS − VCC

MB90562 ICCS − VCC

2.5 3 3.5 4 4.5

VCC (V) 5 5.5 6 6.5

ICCS

(mA)

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

TA = +25 °C

2.5 3 3.5 4 4.5

VCC (V) 5 5.5 6 6.5

CCS

(mA)

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

= +25 °C

MB90560/565 Series

DS07-13715-5E 85

■ORDERING IN FORMATION

•MB90560 series

•MB90565 series

Part No. Package Remarks

MB90561AP

MB90562AP

MB90F562BP

64-pin plastic SH-DIP

(DIP-64P-M01)

MB90561APF

MB90562APF

MB90F562BPF

64-pin plastic QFP

(FPT-64P-M06)

MB90561APMC

MB90562APMC

MB90F562BPMC

64-pin plastic LQFP

(FPT-64P-M23)

Part No. Package Remarks

MB90567PF

MB90568PF

MB90F568PF

64-pin plastic QFP

(FPT-64P-M06)

MB90567PMC

MB90568PMC

MB90F568PMC

64-pin plastic LQFP

(FPT-64P-M23)

MB90560/565 Series

86 DS07-13715-5E

■PACKAGE DIMENSIONS

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

64-pin plastic QFP Lead pitch 1.00 mm

Package width ×

package length 14 × 20 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 3.35 mm MAX

Code

(Reference) P-QFP64-14×20-1.00

64-pin plastic QFP

(FPT-64P-M06)

2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6

0.20(.008)M

18.70±0.40

(.736±.016)

14.00±0.20

(.551±.008)

1.00(.039)

INDEX

0.10(.004)

119

3351

20.00±0.20(.787±.008)

24.70±0.40(.972±.016)

0.42±0.08

(.017±.003)

0.17±0.06

(.007±.002)

0~8°

1.20±0.20

(.047±.008)

3.00 +0.35

–0.20 (Mounting height)

.118+.014

–.008

0.25 +0.15

–0.20

.010 +.006

–.008

(Stand off)

Details of "A" part

"A" 0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB90560/565 Series

DS07-13715-5E 87

(Continued)

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

64-pin plastic LQFP Lead pitch 0.65 mm

Package width ×

package length 12.0 × 12.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm MAX

Code

(Reference) P-LFQFP64-12×12-0.65

64-pin plastic LQFP

(FPT-64P-M23)

2003 FUJITSU LIMITED F64034S-c-1-1

0.65(.026)

0.10(.004)

116

3348

*12.00±0.10(.472±.004)SQ

14.00±0.20(.551±.008)SQ

INDEX

0.32±0.05

(.013±.002) M

0.13(.005)

0.145±0.055

(.0057±.0022)

"A"

.059 –.004

+.008

–0.10

+0.20

1.50

0~8˚

0.25(.010)

(Mounting height)

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB90560/565 Series

88 DS07-13715-5E

■MAIN CHANGES IN THIS EDITION

The vertical lines marked in the left side of the page show the changes.

Page Section Change Results

⎯⎯

Deleted the description of old products MB90561, MB90562,

and MB90F562.

⎯⎯

The package code is changed.

(FPT-64P-M09 →FPT-64P-M23)

34 ■ PERIPHERAL FUNCTIONS

3. Watchdog Timer The resource name of watch timer is collected.

(clock timer → watch timer)

55 ■ PERIPHERAL FUNCTIONS

13. 1 Mbit Flash Memory Deleted “· Standard configuration for Fujitsu Microelectronics

standard ser ial on -b o ar d pr og r am m ing ”.

■ ELECTRICAL CHARACTERISTICS

(MB90560 SERIES)

5. Electrical Characterist ics for the A/D

Converter

Changed the items of “Zer o transition volt age” and “Full-scale

transition voltage”.

■ ELECTRICAL CHARACTERISTICS

(MB90565 SERIES)

5. Electrical Characterist ics for the A/D

Converter

Changed the items of “Zer o transition volt age” and “Full-scale

transition voltage”.

■ ORDERING INFORMATION Order informations ar e ch an ge d .

(MB90561APFM →MB90561APMC

MB90562APFM →MB90562APMC

MB90F562BPFM →MB90F562BPMC

MB90567PFM →MB90567PMC

MB90568PFM →MB90568PMC

MB90F568PFM →MB90F568PMC)

87 ■ PACKAGE DIMENSIONS The package figure is changed.

(FPT-64P-M09 →FPT-64P-M23)

MB90560/565 Series

DS07-13715-5E 89

MEMO

MB90560/565 Series

90 DS07-13715-5E

MEMO

MB90560/565 Series

DS07-13715-5E 91

MEMO

MB90560/565 Series

FUJITSU MICROELECTRONICS LIMITED

7-1, Nishishinjuku 2-chome, Shinjuku Dai-Ichi Seimei Bldg.,

Shinjuku-ku, Tokyo 163-0722, JAPAN

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, F. R. GERMANY

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTR ONICS K OREA LTD .

1002 Daechi-Dong, 206 KOSMO TOWER,

Kangnam-Gu, Seoul 135-280, KOREA

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTR ONICS ASIA PTE LTD .

151 Lorong Chuan, #05-08 New Tech Park,

Singapore 556741, SINGAPORE

Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

FUJITSU MICROELECTR ONICS SHANGHAI CO ., LTD.

No.222 Yan An Road(E), Rm.3102, Bund Center,

Shanghai 200002, P. R. CHINA

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTR ONICS PACIFIC ASIA LTD .

11 Canton Road, 10/F., World Commerce Centre,

Tsimshatsui, Kowloon, HONG KONG

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The informatio n, such as desc riptions of function and application circuit examples, in this document a re present ed solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use b ased on such information. When you develop equipment incorporat-

ing the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of functio n and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual p roper ty right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and househo ld use, but are not designed, developed and manufactured

as contemplated ( 1) for use acco mpanying fatal risks or dangers that, unless extremely high saf ety is secured, could h ave a ser ious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, me dical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redund ancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited Business & Media Promotion Dept.