ISL21007CFB830Z - Intersil Corporation

FN6326.7

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL21007

Precision, Low Noise FGA™Voltage

References

The ISL21007 FGA™ voltage references are extrem ely low

power, high precision, and low noise voltage references

fabricated on Intersil’s proprietary Floating Gate Analog

technology . The ISL21007 features very low noise (4.5µVP-P

for 0.1Hz to 10Hz) and very low operating current (150µA,

Max). In addition, the ISL21007 family features guaranteed

initial accuracy as low as ±0.5mV.

This combination of high initial accuracy, low drift, and low

output noise performance of the ISL21007 enables versatile

high performance control and data acquisition applications

with low power consumption.

Available Options

Pinout ISL21007

(8 LD SOIC)

TOP VIEW

Features

• Reference Output Voltage . . . . . .1.250V, 2.048V, 2.500V,

3.000V

• Initial Accuracy. . . . . . . . . . . . . . . . . . . .±0.5mV (B grade)

• Input Voltage Range

ISL21007-12, 20, 25. . . . . . . . . . . . . . . . . . . . .2.7V to 5.5V

ISL21007-30. . . . . . . . . . . . . . . . . . . . . . . . . . 3.2V to 5.5V

• Low Output Voltage Noise . . . . .4.5µVP-P (0.1Hz to 10Hz)

• Supply Current. . . . . . . . . . . . . . . . . . . . . . . .150µA (Max)

• Temperature Coefficient. . . . . . . . . . . .3ppm/°C (B grade)

• Operating Temperature Range. . . . . . . . .-40°C to +125°C

• Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC

• Pb-Free (RoHS Compliant)

Applications

• High Resolution A/Ds an d D/As

• Digital Meters

• Bar Code Scanners

• Basestations

• Battery Management/Monitoring

• Industrial/Instrumentation Equipment

PART NUMBER

VOUT

OPTION

(V)

INITIAL

ACCURACY

(mV) TEMPCO.

(ppm/°C)

ISL21007BFB812Z 1.250 ±0.5 3

ISL21007CFB812Z 1.250 ±1.0 5

ISL21007DFB812Z 1.250 ±2.0 10

ISL21007BFB820Z 2.048 ±0.5 3

ISL21007CFB820Z 2.048 ±1.0 5

ISL21007DFB820Z 2.048 ±2.0 10

ISL21007BFB825Z 2.500 ±0.5 3

ISL21007CFB825Z 2.500 ±1.0 5

ISL21007DFB825Z 2.500 ±2.0 10

ISL21007BFB830Z 3.000 ±0.5 3

ISL21007CFB830Z 3.000 ±1.0 5

ISL21007DFB830Z 3.000 ±2.0 10

GND or NC

VIN

DNC

GND

DNC

VOUT

TRIM

Data Sheet December 13, 2007

2FN6326.7

December 13, 2007

Ordering Information

PART NUMBER

(Notes 1, 2) PART MARKING VOUT OPTION

(V) GRADE TEMP. RANGE

(°C) PACKAGE

(Pb-Free) PKG. DWG. #

ISL21007BFB812Z 21007BF Z12 1.250 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007CFB812Z 21007CF Z12 1.250 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007DFB812Z 21007DF Z12 1.250 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007BFB820Z 21007BF Z20 2.048 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007CFB820Z 21007CF Z20 2.048 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007DFB820Z 21007DF Z20 2.048 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007BFB825Z 21007BF Z25 2.500 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007CFB825Z 21007CF Z25 2.500 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007DFB825Z 21007DF Z25 2.500 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007BFB830Z 21007BF Z30 3.000 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007CFB830Z 21007CF Z30 3.000 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15

ISL21007DFB830Z 21007DF Z30 3.000 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte

tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

ISL21007

3FN6326.7

December 13, 2007

Typical Application Circuit

Pin Descriptions

PIN NUMBER PIN NAME DESCRIPTION

1 GND or NC Ground or No Connection

2 VIN Power Supply Input Connection

4 GND Ground

5 TRIM Allows user trim VOUT ±2.5%

6 VOUT Voltage Reference Output Connection

3, 7, 8 DNC Do Not Connect; Internal Connection - Must Be Left Floating

FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC

0.001µF

10µF

LOW NOISE DAC OUTPUT

ISL21007-12, 20, 25, 30

GND

NC NC

TRIM

VOUT

VIN

+3V

X79000

SCK

RDY

DOWN

CLR

VCC

VREF

VSS

VOUT

VBUF

VFB

SPI BUS

ISL21007

4FN6326.7

December 13, 2007

Absolute Voltage Ratings Thermal Information

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V

Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . .-0.5V to VOUT + 1

Voltage on “DNC” pins . . . . No connections permitted to these pins.

ESD Rating

Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV

Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600V

Charged Device Model (CDM). . . . . . . . . . . . . . . . . . . . . . . . .2kV

Recommended Operating Conditions

Temperature Range (Industrial). . . . . . . . . . . . . . . .-40°C to +125°C

Thermal Resistance (Typical, Note 3) θJA (°C/W)

8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.12

Continuous Power Dissipation (Note 3) . . . . . . . . . . . . . TA = +70°C

8 Ld SOIC derate 5.88mW/°C above +70°C . . . . . . . . . . . . 471mW

Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

IMPORTANT NOTE: All paramete rs having Min/Max specif ications are guaranteed . Typ values are for information purp oses only. Unless otherwise noted, all test s are at

the specified temperature and are pulsed tests, therefore: TJ = TC = TA

NOTE:

3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Common Electrical Specifications (ISL21007-12, -20, -25, -30) TA = -40°C to +125°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

VOA VOUT Accuracy @ TA = +25°C ISL21007B -0.5 +0.5 mV

ISL21007C -1.0 +1.0 mV

ISL21007D -2.0 +2.0 mV

TC VOUT Output Voltage Temperature

Coefficient (Note 4) ISL21007B 3 ppm/°C

ISL21007C 5 ppm/°C

ISL21007D 10 ppm/°C

IIN Supply Current 75 150 µA

Trim Range ±2.0 ±2.5 %

tRTurn-on Settling Time VOUT = ±0.1% 120 µs

Ripple Rejection f = 10kHz 60 dB

eNOutput Voltage Noise 0.1Hz ≤ f ≤ 10Hz 4.5 µVP-P

VNBroadband Voltage Noise 10Hz ≤ f ≤ 1kHz 2.2 µVRMS

Noise Density f = 1kHz 60 nV/√Hz

Electrical Specifications (ISL21007-12, VOUT = 1.250V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

VIN Input Voltage Range 2.7 5.5 V

VOUT Output Voltage 1.250 V

ΔVOUT /ΔVIN Line Regulation 2.7V < VIN < 5.5V 100 700 µV/V

ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA ≤ IOUT ≤ 7mA 10 100 µV/mA

Sinking: -7mA ≤ IOUT ≤ 0mA 20 150 µV/mA

ISC Short Circuit Current TA = +25°C, VOUT tied to GND 40 mA

ΔVOUT/ΔTAThermal Hysteresis (Note 5) ΔTA = +165°C 50 ppm

ΔVOUT/Δt Long Term Stability (Note 6) TA = +25°C 100 ppm

ISL21007

5FN6326.7

December 13, 2007

Electrical Specifications (ISL21007-20, VOUT = 2.048V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

VIN Input Voltage Range 2.7 5.5 V

VOUT Output Voltage 2.048 V

ΔVOUT /ΔVIN Line Regulation 2.7V < VIN < 5.5V 50 200 µV/V

ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA ≤ IOUT ≤ 7mA 10 100 µV/mA

Sinking: -7mA ≤ IOUT ≤ 0mA 20 150 µV/mA

ISC Short Circuit Current TA = +25°C, VOUT tied to GND 50 mA

ΔVOUT/ΔTAThermal Hysteresis (Note 5) ΔTA = +165°C 50 ppm

ΔVOUT/Δt Long Term Stability (Note 6) TA = +25°C 75 ppm

Electrical Specifications (ISL21007-25, VOUT = 2.500V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

VIN Input Voltage Range 2.7 5.5 V

VOUT Output Voltage 2.500 V

ΔVOUT /ΔVIN Line Regulation 2.7V < VIN < 5.5V 50 200 µV/V

ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA ≤ IOUT ≤ 5mA 10 100 µV/mA

Sinking: -5mA ≤ IOUT ≤ 0mA 20 150 µV/mA

ISC Short Circuit Current TA = +25°C, VOUT tied to GND 50 mA

ΔVOUT/ΔTAThermal Hysteresis (Note 5) ΔTA = +165°C 50 ppm

ΔVOUT/Δt Long Term Stability (Note 6) TA = +25°C 50 ppm

Electrical Specifications (ISL21007-30, VOUT = 3.000V) VIN = 5.0V, TA = -40°C to +125°C, unless otherwise specified

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

VIN Input Voltage Range 3.2 5.5 V

VOUT Output Voltage 3.000 V

ΔVOUT /ΔVIN Line Regulation 3.2V < VIN < 5.5V 50 200 µV/V

ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA ≤ IOUT ≤ 7mA 10 100 µV/mA

Sinking: -7mA ≤ IOUT ≤ 0mA 20 150 µV/mA

ISC Short Circuit Current TA = +25°C, VOUT tied to GND 50 mA

ΔVOUT/ΔTAThermal Hysteresis (Note 5) ΔTA = +165°C 50 ppm

ΔVOUT/Δt Long Term Stability (Note 6) TA = +25°C 50 ppm

4. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the

temperature range; in this case, -40°C to +125°C = +165°C.

5. Thermal Hysteresis is the change of VOUT measured at T A = +25°C after temperature cycling over a specified range, ΔTA. VOUT is read initially

at T A = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference

between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For Δ TA = +165°C, the device under test is cycled

from +25°C to +125°C to -40°C to +25°C.

6. Long term drift is logarithmic in nature and diminishes over time. Drift after the first 1000 hours will be approximately 10ppm/√(1kHrs)

ISL21007

6FN6326.7

December 13, 2007

Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)

FIGURE 2. IIN vs VIN (3 UNITS) FIGURE 3. IIN vs VIN OVER TEMPERATURE

FIGURE 4. LINE REGULATION (3 UNITS) FIGURE 5. LINE REGULATION OVER TEMPERATURE

FIGURE 6. LOAD REGULATION OVER TEMPERATURE FIGURE 7. VOUT vs TEMPERATURE (3 UNITS)

100

120

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VIN (V)

IIN (µA)

UNIT 3

UNIT 1 UNIT 2

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VIN (V)

IIN (µA)

+125°C

+25°C

-40°C

1.24980

1.24985

1.24990

1.24995

1.25000

1.25005

1.25010

1.25015

VOUT (V)

(NORMALIZED TO 1.250V AT VIN = 3.0V)

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VIN (V)

UNIT 3

UNIT 1

UNIT 2

-300

-250

-200

-150

-100

-50

100

150

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VIN (V)

ΔVO (µV)

(NORMALIZED TO VIN = 3.0V)

+125°C

+25°C -40°C

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-7 -6 -5 -4 -3 -2 -1 0 1

SINKING SOURCING

ΔVOUT (mV)

234567

OUTPUT CURRENT (mA)

+125°C

+25°C

-40°C

1.24975

1.24980

1.24985

1.24990

1.24995

1.25000

1.25005

1.25010

-40 -20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

VOUT (V)

UNIT 2

UNIT 1

UNIT 3

ISL21007

7FN6326.7

December 13, 2007

FIGURE 8. PSRR vs CAPACITIVE LOADS FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE

LOAD

FIGURE 10. LINE TRANSIENT RESPONSE, 0.001µF LOAD

CAPACITANCE FIGURE 11. TURN-ON TIME

FIGURE 12. ZOUT vs FREQUENCY FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz

Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) (Continued)

-100

-80

-60

-40

-20

1.00E+00 1.00E+02 1.00E+04 1.00E+0

FREQUENCY (Hz)

PSRR (dB)

1nF LOAD

100nF LOAD

10nF LOAD

1µF LOAD

NO LOAD

Y: 10µs/DIV

X: 200mV/DIV

ΔVIN = -0.3V

ΔVIN = +0.3V

Y: 10µs/DIV

X: 200mV/DIV

ΔVIN = -0.3V

ΔVIN = +0.3V VIN

VOUT = 1.25V

X: 20µs/DIV

Y: 1V/DIV

100

120

140

1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06

FREQUENCY (Hz)

ZOUT (Ω)

NO LOAD

1nF

10nF

100nF

2mV/DIV

GAIN IS x1000,

NOISE IS 4.5µVP-P

ISL21007

8FN6326.7

December 13, 2007

FIGURE 14. LOAD TRANSIENT RESPONSE

Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) (Continued)

NO OUTPUT CAPACITANCE

+7mA

-7mA

X: 50µs/DIV

Y: 1V/DIV

Typical Performance Curves (ISL21007-20) (REXT = 100kΩ)

FIGURE 15. IIN vs VIN (3 UNITS) FIGURE 16. IIN vs VIN OVER TEMPERATURE

FIGURE 17. LINE REGULATION (3 UNITS) FIGURE 18. LINE REGULATION OVER TEMPERATURE

2.73.13.53.94.34.75.15.5

VIN (V)

IIN (µA)

UNIT 3

UNIT 2

UNIT 1

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

VIN (V)

IIN (uA)

+125°C

-40°C

+25°C

2.04790

2.04795

2.04800

2.04805

2.04810

2.04815

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VIN(V)

VOUT (V) NORMALIZED TO 2.048V AT

VIN = 3.0V

UNIT 1

UNIT 3

UNIT 2

2.04795

2.04800

2.04805

2.04810

2.04815

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VIN(V)

+125°C

+25°C

-40°C

VOUT (V)

(NORMALIZED TO 2.048V AT VIN = 3V)

ISL21007

9FN6326.7

December 13, 2007

FIGURE 19. LOAD REGULATION OVER TEMPERATURE FIGURE 20. VOUT vs TEMPERATURE (3 UNITS)

FIGURE 21. PSRR vs CAPACITIVE LOADS FIGURE 22. LINE TRANSIENT RESPONSE, NO CAPACITIVE

LOAD

FIGURE 23. LINE TRANSIENT RESPONSE, 0.001µF LOAD

CAPACITANCE FIGURE 24. TURN-ON TIME

Typical Performance Curves (ISL21007-20) (REXT = 100kΩ) (Continued)

-1.2

-0.8

-0.4

0.0

0.4

0.0

1.2

1.6

-7 -6 -5 -4 -3 -2 -1

Δ VOUT (mV) NORMALIZED TO 0mA

01234567

+25°C

-40°C

+125°C

SINKING SOURCINGOUTPUT CURRENT (mA)

2.0472

2.0476

2.0480

2.0484

2.0488

2.0492

2.0496

-40-25-10 5 203550658095110125

TEMPERATURE (°C)

VOUT(V) NORMALIZED TO 2.048V AT +25°C

UNIT 2 UNIT 1

UNIT 3

-100

-80

-60

-40

-20

1.0E+01 1.0E+03 1.0E+05

FREQUENCY (Hz)

PSRR (dB)

100nF LOAD

10nF LOAD

1µF LOAD

NO LOAD

Y: 10µs/DIV

X: 200mV/DIV

ΔVIN = -0.3V

ΔVIN = +0.3V

Y: 10µs/DIV

X: 200mV/DIV

ΔVIN = -0.3V

ΔVIN = +0.3V

X: 100µs/DIV

Y: 2V/DIV

VIN

VOUT = 2.048V

ISL21007

10 FN6326.7

December 13, 2007

FIGURE 25. ZOUT VS FREQUENCY FIGURE 26. VOUT NOISE, 0.1H z TO 10Hz

FIGURE 27. LOAD TRANSIENT RESPONSE, 0.001µF LOAD

CAPACITANCE FIGURE 28. LOAD TRANSIENT RESPONSE, NO CAP ACITIVE

LOAD

Typical Performance Curves (ISL21007-20) (REXT = 100kΩ) (Continued)

100

120

140

1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06

FREQUENCY (Hz)

ZOUT (Ω)

NO LOAD

1nF

10nF

100nF

GAIN IS x1000,

NOISE IS 4.5µVP-P

2mV/DIV

X: 20µs/DIV

Y: 200mV/DIV +7mA

-7mA

X: 20µs/DIV

Y: 200mV/DIV +7mA

-7mA

Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)

FIGURE 29. IIN vs VIN (3 UNITS) FIGURE 30. IIN vs VIN OVER TEMPERATURE

100

120

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VIN (V)

IIN (µA)

UNIT 3

UNIT 2

UNIT 1

100

2.5 3.0 4.0 4.5 5.0 5.5

VIN (V)

IIN (µA)

3.5

+125°C

+25°C -40°C

ISL21007

11 FN6326.7

December 13, 2007

FIGURE 31. LINE REGULATION (3 UNITS) FIGURE 32. LINE REGULATION OVER TEMPERATURE

FIGURE 33. LOAD REGULATION OVER TEMPERATURE FIGURE 34. VOUT vs TEMPERATURE (3 UNITS)

FIGURE 35. PSRR vs CAPACITIVE LOADS FIGURE 36. LINE TRANSIENT RESPONSE, NO CAPACITIVE

LOAD

Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued)

2.4996

2.4997

2.4998

2.4999

2.5000

2.5001

2.5002

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VIN (V)

VOUT (V)

(NORMALIZED TO 2.500V AT VIN = 3V)

UNIT 1

UNIT 2

UNIT 3

-400

-350

-300

-250

-200

-150

-100

-50

100

2.5 3.0 3.5 4.5 5.0 5.5

VIN (V)

ΔVO (µV)

(NORMALIZED TO VIN = 3.0V)

4.0 6.0

+125°C

+25°C

-40°C

-1.0

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

-7 -2 1 2 3 4 5 6 7

ΔVOUT (mV)

-6 -5 -4 -3 -1 0

+125°C

-40°C

+25°C

SINKING SOURCINGOUTPUT CURRENT (mA)

2.4993

2.4994

2.4995

2.4996

2.4997

2.4998

2.4999

2.5000

2.5001

2.5002

2.5003

-40 -20 0 20 40 60 80 100 120 140

TEMPER ATURE (°C)

OUT

(V)

UNIT 1

UNIT 2

UNIT 3

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

1.E+00 1.E+02 1.E+04 1.E+06

FREQUENCY (Hz)

PSRR (dB)

10nF

NO LOAD

1nF

100nF

1µF

Y: 10µs/DIV

X: 200mV/DIV

ΔVIN = -0.3V

ΔVIN = +0.3V

ISL21007

12 FN6326.7

December 13, 2007

FIGURE 37. LINE TRANSIENT RESPONSE, 0.001µF LOAD

CAPACITANCE FIGURE 38. TURN-ON TIME

FIGURE 39. ZOUT vs FREQUENCY FIGURE 40. VOUT NOISE, 0.1Hz TO 10Hz

FIGURE 41. LOAD TRANSIENT RESPONSE

Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued)

Y: 10µs/DIV

X: 200mV/DIV

ΔVIN = -0.3V

ΔVIN = +0.3V

VIN

VOUT = 2.5V

X: 20µs/DIV

Y: 1V/DIV

100

120

140

1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06

FREQUENCY (Hz)

ZOUT (Ω)

NO LOAD

1nF

10nF

100nF

2mV/DIV

GAIN IS x1000,

NOISE IS 4.5µVP-P

NO OUTPUT CAPACITANCE

+5mA

-5mA

X: 50µs/DIV

Y: 500mV/DIV

ISL21007

13 FN6326.7

December 13, 2007

Typical Performance Curves (ISL21007-30) (REXT = 100kΩ)

FIGURE 42. IIN vs VIN (3 UNITS) FIGURE 43. IIN vs VIN OVER TEMPERATURE

FIGURE 44. LINE REGULATION (3 UNITS) FIGURE 45. LINE REGULATION OVER TEMPERATURE

FIGURE 46. LOAD REGULATION OVER TEMPERATURE FIGURE 47. VOUT vs TEMPERATURE (3 UNITS)

100

120

3.2 3.7 4.2 4.7 5.2

VIN (V)

IIN (µA)

UNIT 3 UNIT 2

UNIT 1

100

120

3.2 3.7 4.2 4.7 5.2

VIN (V)

IIN (µA)

+125°C

+25°C -40°C-40°C

2.9955

2.9965

2.9975

2.9985

2.9995

3.0005

3.2 3.6 4.0 4.4 4.8 5.2 5.6

VIN (V)

VOUT(V) NORMALIZED TO 3.0V AT

5.0VIN

UNIT 3 UNIT 2

UNIT 1

2.994

2.995

2.996

2.997

2.998

2.999

3.000

3.001

3.2 3.6 4.0 4.4 4.8 5.2 5.6

VIN (V)

VOUT (V) NORMALIZED TO 3.0V AT

5.0VIN

+125°C

-40°C

+25°C

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

-7 -6 -5 -4 -3 -2 -1

SINKING LOAD (mA) SOURCING

Δ VOUT (mV) NORMALIZED TO

0mA

01 234 56 7

-40°C

+25°C

+125°C

2.9990

2.9992

2.9994

2.9996

2.9998

3.0000

3.0002

3.0004

3.0006

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

VOUT (V) NORMALIZED TO 3.0V AT +25°C

UNIT 3

UNIT 2

UNIT 1

ISL21007

14 FN6326.7

December 13, 2007

FIGURE 48. PSRR vs CAPACITIVE LOADS FIGURE 49. LINE TRANSIENT RESPONSE, NO CAPACITIVE

LOAD

FIGURE 50. LINE TRANSIENT RESPONSE, 0.001µF LOAD

CAPACITANCE FIGURE 51. TURN-ON TIME

FIGURE 52. ZOUT vs FREQUENCY FIGURE 53. VOUT NOISE, 0.1Hz TO 10Hz

Typical Performance Curves (ISL21007-30) (REXT = 100kΩ) (Continued)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

1.E+00 1.E+02 1.E+04 1.E+06

FREQUENCY (Hz)

PSRR (dB)

10nF

NO LOAD

1nF

100nF

1µF

VIN (DC) = 5.0V

VIN (AC) = 50mVP-P

Y: 10µs/DIV

X: 200mV/DIV

ΔVIN = -0.5V

ΔVIN = +0.5V

Y: 10µs/DIV

X: 200mV/DIV

ΔVIN = -0.5V

ΔVIN = +0.5V

VIN = 5.0V

VOUT = 3.0V

20µs/DIV

1V/DIV

100

120

140

1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06

FREQUENCY (Hz)

ZOUT (Ω)

NO LOAD

1nF

10nF

100nF

2mV/DIV

GAIN IS x1000,

NOISE IS 4.5µVP-P

ISL21007

15 FN6326.7

December 13, 2007

Applications Information

FGA Technology

The ISL21007 voltage reference uses floating gate

technology to create refere nces with very low drift and

supply current. Essentially, the charge stored on a floating

gate cell is set precisely in manufacturing. The reference

voltage output itself is a buffered version of the floating gate

voltage. The resulting reference device has excellent

characteristics which are unique in the industry: very low

temperature drift, high initial accuracy, and almost zero

supply current. Also, the reference voltage itself is not limited

by voltage bandgaps or zener settings, so a wide range of

reference voltages can be programmed (standard voltage

settings are provided, but customer-specific voltages are

available).

The process used for these reference devices is a floating

gate CMOS process, and the amplifier circuitry uses CMOS

transistors for amplifier and output transistor circuitry. While

providing excellent accuracy, there are limitations in output

noise level and load regulation due to the MOS device

characteristics. These limitations are addressed with circuit

techniques discussed in other sections.

Micropower Operation

The ISL21007 consumes extremely low supply current due

to the proprietary FGA technology . Low noise performance is

achieved using optimized biasing techniques. Supply current

is typically 75µA and noise is 4.5µVP-P benefitting precision,

low noise portable applications such as handheld meters

and instruments.

Data Converters in particular can utilize the ISL21007 as an

external voltage reference. Low power DAC and ADC

circuits will realize maximum resolution with lowest noise.

Board Mounting Considerations

For applications requiring the highest accuracy, board

mounting location shoul d be reviewed. The device uses a

plastic SOIC package, which will subject the die to mild

stresses when the PC board is heated and cooled and

slightly change its shape. Placing the device in areas subject

to slight twisting can cause degradation of the accuracy of

the reference voltage due to these die stresses. It is normally

best to place the device near the edge of a board, or the

shortest side, as the axis of bending is most limited at that

location. Mounting the device in a cutout also minimizes flex.

Obviously, mounting the device on flexprint or extremely thin

PC material will likewise cause loss of reference accuracy.

Noise Performance and Reduction

The output noise voltage in a 0.1H z to 10Hz ba ndwi d th is

typical l y 4. 5µ VP-P. The noise measurement is made with a

bandp ass filter made of a 1 pole high-p ass fi lter with a corner

frequency at 0.1Hz and a 2-pole low-pa ss filter with a corner

frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth.

Noise in the 10kHz to 1MHz bandwid th is approximately

40µVP-P with no capacit ance on the output. This noise

measurement is made with a 2 decade band p ass fil ter made

of a 1 pole high-p ass filter with a corner frequency a t 1/10 of

the center frequency and 1-pole low-p ass filter with a co rner

frequency at 10 times the center fre quency. Load capacita nce

up to 1000pF can be added but will result in on ly marginal

improvements in output noise and tra nsient re sponse. The

output stage of the ISL21007 is not designed to drive heavily

capacitive loads, so for load cap acitances above 0.001µF, the

noise reduction network show n in Figure 55 is recommended .

This network reduces noise significantly over the fu ll

bandwidth. Noi se is reduced to less than 20 µVP-P from 1Hz to

1MHz using this network with a 0.01µF capacitor and a 2kΩ

resistor in series with a 10µF cap acitor. Also, transient

response is improved with higher value output cap acitor. The

0.01µF value can be increased for better load transient

response with little sacrif ice in outp ut st ab ility.

FIGURE 54. LOAD TRANSIENT RESPONSE

Typical Performance Curves (ISL21007-30) (REXT = 100kΩ) (Continued)

+7mA

-7mA

100µs/DIV

200mV/DIV

ISL21007

16 FN6326.7

December 13, 2007

Turn-On Time

The ISL21007 devices have low supply current and thus the

time to bias up internal circuitry to final values will be longer

than with higher power references. Normal turn-on time is

typically 120µs. This is shown in Figure 10. Circuit design

must take this into account when looking at power-up delays

or sequencing.

Temperature Coefficient

The limits stated for temperature coefficient (tempco) are

governed by the method of measurement. The overwhelming

standard for specifying the temperature drift of a reference is to

measure the reference voltage at two temperatures, take the

total variation, (VHIGH – VLOW), and divide by the temperature

extremes of measurem ent (THIGH –T

LOW). The result is

divided by the nominal reference voltage (at T = +25°C) and

multiplied by 106 to yield ppm/°C. This is the “Box” method for

specifying temperature coefficient.

Output Voltage Adjustment

The output voltage can be adjusted up or down by 2.5% by

placing a potentiometer from VOUT to ground, and connecting

the wiper to the TRIM pin. The TRIM input is high impedance,

so no series resistance is needed. The resistor in the

potentiometer should be a low tempco (<50ppm/°C) and the

resulting voltage divider should have very low tempco

<5ppm/°C. A digital potentiometer such as the ISL95810

provides a low tempco resistance and excellent resistor and

tempco matching for trim applications. See Figure 58 and

TB473 for further information.

VIN = 5.0V

VIN VO

GND

ISL21007

0.01µF

10µF

2kΩ

0.1µF

10µF

FIGURE 55. HANDLING HIGH LOAD CAPACITANCE

Typical Application Circuits

FIGURE 56. PRECISION 2.500V 50mA REFERENCE

VIN = +5.0V

2N2905

2.5V/50mA

0.001µF

VIN

VOUT

GND

ISL21007

R = 200Ω

VOUT = 2.500V

ISL21007

17 FN6326.7

December 13, 2007

FIGURE 57. 2.500V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE

FIGURE 58. KELVIN SENSED LOAD

FIGURE 59. OUTPUT ADJUSTMENT USING THE TRIM PIN

Typical Application Circuits (Continued)

VIN

VOUT

GND

+2.7 TO 5.5V 0.1µF

0.001µF

VOUT

–

VCC RH

X9119

VSS

SDA

SCL

2-WIRE BUS VOUT

(BUFFERED)

10µF

ISL21007-25

VOUT = 2.500V

EL8178

(UNBUFFERED)

0.1µF

+2.7 TO 5.5V

VIN

VOUT

GND

ISL21007-12

VOUT SENSE

LOAD

–

10µF

EL8178

0.1µF

+2.7 TO 5.5V

VIN VOUT

GND

ISL21007-12

10µF

TRIM

2.5V ±2.5%

VSS

SDA

SCL

I2C BUS

VCC RH

ISL95810

ISL21007

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6326.7

December 13, 2007

ISL21007

Small Outline Plastic Packages (SOIC)

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α0° 8° 0° 8° -

Rev. 1 6/05