IDT72131 IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 FEATURES: * * * * * * * * * * * DESCRIPTION: 35ns parallel port access time, 45ns cycle time 50MHz serial port shift rate Expandable in depth and width with no external components Programmable word lengths including 7-9, 16-18, 32-36 bit using Flexishift serial output without using any additional components Multiple status flags: Full, Almost-Full (1/8 from full), Half-Full, Almost- Empty (1/8 from empty), and Empty Asynchronous and simultaneous read and write operations Dual-Port zero fall-through architecture Retransmit capability in single device mode Produced with high-performance, low power CMOS technology Available in 28-pin plastic DIP Industrial temperature range (-40C to +85C) The IDT72131/72141 are high-speed, low power parallel-to-serial FIFOs. These FIFOs are ideally suited to serial communications applications, tape/ disk controllers, and local area networks (LANs). These devices can be configured with the IDTs serial-to-parallel FIFOs (IDT72132/72142) for bidirectional serial data buffering. The FIFO has a 9-bit parallel input port and a serial output port. Wider and deeper parallel-to-serial data buffers can be built using multiple IDT72131/72141 chips. IDTs unique Flexishift serial expansion logic (SOX, NR) makes width expansion possible with no additional components. These FIFOs will expand to a variety of word widths including 8, 9, 16, and 32 bits. These devices can also be directly connected for depth expansion. Five flags are provided to monitor the FIFO. The full and empty flags prevent any FIFO data overflow or underflow conditions. The Almost-Full (7/8), Half-Full, and Almost-Empty (1/8) flags signal memory utilization within the FIFO. The IDT72131/72141 is fabricated using IDTs high-speed submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION D0-D8 EF AEF FLAG LOGIC W RS FL/RT RAM ARRAY 2,048 x 9 4,096 x 9 WRITE POINTER /HF FF NEXT READ POINTER NR RESET LOGIC SOCP XI EXPANSION LOGIC XO/ SERIAL OUTPUT CIRCUITRY Q4 Q6 Q7 Q8 SOX SO W 1 28 Vcc D4 2 27 D5 D3 3 26 D6 D2 4 25 D7 D1 5 24 D8 D0 6 23 FL/RT XI 7 22 RS SOX 8 21 EF SOCP 9 20 XO/HF SO 10 19 GND AEF 11 18 Q8 FF 12 17 Q7 Q4 13 16 Q6 GND 14 15 NR 2751 drw01 2751 drw02 PLASTIC DIP (P28-1, order code: P) TOP VIEW IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2002 1 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2751/1 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTIONS Symbol D0-D8 Name Inputs I/O I RS Reset I When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM array. HF and FF go HIGH, and AEF and EF go LOW. A reset is required before an initial WRITE after power-up. W must be HIGH and SOCP must be LOW during RS cycle. W Write I A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation. SOCP Serial Output Clock Next Read I A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together. To program the Serial Out data word width , connect NR with one of the Data Set pins (Q4, Q6, Q7 and Q8). For example, NR - Q7 programs for a 8-bit Serial Out word width. This is a dual purpose input. In the single device configuration (XI grounded), activating retransmit (FL/RTLOW) will set the internal READ pointer to the first location. There is no effect on the WRITE pointer. W must be high and SOCP must be low before setting FL/RT LOW. Retransmit is not compatible with depth expansion. In the depth expansion configuration, FL/RT grounded indicates the first activated device. In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion, XI is connected to XO (expansion out) of the previous device. NR Description Data inputs for 9-bit wide data. I FL/RT First Load/ Retransmit I XI Expansion In I SOX Serial Output Expansion I In the Serial Output Expansion mode, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other devices is connected to the Q8 pin of the previous device. Data is then clocked out least significant bit first. For single device operation, SOX is tied HIGH. SO Serial Output O FF Full Flag O Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first. In the Serial Width Expansion mode the SO pins are tied together and each SO pin is tristated at the end of the byte. When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH, the device is not full. EF Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the device is not empty. See the description on page 6 for more details. AEF Almost-Empty/ Almost-Full Flag Expansion Out/ Half-Full Flag O When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH, the device is greater than 1/8 full, but less than 7/8 full. This is a dual-purpose output. In the single device configuration (XI grounded), the device is more than half full when HF is LOW. In the depth expansion configuration (XO connected to XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array is filled. The appropriate Data Set pin (Q4, Q6, Q7 and Q8) is connected to NR to program the Serial Out data word width. For example: Q6 - NR programs a 7-bit word width, Q8 - NR programs a 9-bit word width, etc. XO/HF Q4, Q6, Q7 and Q8 Data Set VCC GND Power Supply Ground O O Single Power Supply of 5V. Single ground at 0V. STATUS FLAGS Number of Words in FIFO IDT72131 IDT72141 FF AEF HF EF 0 0 H L H L 1-255 1-511 H L H H 256-1,024 512-2,048 H H H H 1,025-1,792 2,049-3,584 H H L H 1,793-2,047 3,585-4,095 H L L H 2,048 4,096 L L L H 2 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Commercial Unit VTERM Terminal Voltage with Respect to GND -0.5 to +7.0 V TSTG Storage Temperature -55 to +125 C IOUT DC Output Current -50 to +50 mA RECOMMENDED OPERATING CONDITIONS Symbol NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VCC Commercial Supply Voltage GND Supply Voltage VIH Input High Voltage Commercial 2.0 -- -- V VIL(1) Input Low Voltage -- -- 0.8 V TA Operating Temperature Industrial -40 -- 85 C NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. CAPACITANCE Symbol (TA = +25C, f = 1.0MHz) Max. Unit CIN Input Capacitance Parameter VIN = 0V Conditions 10 pF COUT Output Capacitance VOUT = 0V 12 pF NOTE: 1. Characterized values, not currently tested. DC ELECTRICAL CHARACTERISTICS (Industrial: VCC = 5.0V 10%, TA = -40C to +85C) IDT72131 IDT72141 Industrial Symbol Min. Typ. Max. Unit Input Leakage Current (Any Input) -1 -- 1 A IOL(2) Output Leakage Current -10 -- 10 A VOH Output Logic "1" Voltage, IOUT = -2mA 2.4 -- -- V VOL Output Logic "0" Voltage IOUT = 8mA -- -- 0.4 V Active Power Supply Current -- 90 140 mA Standby Current (W = RS = FL/RT = VIH; SOCP = VIL) -- 8 12 mA Power Down Current -- -- 2 mA IIL (1) ICC1(3) ICC2 (3,4) ICC3(3,4) Parameter NOTES: 1. Measurements with 0.4 VIN VCC. 2. SOCP VIL, 0.4 VOUT VCC. 3. Tested with outputs open (IOUT = 0). 4. RS = FL/RT = W = VCC -0.2V; SOCP 0.2V; all other inputs = VCC - 0.2V or GND + 0.2V, which toggle at 20 MHz. 3 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Industrial: VCC = 5.0V 10%, TA = -40C to +85C) Industrial Symbol IDT72131L35 IDT72141L35 Min. Max. Parameter IDT72131L50 IDT72141L50 Min. Max. Unit tS Parallel Shift Frequency -- 22.2 -- 15 MHz tSOCP Serial-Out Shift Frequency -- 50 -- 40 MHz 18 -- 30 -- ns ns PARALLEL INPUT TIMINGS tDS Data Set-up Time tDH Data Hold Time 0 -- 5 -- tWC Write Cycle Time 45 -- 65 -- ns tWPW Write Pulse Width 35 -- 50 -- ns tWR Write Recovery Time 10 -- 15 -- ns tWEF Write High to EF HIGH -- 30 -- 45 ns tWFF Write Low to FF LOW -- 30 -- 45 ns tWF Write Low to Transitioning HF, AEF -- 45 -- 65 ns tWPF Write Pulse Width After FF HIGH 35 -- 50 -- ns SERIAL OUTPUT TIMINGS tSOHZ SOCP Rising Edge to SO at High-Z(1) 5 16 5 26 ns tSOLZ SOCP Rising Edge to SO at Low-Z(1) 5 22 5 22 ns tSOPD SOCP Rising Edge to Valid Data on SO -- 18 -- 18 ns tSOX SOX Set-up Time to SOCP Rising Edge 5 -- 5 -- ns tSOCW Serial In Clock Width HIGH/LOW 8 -- 10 -- ns tSOCEF SOCP Rising Edge (Bit 0 - Last Word) to EF LOW -- 20 -- 25 ns tSOCFF SOCP Rising Edge to FF HIGH -- 30 -- 40 ns tSOCF SOCP Rising Edge to HF, AEF, HIGH -- 30 -- 40 ns tREFSO Recovery Time SOCP After EF HIGH 35 -- 50 -- ns RESET TIMINGS tRSC Reset Cycle Time 45 -- 65 -- ns tRS Reset Pulse Width 35 -- 50 -- ns tRSS Reset Set-up Time 35 -- 50 -- ns tRSR Reset Recovery Time 10 -- 15 -- ns tRSF1 Reset to EF and AEF LOW -- 45 -- 65 ns tRSF2 Reset to HF and FF HIGH -- 45 -- 65 ns tRSQL Reset to Q LOW 20 -- 35 -- ns tRSQH Reset to Q HIGH 20 -- 35 -- ns RETRANSMIT TIMINGS tRTC Retransmit Cycle Time 45 -- 65 -- ns tRT Retransmit Pulse Width 35 -- 50 -- ns tRTS Retransmit Set-up Time 35 -- 50 -- ns tRTR Retransmit Recovery Time 10 -- 15 -- ns -- 35 -- 50 ns DEPTH EXPANSION MODE TIMINGS tXOL Read/Write to XO LOW tXOH Read/Write to XO HIGH -- 35 -- 50 ns tXI XI Pulse Width 35 -- 50 -- ns tXIR XI Recovery Time 10 -- 10 -- ns tXIS XI Set-up Time 15 -- 15 -- ns NOTE: 1. Guaranteed by design minimum times, not tested. 4 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE AC TEST CONDITIONS 5V Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load 1.1K D.U.T. 680 See Figure A 30pF* 2751 drw03 or equivalent circuit Figure A. Output Load *Including jig and scope capacitances FUNCTIONAL DESCRIPTION SERIAL DATA OUTPUT The serial data is output on the SO pin. The data is clocked out on the rising edge of SOCP providing the Empty Flag (EF) is not asserted. If the Empty Flag is asserted then the next data word is inhibited from moving to the output register and being clocked out by SOCP. NOTE: SOCP should not be clocked once the last bit of the last word has been clocked out. If it is, then two things will occur. One, the SO pin will go High-Z and two, SOCP will be out of sync with Next Read (NR). The serial word is shifted out Least Significant Bit first, that is the first bit will be D0, then D1 and so on up to the serial word width. The serial word width must be programmed by connecting the appropriate Data Set line (Q4, Q6, Q7 or Q8) to the NR input. The Data Set lines are taps off a digital delay line. Selecting one of these taps, programs the width of the serial word to be read and shifted out. PARALLEL DATA INPUT The data is written into the FIFO in parallel through the D0-8 input data lines. A write cycle is initiated on the falling edge of the Write (W) signal provided the Full Flag (FF) is not asserted. If the W signal changes from HIGH-to-LOW and the Full-Flag (FF) is already set, the write line is inhibited internally from incrementing the write pointer and no write operation occurs. Data set-up and hold times must be met with respect to the rising edge of Write. The data is written to the RAM at the write pointer. On the rising edge of W, the write pointer is incremented. Write operations can occur simultaneously or asynchronously with read operations. tRSC tRS RS tRSS tRSR W tRSF1 AEF, EF tRSF2 HF, FF tRSS tRSR SOCP tRSQL tRSQH Q4, Q6, Q7, Q8 2751 drw04 Figure 1. Reset 5 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE tWC W tWR tWPW tDS tDH D0-8 2751 drw05 Figure 2. Write Operation 1/f SOCP 0 1 n-1 SOCP tSOCW tSOCW SOX tSOX SO(1) tSOHZ tSOLZ tSOPD SO(2) 2751 drw06 NOTES: 1. This timing applies to the Active Device in Width Expansion Mode. 2. This timing applies to Single Device Mode at Empty Boundary (EF = LOW) and the Next Active Device in Width Expansion Mode. Figure 3. Read Operation LAST WRITE IGNORED WRITE FIRST READ 0 1 ADDITIONAL READS n-1 0 1 FIRST WRITE n-1 SOCP W tSOCFF t WFF FF 2751 drw07 Figure 4. Full Flag from Last Write to First Read 6 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 LAST READ INDUSTRIAL TEMPERATURE RANGE NO READ FIRST WRITE ADDITIONAL WRITES FIRST READ W 0 1 0 n-1 SOCP 1 n-1 (1) tSOCEF tWEF EF t SOPD VALID SO VALID 2751 drw08 NOTE: 1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH. Figure 5. Empty Flag from Last Read to First Write DATAIN W tSOCEF tWEF EF tREFSO SOCP 0 1 n-1 (1) tSOLZ tSOPD SO NOTE: 1. SOCP should not be clocked until EF goes HIGH. 2751 drw09 Figure 6. Empty Boundary Condition Timing 0 1 n-1 SOCP tSOCFF tWFF FF tWPF W tDS tDH DATA IN VALID DATA IN tSOPD SO DATA OUT VALID Figure 7. Full Boundary Condition Timing 7 2751 drw10 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE W HALF-FULL (1/2) HF HALF-FULL HALF-FULL +1 tWF tSOCF tWF tSOCF SOCP AEF 7/8 FULL AEF ALMOST-EMPTY (1/8 FULL-1) 7/8 FULL ALMOST-FULL (7/8 FULL + 1) ALMOST-EMPTY (1/8 FULL-1) 1/8 FULL 2751 drw11 Figure 8. Half Full, Almost Full and Almost Empty Timings tRTC tRT RT tRTS tRTR 0 1 SOCP W tRTS FLAG VALID EF, AEF, HF, FF 2751 drw12 NOTE: 1. EF, AEF, HF and FF may change status during Retransmit, but flags will be valid at tRTC. Figure 9. Retransmit WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION W LAST LAST -1 0 1 0 tXOL tXOH 1 SOCP tXOL tXOH 2751 drw13 XO Figure 10. Expansion-Out 8 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE tXIR tXI XI Write to first physical location tXIS W Read from first physical location tXIS SOCP 2751 drw14 Figure 11. Expansion-In OPERATING CONFIGURATIONS Q8) go LOW and a new serial word is started. The Data Set lines then go HIGH on the equivalent SOCP clock pulse. This continues until the Q line connected to NR goes HIGH completing the serial word. The cycle is then repeated with the next LOW-to-HIGH transition of SOCP. SINGLE DEVICE CONFIGURATION In the standalone case, the SOX line is tied HIGH and not used. On the first LOW-to-HIGH of the SOCP clock, all of the Data Set lines (Q4, Q6, Q7, PARALLEL DATA IN D0-7 SOCP SERIAL OUTPUT CLOCK SOX VCC XI NR 0 1 2 3 4 5 SERIAL DATA OUTPUT SO 6 7 GND Q6 Q7 Q8 Q4 0 1 2 3 4 5 6 7 0 SOCP Q4 Q6 Q7 NR 2751 drw15 Figure 12. Eight-Bit Word Single Device Configuration TRUTH TABLES TABLE 1 RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE Inputs Internal Status Outputs RS FL/RT XI Read Pointer Write Pointer AEF, EF FF HF Reset 0 X 0 Location Zero Location Zero 0 1 1 Retransmit Read/Write 1 1 0 1 0 0 Location Zero Increment(1) Unchanged Increment(1) X X X X X X Mode NOTE: 1. Pointer will increment if appropriate flag is HIGH. 9 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE WIDTH EXPANSION CONFIGURATION In the cascaded case, word widths of more than 9 bits can be achieved by using more than one device. By tying the SOX line of the least significant device HIGH and the SOX of the subsequent devices to the appropriate Data Set lines of the previous devices, a cascaded serial word is achieved. On the first LOW-to-HIGH clock edge of SOCP, all lines go LOW. Just as in the standalone case, on each corresponding clock cycle, the equivalent Data Set line goes HIGH in order of least to most significant. When the Data Set line which is connected to the SOX input of the next device goes HIGH, the D0 of that device goes HIGH, the cascading from one device to the next. The Data Set line of the most significant bit programs the serial word width by being connected to all NR inputs. The Serial Data Output (SO) of each device in the serial word must be tied together. Since the SO pin is three stated, only the device which is currently shifting out is enabled and driving the 1-bit-bus. PARALLEL DATA IN 16-BITS WIDE 9 GND XI D0-8 SO SOCP VCC FIFO #1 SOCP SOX 1 FIFO #2 SOX NR 0 GND XI D0-6 SO SERIAL OUTPUT CLOCK 7 SERIAL DATA OUTPUT 7 NR Q8 8 9 10 14 15 Q6 0 SOCP Q 8 OF FIFO #1 AND SOX OF FIFO #2 Q6 OF FIFO #2 AND NR OF FIFO #1 AND FIFO #2 2751 drw16 Figure 13. Width Expansion for 16-bit Parallel Data In. The Parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2. 10 IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO 2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the OR-ing of all EFs and OR-ing of all FFs (i.e., all must be set to generate the correct composite FF or EF). 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion mode. DEPTH EXPANSION (DAISY CHAIN) MODE The IDT72131/72141 can be easily adapted to applications where the requirements are for greater than 2,048/4,096 words. Figure 14 demonstrates Depth Expansion using three IDT72131/72141. Any depth can be attained by adding additional IDT72131/72141 operates in the Depth Expansion configuration when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. D0-7 XI FL/RT SOX D0-7 FIFO #1 IDT72141 SO W SOCP W NR XO Q7 XI D0-7 VCC SOCP VCC FIFO #2 IDT72141 FL/RT SOX SO W SOCP NR XO Q7 XI D0-7 VCC SO VCC FIFO #3 IDT72141 FL/RT SOX SO W NR XO SOCP Q7 VCC 2751 drw17 Figure 14. A 12K x 8 Parallel-In Serial-Out FIFO TABLE 2 RESET AND FIRST LOAD TRUTH TABLE DEPTH EXPANSION/COMPOUND EXPANSION MODE Inputs Internal Status Outputs RS FL XI Read Pointer Write Pointer EF FF Reset-First Device 0 0 (1) Location Zero Location Zero 0 1 Reset-All Other Devices 0 1 (1) Location Zero Location Zero 0 1 Read/Write 1 X (1) X X X X Mode NOTES: 1. XI is connected to XO of previous device. 2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input. 11 ORDERING INFORMATION IDT XXXXX X Device Type Power XXX Speed X Package X Process/ Temperature Range Blank Industrial (-40C to +85C) P Plastic DIP (P28-1) 35 50 (50MHz serial shift rate) (40MHz serial shift rate) L Low Power 72131 72141 2,048 x 9-Bit Parallel-Serial FIFO 4,096 x 9-Bit Parallel-Serial FIFO Parallel Access Time (tA) 2751 drw18 DATASHEET DOCUMENT HISTORY 02/11/2002 pg. 3. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 12 for TECH SUPPORT: e-mail: FIFOhelp@idt.com Phone: (408) 330-1753