1FEBRUARY 2002
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9
IDT72131
IDT72141
DSC-2751/1
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
FEATURES:
•35ns parallel port access time, 45ns cycle time
•50MHz serial port shift rate
•Expandable in depth and width with no external components
•Programmable word lengths including 7-9, 16-18, 32-36 bit using
Flexishift serial output without using any additional components
•Multiple status flags: Full, Almost-Full (1/8 from full), Half-Full,
Almost- Empty (1/8 from empty), and Empty
•Asynchronous and simultaneous read and write operations
•Dual-Port zero fall-through architecture
•Retransmit capability in single device mode
•Produced with high-performance, low power CMOS technology
•Available in 28-pin plastic DIP
•Industrial temperature range (–40°C to +85°C)
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION
DESCRIPTION:
The IDT72131/72141 are high-speed, low power parallel-to-serial FIFOs.
These FIFOs are ideally suited to serial communications applications, tape/
disk controllers, and local area networks (LANs). These devices can be
configured with the IDTs serial-to-parallel FIFOs (IDT72132/72142) for
bidirectional serial data buffering.
The FIFO has a 9-bit parallel input port and a serial output port. Wider
and deeper parallel-to-serial data buffers can be built using multiple
IDT72131/72141 chips. IDTs unique Flexishift serial expansion logic (SOX,
NR) makes width expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16, and 32 bits.
These devices can also be directly connected for depth expansion.
Five flags are provided to monitor the FIFO. The full and empty flags
prevent any FIFO data overflow or underflow conditions. The Almost-Full
(7/8), Half-Full, and Almost-Empty (1/8) flags signal memory utilization
within the FIFO.
The IDT72131/72141 is fabricated using IDTs high-speed submicron
CMOS technology.
2751 drw01
D
0
-D
8
RAM ARRAY
2,048 x 9
4,096 x 9
WRITE
POINTER NEXT READ
POINTER
FLAG
LOGIC
EF
AEF
/HF
FF
NR
W
RESET LOGIC
RS
EXPANSION
LOGIC
XI
FL/RT
XO/SERIAL OUTPUT
CIRCUITRY
SOCP
SOX
SO
Q
4
Q
6
Q
7
Q
8
5
6
7
8
9
10
11
12
FF
W
D
4
D
3
1
2
3
4
26
25
24
23
22
21
20
19
Vcc
18
17
16
15
D
2
D
1
XI
SOX
FL/RT
RS
EF
XO/HFSOCP
SO
AEF
GND
13
14
28
27
Q
4
GND NR
2751 drw02
D
0
D
5
D
6
D
7
D
8
Q
7
Q
8
Q
6
PLASTIC DIP (P28-1, order code: P)
TOP VIEW
2
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
Symbol Name I/O Description
D0–D8Inputs I Data inputs for 9-bit wide data.
RS Reset I When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM array. HF
and FF go HIGH, and AEF and EF go LOW. A reset is required before an initial WRITE after power-up.
W must be HIGH and SOCP must be LOW during RS cycle.
WWrite I A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold
times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
SOCP Serial Output I A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth
Clock and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
NR Next Read I To program the Serial Out data word width , connect NR with one of the Data Set pins (Q4, Q6, Q7 and Q8).
For example, NR - Q7 programs for a 8-bit Serial Out word width.
FL/RT First Load/ I This is a dual purpose input. In the single device configuration (XI grounded), activating retransmit (FL/RT-
Retransmit LOW) will set the internal READ pointer to the first location. There is no effect on the WRITE pointer. W must
be high and SOCP must be low before setting FL/RT LOW. Retransmit is not compatible with depth
expansion. In the depth expansion configuration, FL/RT grounded indicates the first activated device.
XI Expansion In I In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion, XI is
connected to XO (expansion out) of the previous device.
SOX Serial Output I In the Serial Output Expansion mode, the SOX pin of the least significant device is tied HIGH. The SOX pin
Expansion of all other devices is connected to the Q8 pin of the previous device. Data is then clocked out least significant
bit first. For single device operation, SOX is tied HIGH.
SO Serial Output O Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first. In the Serial
Width Expansion mode the SO pins are tied together and each SO pin is tristated at the end of the byte.
FF Full Flag O When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH, the
device is not full.
EF Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the
device is not empty. See the description on page 6 for more details.
AEF Almost-Empty/ O When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH, the device
Almost-Full Flag is greater than 1/8 full, but less than 7/8 full.
XO/HF Expansion Out/ O This is a dual-purpose output. In the single device configuration (XI grounded), the device is more than half
Half-Full Flag full when HF is LOW. In the depth expansion configuration (XO connected to XI of the next device), a pulse
is sent from XO to XI when the last location in the RAM array is filled.
Q4, Q 6, Data Set O The appropriate Data Set pin (Q4, Q6, Q7 and Q8) is connected to NR to program the Serial Out data word
Q7 and Q8width. For example: Q6 - NR programs a 7-bit word width, Q8 - NR programs a 9-bit word width, etc.
VCC Power Supply Single Power Supply of 5V.
GND Ground Single ground at 0V.
PIN DESCRIPTIONS
Number of Words in FIFO
IDT72131 IDT72141 FF AEF HF EF
0 0 HL HL
1-255 1-511 H L H H
256-1,024 512-2,048 H H H H
1,025-1,792 2,049-3,584 H H L H
1,793-2,047 3,585-4,095 H L L H
2,048 4,096 L L L H
STATUS FLAGS
3
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial Unit
VTERM Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TSTG Storage –55 to +125 °C
Temperature
IOUT DC Output Current –50 to +50 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Commercial Supply 4.5 5.0 5.5 V
Voltage
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.0 — — V
Commercial
VIL(1) Input Low Voltage — — 0.8 V
TAOperating Temperature -40 — 85 °C
Industrial
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C) IDT72131
IDT72141
Industrial
Symbol Parameter Min. Typ. Max. Unit
IIL(1) Input Leakage Current –1 — 1 µA
(Any Input)
IOL(2) Output Leakage Current –10 — 10 µA
VOH Output Logic "1" Voltage, 2.4 — — V
IOUT = –2mA
VOL Output Logic "0" Voltage — — 0.4 V
IOUT = 8mA
ICC1(3) Active Power Supply Current — 90 140 mA
ICC2(3,4) Standby Current — 8 12 mA
(W = RS = FL/RT = VIH; SOCP = VIL)
ICC3(3,4) Power Down Current — — 2 mA
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 10 pF
COUT Output Capacitance VOUT = 0V 12 pF
NOTE:
1. Characterized values, not currently tested.
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. SOCP ≤ VIL, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RS = FL/RT = W = VCC -0.2V; SOCP ≤ 0.2V; all other inputs = VCC - 0.2V or GND + 0.2V, which toggle at 20 MHz.
4
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
Industrial
IDT72131L35 IDT72131L50
IDT72141L35 IDT72141L50
Symbol Parameter Min. Max. Min. Max. Unit
tSParallel Shift Frequency — 22.2 — 15 MHz
tSOCP Serial-Out Shift Frequency — 50 — 40 MHz
PARALLEL INPUT TIMINGS
tDS Data Set-up Time 18 — 30 — ns
tDH Data Hold Time 0 — 5 — ns
tWC Write Cycle Time 45 — 65 — ns
tWPW Write Pulse Width 35 — 50 — n s
tWR Write Recovery Time 10 — 15 — ns
tWEF Write High to EF HIGH — 30 — 45 ns
tWFF Write Low to FF LOW — 30 — 45 ns
tWF Write Low to Transitioning HF, AEF —45—65ns
tWPF Write Pulse Width After FF HIGH 35 — 50 — ns
SERIAL OUTPUT TIMINGS
tSOHZ SOCP Rising Edge to SO at High-Z(1) 516526ns
tSOLZ SOCP Rising Edge to SO at Low-Z(1) 522522ns
tSOPD SOCP Rising Edge to Valid Data on SO — 18 — 18 ns
tSOX SOX Set-up Time to SOCP Rising Edge 5 — 5 — ns
tSOCW Serial In Clock Width HIGH/LOW 8 — 10 — ns
tSOCEF SOCP Rising Edge (Bit 0 - Last Word) to EF LOW — 20 — 25 ns
tSOCFF SOCP Rising Edge to FF HIGH — 30 — 40 ns
tSOCF SOCP Rising Edge to HF, AEF, HIGH — 30 — 40 ns
tREFSO Recovery Time SOCP After EF HIGH 35 — 50 — ns
RESET TIMINGS
tRSC Reset Cycle Time 45 — 65 — ns
tRS Reset Pulse Width 35 — 50 — ns
tRSS Reset Set-up Time 35 — 50 — ns
tRSR Reset Recovery Time 10 — 15 — ns
tRSF1 Reset to EF and AEF LOW — 45 — 65 ns
tRSF2 Reset to HF and FF HIGH — 45 — 65 ns
tRSQL Reset to Q LOW 20 — 35 — ns
tRSQH Reset to Q HIGH 20 — 35 — ns
RETRANSMIT TIMINGS
tRTC Retransmit Cycle Time 45 — 65 — ns
tRT Retransmit Pulse Width 35 — 50 — ns
tRTS Retransmit Set-up Time 35 — 50 — ns
tRTR Retransmit Recovery Time 10 — 15 — ns
DEPTH EXPANSION MODE TIMINGS
tXOL Read/Write to XO LOW — 35 — 50 ns
tXOH Read/Write to XO HIGH — 35 — 50 ns
tXI XI Pulse Width 35 — 50 — ns
tXIR XI Recovery Time 10 — 10 — ns
tXIS XI Set-up Time 15 — 15 — ns
NOTE:
1. Guaranteed by design minimum times, not tested.
5
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure A
or equivalent circuit
SERIAL DATA OUTPUT
The serial data is output on the SO pin. The data is clocked out on the
rising edge of SOCP providing the Empty Flag (EF) is not asserted. If the
Empty Flag is asserted then the next data word is inhibited from moving to
the output register and being clocked out by SOCP. NOTE: SOCP should
not be clocked once the last bit of the last word has been clocked out. If it
is, then two things will occur. One, the SO pin will go High-Z and two, SOCP
will be out of sync with Next Read (NR).
The serial word is shifted out Least Significant Bit first, that is the first bit
will be D0, then D1 and so on up to the serial word width. The serial word
width must be programmed by connecting the appropriate Data Set line
(Q4, Q6, Q7 or Q8) to the NR input. The Data Set lines are taps off a digital
delay line. Selecting one of these taps, programs the width of the serial word
to be read and shifted out.
FUNCTIONAL DESCRIPTION
PARALLEL DATA INPUT
The data is written into the FIFO in parallel through the D0-8 input data
lines. A write cycle is initiated on the falling edge of the Write (W) signal
provided the Full Flag (FF) is not asserted. If the W signal changes from
HIGH-to-LOW and the Full-Flag (FF) is already set, the write line is inhibited
internally from incrementing the write pointer and no write operation occurs.
Data set-up and hold times must be met with respect to the rising edge
of Write. The data is written to the RAM at the write pointer. On the rising
edge of W, the write pointer is incremented. Write operations can occur
simultaneously or asynchronously with read operations.
*Including jig and scope capacitances
Figure A. Output Load
1.1KΩ
30pF*
680Ω
5V
D.U.T.
2751 drw03
Figure 1. Reset
2751 drw04
W
RS
AEF, EF
HF, FF
t
RSC
t
RS
t
RSS
t
RSR
t
RSF1
t
RSF2
t
RSS
t
RSR
t
RSQH
t
RSQL
SOCP
Q
4
, Q
6
, Q
7
, Q
8
6
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
2751 drw05
W
D
0-8
t
WR
t
DH
t
WC
t
WPW
t
DS
2751 drw06
SOCP
SOX
SO
(1)
SO
(2)
1/f
SOCP
0 1 n - 1
t
SOX
t
SOCW
t
SOCW
t
SOHZ
t
SOLZ
t
SOPD
Figure 4. Full Flag from Last Write to First Read
2751 drw07
SOCP
t
SOCFF
LAST WRITE IGNORED
WRITE FIRST READ ADDITIONAL
READS FIRST WRITE
0 1 n - 1 0 1 n - 1
t
WFF
W
FF
NOTES:
1. This timing applies to the Active Device in Width Expansion Mode.
2. This timing applies to Single Device Mode at Empty Boundary (EF = LOW) and the Next Active Device in Width Expansion Mode.
Figure 3. Read Operation
Figure 2. Write Operation
7
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
NOTE:
1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
2751 drw08
SOCP
t
WEF
LAST READ NO READ FIRST WRITE ADDITIONAL
WRITES FIRST READ
0 1 n - 1 0 1 n - 1
W
EF
t
SOPD
SO VALID VALID
(1)
t
SOCEF
2751 drw09
SOCP
t
WEF
0 1 n - 1
W
EF
SO
t
REFSO
DATA
IN
(1)
t
SOLZ
t
SOPD
t
SOCEF
NOTE:
1. SOCP should not be clocked until EF goes HIGH.
Figure 6. Empty Boundary Condition Timing
Figure 5. Empty Flag from Last Read to First Write
Figure 7. Full Boundary Condition Timing
2751 drw10
SOCP
0 1 n - 1
W
FF
SO
DATA
IN
t
WFF
t
WPF
DATA
IN
VALID
DATA
OUT
VALID
t
DS
t
DH
t
SOPD
t
SOCFF
8
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
2751 drw11
SOCP
W
HF
AEF
HALF-FULL (1/2)
7/8 FULL
AEF ALMOST-EMPTY
(1/8 FULL-1) 1/8 FULL
ALMOST-FULL (7/8 FULL + 1)
t
SOCF
t
SOCF
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
HALF-FULL
HALF-FULL +1
t
WF
t
WF
Figure 8. Half Full, Almost Full and Almost Empty Timings
Figure 10. Expansion-Out
NOTE:
1. EF, AEF, HF and FF may change status during Retransmit, but flags will be valid at tRTC.
Figure 9. Retransmit
2751 drw12
W
SOCP
RT
EF, AEF, HF, FF
t
RTC
t
RT
t
RTS
t
RTR
t
RTS
FLAG VALID
01
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SOCP
101
W
XO
0
LAST
LAST -1
WRITE TO LAST PHYSICAL LOCATION READ FROM LAST
PHYSICAL LOCATION
t
XOH
t
XOL
t
XOH
t
XOL
9
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
2751 drw14
SOCP
W
XI
t
XI
t
XIR
t
XIS
t
XIS
Write to first
physical location Read from first
physical location
Figure 11. Expansion-In
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
In the standalone case, the SOX line is tied HIGH and not used. On the
first LOW-to-HIGH of the SOCP clock, all of the Data Set lines (Q4, Q6, Q7,
Q8) go LOW and a new serial word is started. The Data Set lines then go
HIGH on the equivalent SOCP clock pulse. This continues until the Q line
connected to NR goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SOCP.
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SOCP
NR
V
CC
01234567012345670
Q
4
Q
6
Q
7
SOCP
SOX
SERIAL OUTPUT CLOCK SO
XI
SERIAL DATA OUTPUT
GND
PARALLEL DATA IN
D
0-7
NR Q
4
Q
6
Q
7
Q
8
Figure 12. Eight-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1 RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Internal Status Outputs
Mode RS FL/RT XI Read Pointer Write Pointer AEF, EF FF HF
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment(1) Increment(1) XXX
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
10
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
WIDTH EXPANSION CONFIGURATION
In the cascaded case, word widths of more than 9 bits can be achieved
by using more than one device. By tying the SOX line of the least significant
device HIGH and the SOX of the subsequent devices to the appropriate
Data Set lines of the previous devices, a cascaded serial word is achieved.
On the first LOW-to-HIGH clock edge of SOCP, all lines go LOW. Just
as in the standalone case, on each corresponding clock cycle, the equiva-
lent Data Set line goes HIGH in order of least to most significant. When the
Data Set line which is connected to the SOX input of the next device goes
HIGH, the D0 of that device goes HIGH, the cascading from one device to
the next. The Data Set line of the most significant bit programs the serial
word width by being connected to all NR inputs.
The Serial Data Output (SO) of each device in the serial word must be
tied together. Since the SO pin is three stated, only the device which is
currently shifting out is enabled and driving the 1-bit-bus.
Figure 13. Width Expansion for 16-bit Parallel Data In. The Parallel Data In is tied to D 0-8 of FIFO #1 and D0-6 of FIFO #2.
2751 drw16
SOCP
V
CC
0
Q OF FIFO #1 AND
SOX OF FIFO #2
8
SOCP
SOX
SERIAL OUTPUT CLOCK
XI
SERIAL DATA
OUTPUT
GND
PARALLEL DATA IN
16-BITS WIDE
D
0-8
NR Q
8
SO
FIFO #1 SOCP
SOX
XI
D
0-6
NR Q
6
SO
FIFO #2
GND
17891014150
Q
6
OF FIFO #2 AND
NR OF FIFO #1 AND
FIFO #2
97
11
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9 INDUSTRIAL TEMPERATURE RANGE
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT72131/72141 can be easily adapted to applications where the
requirements are for greater than 2,048/4,096 words. Figure 14 demon-
strates Depth Expansion using three IDT72131/72141. Any depth can be
attained by adding additional IDT72131/72141 operates in the Depth
Expansion configuration when the following conditions are met:
1. The first device must be designated by grounding the First Load (FL)
control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (XI) pin of the next device.
4. External logic is needed to generate a composite Full Flag (FF) and
Empty Flag (EF). This requires the OR-ing of all EFs and OR-ing of all
FFs (i.e., all must be set to generate the correct composite FF or EF).
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available
in the Depth Expansion mode.
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SOCP
W
D
0-7
NR
Q
7
SO
FIFO #1
IDT72141
SOX
FL/RT XI
XO
SOCP
W
D
0-7
NR
Q
7
SO
FIFO #2
IDT72141
SOX
FL/RT
XI
XO
SOCP
W
D
0-7
NR
Q
7
SO
FIFO #3
IDT72141
SOX
FL/RT
XI
XO
V
CC
V
CC
V
CC
D
0-7
W
V
CC
V
CC
SO
SOCP
Figure 14. A 12K x 8 Parallel-In Serial-Out FIFO
TABLE 2 RESET AND FIRST LOAD TRUTH TABLE
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Internal Status Outputs
Mode RS FL XI Read Pointer Write Pointer EF FF
Reset-First 0 0 (1) Location Zero Location Zero 0 1
Device
Reset-All 0 1 (1) Location Zero Location Zero 0 1
Other Devices
Read/Write 1 X (1) X X X X
NOTES:
1. XI is connected to XO of previous device.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input.
CORPORATE HEADQUARTERS for SALES: for TECH SUPPORT:
2975 Stender Way 800-345-7015 or 408-727-6116 e-mail: FIFOhelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 Phone: (408) 330-1753
www.idt.com
12
ORDERING INFORMATION
X
Power XXX
Speed X
Package X
Process/
Temperature
Range
Blank Industrial (-40°C to +85°C)
P Plastic DIP (P28-1)
35
50
L Low Power
XXXXX
Device Type
72131
72141 2,048 x 9-Bit Parallel-Serial FIFO
4,096 x 9-Bit Parallel-Serial FIFO
IDT
Parallel Access Time (t
A
)
2751 drw18
(50MHz serial shift rate)
(40MHz serial shift rate)
DATASHEET DOCUMENT HISTORY
02/11/2002 pg. 3.
