M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 64Mx8 DDR2 SDRAM Features * JEDEC Standard 240-pin Dual In-Line Memory Module * 64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on 64Mx8 DDR2 SDRAM * Performance: clock edge * Write Latency = Read Latency - 1 * Programmable Operation: - Device Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 14/10/1 Addressing (row/column/bank) - 512MB * 14/10/2 Addressing (row/column/bank) - 1GB * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * On Die Termination (ODT) * Gold contacts * SDRAMs in TSOP Package * RoHS Compliance PC2-4200 PC2-5300 Speed Sort Unit 37B 3C 4 5 f CK Clock Frequency 266 333 t CK Clock Cycle 3.75 3 ns f DQ DQ Burst Frequency 533 667 MHz DIMM Latency* MHz * Intended for 266MHz and 333MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8Volt 0.1 * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble * Address and control signals are fully synchronous to positive Description M2Y51264TU88A2G and M2Y1G64TU8HA2G are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as a one-rank 64Mx64 and two ranks 128Mx64 high-speed memory array. Modules use eight 64Mx8 (M2Y51264TU88A2G) and sixteen 64Mx8 (M2Y1G64TU8HA2G) DDR2 SDRAMs in TSOP packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 266MHZ (333MHz) clock speeds and achieves high-speed data transfer rates of up to 533MHz (667MHz). Prior to any access operation, the device latency and burst / length / operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.0 6/2006 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Ordering Information Part Number M2Y51264TU88A2G-37B M2Y1G64TU8HA2G-37B Speed 266MHz (3.75ns @ CL = 4) M2Y51264TU88A2G-3C 333MHz (3ns @ CL = 5) Organization DDR2-533 DDR2-667 PC2-4200 PC2-5300 M2Y1G64TU8HA2G-3C Leads Power Gold 1.8V Note 64Mx64 128Mx64 64Mx64 128Mx64 Pin Description CK0, CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable DQS0-DQS7 Row Address Strobe DM0-DM7 Column Address Strobe , A0-A9, A11-A13 A10/AP BA0, BA1 ODT0, ODT1 NC REV 1.0 6/2006 - Data input/output Bidirectional data strobes Input Data Mask/High Data Strobes Differential data strobes Write Enable VDD Power (1.8V) Chip Selects VREF Ref. Voltage for SSTL_18 inputs Address Inputs VDDSPD Serial EEPROM positive power supply Column Address Input/Auto-precharge VSS Ground SDRAM Bank Address Inputs SCL Serial Presence Detect Clock Input Reset pin SDA Serial Presence Detect Data input/output Active termination control lines SA0-2 Serial Presence Detect Address Inputs No Connect 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin 1 VREF 42 NC 82 VSS 121 VSS 2 VSS 43 NC 83 122 DQ4 3 DQ0 44 VSS 84 DQS4 123 DQ5 4 DQ1 45 NC 85 VSS 124 5 VSS 46 NC 86 DQ34 47 VSS 87 DQ35 DQS0 48 NC 88 8 VSS 49 NC 9 DQ2 50 VSS 10 DQ3 51 VDDQ 91 11 VSS 52 CKE0 92 12 DQ8 53 VDD 93 13 DQ9 54 NC 94 14 VSS 55 NC 56 VDDQ A11 6 7 15 Back Pin Back Pin Back 162 NC 202 DM4 163 VSS 203 NC 164 NC 204 VSS VSS 165 NC 205 DQ38 125 DM0 166 VSS 206 DQ39 126 NC 167 NC 207 VSS VSS 127 VSS 168 NC 208 DQ44 89 DQ40 128 DQ6 169 VSS 209 DQ45 90 DQ41 129 DQ7 170 VDDQ 210 VSS VSS 130 VSS 171 CKE1 211 DM5 131 DQ12 172 VDD 212 NC DQS5 132 DQ13 173 NC 213 VSS VSS 133 VSS 174 NC 214 DQ46 95 DQ42 134 DM1 175 VDDQ 215 DQ47 96 DQ43 135 NC 176 A12 216 VSS 97 VSS 136 VSS 177 A9 217 DQ52 CK1 178 VDD 218 DQ53 179 A8 219 VSS CK2 16 DQS1 57 17 VSS 58 A7 98 DQ48 137 18 NC 59 VDD 99 DQ49 138 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS 142 VSS 183 A1 223 DM6 23 VSS 64 VDD 104 143 DQ20 184 VDD 224 NC 24 DQ16 25 DQ17 65 26 VSS 27 KEY 105 DQS6 144 DQ21 VSS 106 VSS 145 VSS 185 KEY 66 VSS 107 DQ50 146 DM2 186 67 VDD 108 DQ51 147 NC 187 CK0 225 VSS 226 DQ54 227 DQ55 VDD 228 VSS 28 DQS2 68 NC 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS 151 VSS 191 VDDQ 232 DM7 32 VSS 72 VDDQ 113 152 DQ28 192 233 NC 33 DQ24 73 153 DQ29 193 234 VSS 34 DQ25 74 35 VSS 75 36 114 VDDQ 76 DQS7 115 VSS 154 VSS 194 VDDQ 235 DQ62 116 DQ58 155 DM3 195 ODT0 236 DQ63 117 DQ59 156 NC 196 A13 237 VSS 37 DQS3 77 ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 VSS 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 VSS 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 VSS 81 DQ33 161 NC 201 VSS REV 1.0 6/2006 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Input/Output Functional Description Symbol CK0, CK1, CK2 , , Type Polarity Function (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, operation to be executed by the SDRAM. , , , , define the VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. (SSTL) - During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. (SSTL) Active High A0 - A9 A10/AP A11 - A13 DQ0 - DQ63 VDD, VSS Supply DQS0 - DQS7 - (SSTL) DM0 - DM7 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.0 6/2006 Supply Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) REV 1.0 6/2006 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 2 Rank, 64Mx8 DDR2 SDRAMs) / (/ ( ( + / 6 7 + / 6 7 + / 6 7 ( + ++ +/ ++6 +7 +4 +5 4 ( + / 6 7 + / 6 7 / (( ( ( 4 5 + / 6 7 + / - + / 6 7 / / / /+ // //6 /7 5 ( + / 6 7 + / 6 7 - + 6 (6 ( ( 6 7 4 5 ( + / 6 7 + ( /4 /5 -+ -/ -- + / 6 7 + ( + / 6 7 + / 6 7 6 / 7 (+ (7 ( / 6 7 4 5 + + ( + / 6 7 0 + ) ) 8 8 + / 6 7 + 0 0 ( -6 -7 -4 -5 6 6 6 6+ 0 + ( ( ( ( ( ( ( ( ( ) ) 8 8 - ( + / 6 7 + / 6 7 7 - 3 - 3 3 3 3 3 7 4 7 4 - * / !" #$ %& ! ' & $# ) &* " ' & + &" , -. / 0 12 12 2 2 &" , -. - '' '% &" , -. ( REV 1.0 6/2006 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 1 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry SPD Entry Value Byte Description (Hexadecimal) 667 -3C 533 -37B 667 -3C 533 -37B 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 Fundamental Memory Type (FPM, EDO.SRDAM, DDR, 2 DDR2 08 DDR2...) 3 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank, Package and Height 1 rank, Height >30.5mm A0 6 Data Width of This Assembly 64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 DDR2 SDRAM Device Cycle Time at Maximum Support /CAS 9 3ns 3.75ns 30 3D Latency CL=5 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 0.45ns 0.5ns 45 50 11 DIMM Configuration Type (non-parity, parity or ECC) Non Parity/ECC 00 12 Refresh Rate/Type 7.89s/self 82 13 Primary DDRII SDRAM Width x8 08 14 Error Checking DDRII SDRAM Device Width N/A 00 15 Reserved Undefined 00 16 DDR SDRAM Device Attributes: Burst Lengths Supported 4,8 0C DDR SDRAM Device Attributes: Number of Banks on DDRII 17 4 04 SDRAM Device 18 DDR SDRAM Device Attributes: /CAS Latencies Supported 5,4,3 38 19 DIMM Mechanical Characteristics <4.10mm 01 20 DIMM type information Regular UDIMM(133.35mm) 02 21 DDRII SDRAM Modules Attributes Normal DIMM 00 22 DDRII SDRAM Device Attributes: General Support weak driver 03 01 23 Minimum Clock Cycle Time at CL=4 3.75ns 3.75ns 3D 3D 24 Maximum Data Access Time (tAC) from Clock at CL=4 0.5ns 0.5ns 50 50 25 Minimum Clock Cycle Time at CL=3 5.0ns 5.0ns 50 50 26 Maximum Data Access Time (tAC) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15.0ns 3C 30 Minimum Active to Precharge Time (tRAS) 45.0 2D 31 Module Bank Density 512MB 80 32 Address and Command Input Setup Time Before Clock (tIS) 0.2ns 0.25ns 20 25 33 Address and Command Input Hold Time After Clock (tIH) 0.275ns 0.375ns 27 37 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.10ns 10 10 35 Data Input Hold Time After Clock (tDH) 0.175ns 0.225ns 17 22 36 Write recovery time (tWR) 15.0ns 3C 37 Internal write to read command delay (tWTR) 7.5ns 7.5ns 1E 1E 38 Internal Read to Precharge command delay(tRTP) 7.5ns 1E 39 Memory Analysis Probe Characteristics Undefined 00 The number below a decimal 40 Extension of Byte 41 tRC and Byte 42 tRFC 00 point of tRC and tRFC are 0, tRFC is less than 256ns SDRAM Device Minimum Active to Active/Auto-Refresh Time 41 60.0ns 3C (tRC) SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh 42 105ns 69 Command Period (tRFC) 43 SDRAM Device Maximum Cycle Time (tCK max) 8.0ns 80 SDRAM Device Maximum skew between DQS and DQ signals 44 0.24ns 0.30ns 18 1E (tDQS) SDRAM Device Maximum Read Data Hold Skew Factor 45 0.34ns 0.40ns 22 28 (tQHS) 46 PLL Relock Time N/A 00 95 95 Tcasemax 47 52 51 DT4R4W Delta 0.8 0.4 Thermal Resistance of DRAM Package from Top (Case) to 61 /W 48 7A Ambient ( Psi T-A DRAM ) DRAM Case Temperature Rise from Ambient due to 8.8 8.2 49 53 4B Activate-Precharge/Mode Bits (DT0/Mode Bits) DRAM Case Temperature Rise from Ambient due to 5.8 4.6 50 3A 2E Precharge/Quiet Standby(DT2N/DT2Q) REV 1.0 6/2006 Note 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 2 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry SPD Entry Value Byte Description (Hexadecimal) 667 -3C 533 -37B 667 -3C 533 -37B DRAM Case Temperature Rise from Ambient due to 0.585 51 27 Precharge Power-Down(DT2P) DRAM Case Temperature Rise from Ambient due to Active 5.85 4.95 52 27 21 Standby (DT3N) DRAM Case temperature Rise from Ambient due to Active 2.2 1.85 53 2C 25 Power-Down with Fast PDN Exit (DT3Pfast) DRAM Case temperature Rise from Ambient due to Active 0.7 0.575 54 1C 17 Power-Down with Slow PDN Exit (DT3Pslow) DRAM Case Temperature Rise from Ambient due to Page 15.2 10.4 55 Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode 4C 34 Bit) DRAM Case Temperature Rise from Ambient due to Burst 18.5 17.5 56 25 23 Refresh (DT5B) DRAM Case Temperature Rise from Ambient due to Bank 20 18.5 57 28 25 Interleave Reads with Auto-Precharge (DT7) Thermal Resistance of PLL Package from Top (Case) to 58 00 00 00 00 Ambient ( Psi T-A PLL ) Thermal Resistance of Register Package from Top (Case) to 59 00 00 00 00 Ambient ( Psi T-A Register) PLL Case Temperature Rise from Ambient due to PLL Active 60 00 00 00 00 (DT PLL Active) Register Case Temperature Rise from Ambient due to 61 00 00 00 00 Register Active/Mode Bit (DT Register Active/Mode Bit) 62 SPD Reversion 1.2 12 63 Checksum for bytes 0-62 Checksum data 39 37 64-71 Manufacturer's JEDED ID Code 0B Hex bank 3 7F7F7F0B00000000 72 Module Manufacturing Location Manufacturing code -73-91 Module Part Number Module Part Number in ASCII -92-255 Reserved Undefined -Note1: M2Y51264TU88A2G-37B M2Y51264TU88A2G-3C REV 1.0 6/2006 Note 1 4D32593531323634545538384132472D333742 4D32593531323634545538384132472D334320 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description 0 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Bank, Package and Height Data Width of This Assembly Reserved Voltage Interface Level of this Assembly DDR2 SDRAM Device Cycle Time at Maximum Support /CAS Latency CL=5 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 DIMM Configuration Type (non-parity, parity or ECC) Refresh Rate/Type Primary DDRII SDRAM Width Error Checking DDRII SDRAM Device Width Reserved DDR SDRAM Device Attributes: Burst Lengths Supported DDR SDRAM Device Attributes: Number of Banks on DDRII SDRAM Device DDR SDRAM Device Attributes: /CAS Latencies Supported DIMM Mechanical Characteristics DIMM type information DDRII SDRAM Modules Attributes DDRII SDRAM Device Attributes: General Minimum Clock Cycle Time at CL=4 Maximum Data Access Time (tAC) from Clock at CL=4 Minimum Clock Cycle Time at CL=3 Maximum Data Access Time (tAC) from Clock at CL=3 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum Active to Precharge Time (tRAS) Module Bank Density Address and Command Input Setup Time Before Clock (tIS) Address and Command Input Hold Time After Clock (tIH) Data Input Setup Time Before Clock (tDS) Data Input Hold Time After Clock (tDH) Write recovery time (tWR) Internal write to read command delay (tWTR) Internal Read to Precharge command delay(tRTP) Memory Analysis Probe Characteristics 40 Extension of Byte 41 tRC and Byte 42 tRFC 9 10 11 12 13 14 15 16 17 41 42 43 44 45 46 47 48 49 50 51 SDRAM Device Minimum Active to Active/Auto-Refresh Time (tRC) SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) SDRAM Device Maximum Cycle Time (tCK max) SDRAM Device Maximum skew between DQS and DQ signals (tDQS) SDRAM Device Maximum Read Data Hold Skew Factor (tQHS) PLL Relock Time Tcasemax Thermal Resistance of DRAM Package from Top (Case) to Ambient ( Psi T-A DRAM ) DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby(DT2N/DT2Q) DRAM Case Temperature Rise from Ambient due to Precharge Power-Down(DT2P) REV 1.0 6/2006 Serial PD Data Entry (Hexadecimal) 667 -3C 533 -37B 80 08 08 0E 0A A1 40 00 05 667 -3C 533 -37B 3ns 3.75ns 30 0.45ns 0.5ns Non Parity/ECC 7.89s/self x8 N/A Undefined 4,8 45 128 256 DDR2 14 10 2 rank, Height >30.5mm 64 Undefined SSTL_1.8V 3D 00 82 08 00 00 0C 4 04 5,4,3 <4.10mm Regular UDIMM (133.35mm) Normal DIMM Support weak driver 3.75ns 3.75ns 0.5ns 0.5ns 5.0ns 5.0ns 0.6ns 15ns 7.5ns 15.0ns 45.0 512MB 0.2ns 0.25ns 0.275ns 0.375ns 0.10ns 0.10ns 0.175ns 0.225ns 15.0ns 7.5ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 38 01 02 00 03 3D 50 50 20 27 10 17 1E 3C 1E 00 00 3C 105ns 69 0.24ns 0.34ns 3 60 3C 1E 3C 2D 80 60.0ns 8.0ns N/A 61 50 01 3D 50 50 25 37 10 22 1E 80 0.30ns 18 0.40ns 22 1 1E 28 00 52 /W 51 7A 8.8 8.2 53 4B 5.8 4.6 3A 2E 0.585 Note 27 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description 667 -3C 533 -37B DRAM Case Temperature Rise from Ambient due to Active 5.85 4.95 Standby (DT3N) DRAM Case temperature Rise from Ambient due to Active 2.2 1.85 53 Power-Down with Fast PDN Exit (DT3Pfast) DRAM Case temperature Rise from Ambient due to Active 0.7 0.575 54 Power-Down with Slow PDN Exit (DT3Pslow) DRAM Case Temperature Rise from Ambient due to Page 15.2 10.4 55 Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) DRAM Case Temperature Rise from Ambient due to Burst 18.5 17.5 56 Refresh (DT5B) DRAM Case Temperature Rise from Ambient due to Bank 20 18.5 57 Interleave Reads with Auto-Precharge (DT7) Thermal Resistance of PLL Package from Top (Case) to 58 00 00 Ambient ( Psi T-A PLL ) Thermal Resistance of Register Package from Top (Case) to 59 00 00 Ambient ( Psi T-A Register) PLL Case Temperature Rise from Ambient due to PLL Active 60 00 00 (DT PLL Active) Register Case Temperature Rise from Ambient due to Register 61 00 00 Active/Mode Bit (DT Register Active/Mode Bit) 62 SPD Reversion 1.2 63 Checksum for bytes 0-62 Checksum data 64-71 Manufacturer's JEDED ID Code 0B Hex bank 3 72 Module Manufacturing Location Manufacturing code 73-91 Module Part Number Module Part Number in ASCII 92-255 Reserved Undefined Note1: M2Y1G64TU8HA2G-37B 4D325931473634545538484132462D33374220 M2Y1G64TU8HA2G-3C 4D325931473634545538484132472D33432020 52 REV 1.0 6/2006 Serial PD Data Entry (Hexadecimal) 667 -3C 533 -37B 27 21 2C 25 1C 17 4C 34 25 23 28 25 00 00 00 00 00 00 00 00 12 3A 38 7F7F7F0B00000000 ---- Note 1 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Environmental Requirements Symbol Parameter Rating Units TOPR Operating Temperature (ambient) 0 to 55 C HOPR Operating Humidity (relative) 10 to 90 % TSTG Storage Temperature -50 to 100 C HSTG Storage Humidity (without condensation) Barometric pressure (operating & storage) up to 9850ft. 5 to 95 % 105 to 69 kPa Note: Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Absolute Maximum DC Ratings Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Voltage on VDD pins relative to Vss Rating Units -1.0 to +2.3 V Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V Voltage on VDDL pins relative to Vss -0.5 to +2.3 V Voltage on I/O pins relative to Vss -0.5 to +2.3 V Storage Temperature (Plastic) -55 to +100 C Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage temperature is the case surface temperature on the center/top side of the DRAM. Operating temperature Conditions Symbol TCASE Note: 1. 2. Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 9s DC Electrical Characteristics and Operating Conditions Symbol Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.9 V 1 0 0 V VSS, VSSQ VREF VTT Parameter Supply Voltage, I/O Supply Voltage Input Reference Voltage Termination Voltage 0.49VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 3 Note: 1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However, VDDQ must be less than or equal to VDD under all conditions. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. REV 1.0 6/2006 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM ODT DC Electrical Characteristics Parameter/Condition Symbol Min. Nom. Max. Units Note Rtt effective impedance value for EMRS(A6,A2)=0,1; 75ohm Rtt1(eff) 60 75 90 ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,0; 150ohm Rtt2(eff) 120 150 180 ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,1; 50ohm Rtt3(eff) 40 50 60 ohm 1 Deviation of VM with respect to VDDQ/2 Delta VM -6 +6 % 1 Note1: Test condition for Rtt measurements. Input AC/DC logic level Symbol Parameter VIH (AC) Input High (Logic1) Voltage VIL (AC) Input Low (Logic0) Voltage VIH (DC) Input High (Logic1) Voltage VIL (DC) Input Low (Logic0) Voltage REV 1.0 6/2006 DDR2-533 DDR2-667 Units Min. Max. Min. Max. VREF + 0.250 - VREF + 0.200 - V - VREF 0.250 - VREF 0.200 V VREF + 0.125 VDDQ + 0.3 VREF + 0.125 VDDQ + 0.3 V -0.3 VREF 0.125 -0.3 VREF 0.125 V 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) Symbol PC2-4200 PC2-5300 (-37B) (-3C) Parameter/Condition I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 560 600 I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 640 720 I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 40 40 I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 320 400 I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 240 320 I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 128 152 I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 40 48 I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 336 400 I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 720 1040 I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 760 1120 I DD5B Burst Auto-Refresh Current: tRFC = tRFC (MIN) 1200 1280 I DD5D Distributes Auto-Refresh Current: tRFC = tREFI 48 48 I DD6 Self-Refresh Current: CKE 0.2V 40 40 I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1280 1360 Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 6/2006 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) Symbol PC2-4200 PC2-5300 (-37B) (-3C) Parameter/Condition I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 880 1000 I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 960 1120 I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 80 80 I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 640 800 I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 480 640 I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 256 304 I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 80 96 I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 656 800 I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1040 1440 I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1080 1520 I DD5B Burst Auto-Refresh Current: tRFC = tRFC (MIN) 1520 1680 I DD5D Distributes Auto-Refresh Current: tRFC = tREFI 288 368 I DD6 Self-Refresh Current: CKE 0.2V 80 80 I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1600 1760 Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 6/2006 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol -3C Unit Min. Max. Min. DQ output access time from CK/ -0.5 +0.5 -0.45 +0.45 ns DQS output access time from CK/ -0.45 +0.45 -0.4 +0.4 ns tCH CK high-level width 0.45 0.55 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCH or tCL - tCH or tCL - tCK tCK Clock Cycle Time 3.75 8 3 8 ns tDH DQ and DM input hold time 225 - 175 - ps tDS DQ and DM input setup time 100 - 100 - ps tIPW Input pulse width 0.6 - 0.6 - tCK tDIPW DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK tAC max - tAC tDQSCK Max. tHZ Data-out high-impedance time from CK/ - tAC max ns tLZ(DQ) Data-out low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max ns tLZ(DQS) DQS low-impedance time from CK/ tAC min tAC max ns - 0.30 - tDQSQ Data hold Skew Factor - 0.24 ns 0.4 - 0.34 ns Data output hold time from DQS - tHP tQHS - ns tDQSS Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 tCK tDQSH DQS input high pulse width 0.35 - 0.35 - tCK tDQSL DQS input low pulse width 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - tCK tWPST Write postamble 0.40 0.60 0.40 0.60 tCK tWPRE Write preamble 0.35 - 0.35 - tCK tIH Address and control input hold time 0.375 - 0.275 - ns tIS Address and control input setup time 0.25 - 0.2 - ns tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 tCK tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tIS + tCK + tIH - tIS + tCK + tIH - ns tRFC Refresh to active/Refresh command time tQH REV 1.0 DQS-DQ skew (DQS & associated DQ signals) tAC min tAC max tHP tQHS tQHS 6/2006 -37B Parameter 105 105 Notes ns 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol tREFI tRRD tCCD -37B Parameter Min. -3C Max. Min. Max. Unit Average Periodic Refresh Interval (85C < TCASE : 95C) 3.9 3.9 9s Average Periodic Refresh Interval (0C : TCASE : 85C) 7.8 7.8 9s Active bank A to Active bank B command 7.5 - 2 15 to tWR Write recovery time WR Write recovery time with Auto-Precharge 7.5 - ns - 2 - tCK - 15 - ns tWR/tCK tWR/tCK - WR +tRP - tCK 7.5 - ns ns tDAL Auto precharge write recovery + precharge time WR +tRP tWTR Internal write to read command delay 7.5 - tRTP Internal read to precharge command delay 7.5 - 7.5 - ns Exit self refresh to a Non-read command tRFC +10 - tRFC +10 - ns Exit self refresh to a Read command tXSNR 200 - 200 - tCK Exit precharge power down to any Non- read command 2 - 2 - tCK tXARD Exit active power down to read command 2 - 2 - tCK tXARDS Exit active power down to read command tXSRD tXP Notes 6-AL - 7-AL - tCK tCKE CKE minimum pulse width 3 - 3 - tCK tOIT OCD drive mode output delay 0 12 0 12 ns 2 2 2 tCK ODT tAOND tAON tAONPD tAOFD tAOF ODT turn-on delay 2 ODT turn-on tAC(min) tAC(max) ns 2tCK + 2tCK + t tAC(min) +2 tAC(max) AC(min) tAC(max) +2 +1 +1 ns tAC (min) ODT turn-on (Power down mode) ODT turn-off delay 2.5 ODT turn-off tAC tAC(min) (max) +1 2.5 +0.7 2.5 2.5 tAC(max) tAC(max) t +0.6 AC(min) +0.6 2.5tCK + tAC(min) +2 t AC(max) +1 2.5tCK + tAC(min) +2 tAC(max) +1 tCK ns tAOFPD ODT turn-off (Power down mode) ns tANPD ODT to power down entry latency 3 - 3 - tCK tAXPD ODT power down exit latency 8 - 8 - tCK Speed Grade Definition REV 1.0 6/2006 tRAS Row Active Time 45 70000 45 70000 ns tRCD RAS to CAS delay 15 - 15 - ns tRC Row Cycle Time 60 - 60 - ns tRP Row Precharge Time 15 - 15 - ns 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) 8 + +- 7 /7 57 0 54 0 + 5 74 7 +5/ ; <= / -7 4 5+ - 76 + 7/5 ++ +- - 7, - 7 ) 4 '& + / +4 - -7 0 %& -5 '" @ ( " +5 #*% & % >, -; 6= ? & ' ; %& = Note: Device position is only for reference. REV 1.0 6/2006 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions + 7/5 -7 / +4 - + 5 74 7 +5/ ; <= / -7 (1GB, 2 Rank, 64Mx8 DDR2 SDRAMs) Note: Device position is only for reference. REV 1.0 6/2006 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y51264TU88A2G/ M2Y1G64TU8HA2G 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 05/2006 Preliminary Release. 1.0 06/2006 Official Release. REV 1.0 6/2006 Modification 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.