TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 2010, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•Second-Generation PLD Architecture
•High-Performance Operation:
fmax (External Feedback) . . . 33.3 MHz
Propagation Delay...20 ns Max
•Increased Logic Power − Up to 22 Inputs
and 10 Outputs
•Increased Product Terms − Average of 12
per Output
•Variable Product Term Distribution
Allows More Complex Functions to Be
Implemented
•Each Output Is User Programmable for
Registered or Combinational Operation,
Polarity, and Output Enable Control
•Power-Up Clear on Registered Outputs
•TTL-Level Preload for Improved Testability
•Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
•Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses
•AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
•Dependable Texas Instruments Quality and
Reliability
•Package Options Include Plastic
Dual-In-Line and Chip Carrier Packages
description
The TIBPAL22V10-20M is a programmable array logic device featuring high speed and functional equivalency
when compared to presently available devices. They are implemented with the familiar sum-of-products
(AND-OR) logic structure featuring the new concept “Programmable Output Logic Macrocell”. These
IMPACT-X™ circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-
tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
This device is covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/I
I
I
I
I
I
I
I
I
I
I
GND
VCC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
JT OR W PACKAGE
(TOP VIEW)
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
I
I
I
NC
I
I
I
426
14 15 16 17 18
I
I
GND
NC
I
I/O/Q
I/O/Q
I
I
CLK/I
NC
I/O/Q
I/O/Q
FK PACKAGE
(TOP VIEW)
NC −No internal connection
Pin assignments in operating mode
V
CC
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10-20M offers quick design and development of custom LSI functions with complexities of 500 to
800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a
temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and
10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered
outputs selected as active-high power up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22V10-20M is characterized for operation over the full military temperature range of
−55°C to 125°C.
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
functional block diagram (positive logic)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
10
12
14
EN
16
16
14
12
10
22
22
1
10
&
44 x 132
I/O/Q
I/O/Q
I/O/Q
I/O/Q
EN
EN
EN
EN
EN
EN
EN
EN
EN
10
10
8
8
10
11
CLK/I
I
Set
Reset
1S
R
C1
denotes fused inputs
Output
Logic
Macrocell
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
0 4 8 1216202428
Increments
First
Fuse
Numbers
32 36 40
Macro-
cell
R = 5809
P = 5808
R = 5811
P = 5810
R = 5813
P = 5812
R = 5815
P = 5814
R = 5817
P = 5816
logic symbol (positive logic)
Asynchronous Reset
23
22
21
20
19
1
2
3
4
5
(to all registers)
396
0
440
880
924
1452
1496
2112
2156
2860
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
CLK/I
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
Fuse number = First fuse number + Increment
R = 5819
P = 5818
R = 5821
P = 5820
R = 5823
P = 5822
R = 5825
P = 5824
R = 5827
P = 5826
18
6
7
8
9
10
11
17
16
15
14
Synchronous Set
13
(to all registers)
Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.
2904
3608
3652
4268
4312
4840
4884
5324
5368
5720
5764
I
I
I
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
output logic macrocell diagram
C1
G
0
3
0
1
1
0
3
2
MUX
I = 0
1S
1D
R
MUX
G1
1
1
SS
AR
From Clock Buffer
S1
S0
AR = asynchronous reset
SS = synchronous set
Output Logic Macrocell
Not Recommended For New Designs
FEEDBACK AND OUTPUT CONFIGURATION
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
C1
1S
1D
R
S1 = 0
S0 = 0
C1
1S
1D
R
S1 = 0
S0 = 1
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
S1 = 1
S0 = 0
S1 = 1
S0 = 1
I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT
S1 S0
0 0 Register feedback Registered Active low
01 Register feedback Registered Active high
10 I/O feedback Combinational Active low
1 1 I/O feedback Combinational Active high
0 = unblown fuse, 1 = blown fuse
S1 and S0 are select-function fuses as shown in the output logic macrocell
diagram.
Figure 1. Resultant Macrocell Feedback and Output Logic After Programming
Not Recommended For New Designs
tsu Setup time before clock↑
ns
ns
Pulse durationtw
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −2 mA
IOL Low-level output current 12 mA
Clock high or low 15
Asynchronous Reset high or low 20
Input 17
Feedback 17
Synchronous Preset (active) 17
Asynchronous Reset (inactive) 20
thHold time, input, set, or feedback after clock↑0 ns
TAOperating free-air temperature −55 125 °C
Not Recommended For New Designs
IIL VCC = 5.5 V, VI = 0.4 V mA
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −1.2 V
VOH VCC = 4.5 V, IOH = − 2 mA 2.4 3.5 V
VOL VCC = 4.5 V, IOL = 12 mA 0.25 0.5 V
IOZH VCC = 5.5 V, VO = 2.7 V 0.1 mA
IOZL VCC = 5.5 V, VO = 0.4 V −0.1 mA
IIVCC = 5.5 V, VI = 5.5 V 1 mA
IIH VCC = 5.5 V, VI = 2.7 V 25 μA
CLK −0.2
All others −0.1
IOS‡VCC = 5.5 V, VO = 0.5 V −30 −90 mA
ICC VCC = 5.5 V, VI = GND, Outputs open 200 mA
Cif = 1 MHz, VI = 2 V 5.5 pF
Cof = 1 MHz, VO = 2 V 8 pF
Cclk f = 1 MHz, VCLK = 2 V 7 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN MAX UNIT
fmax§External feedback 33.3 MHz
tpd I, I/O I/O R1 = 390 Ω, 20 ns
tpd I, I/O (reset) QR2 = 750 Ω, 25 ns
tpd CLK Q See Figure 4 15 ns
ten I, I/O I/O, Q 20 ns
tdis I, I/O I/O, Q 20 ns
§fmax (with feedback) = 1
tsu )tpd(CLK to Q).Verification of tsu and tpd(CLK to Q) may be used to verify expected performance.
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
preload procedure for registered outputs (see Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below:
Step 1. With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level
at the output pin.
td
tsu
tw
td
VIHH
VIL
VIL
VOL
VOH
VIH
Pin 13
Pin 1
Registered I/O Input Output
VIH
VIL
Figure 2. Preload Waveforms
NOTES: 2. Pin numbers shown are for the JT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly.
3. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
1.5 V
tsu ‡
tpd †
tw
VOL
VOH
VIL
VIH
5 V
VCC
Active High
Registered Output
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
1.5 V
(600 ns typ, 1000 ns MAX)
State Unknown
1.5 V
State Unknown
†This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡This is the setup time for input or feedback.
Figure 3. Power-Up Reset Waveforms
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
PARAMETER MEASUREMENT INFORMATION
tsu
S1
From Output
Under Test
Test
Point
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
1.5 V
1.5 V
th
1.5 V
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note D)
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
3 V
0
3 V
0
(see Note B)
1.5 V 1.5 V
1.5 V 1.5 V
tw
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C)
1.5 V 1.5 V
3 V
0
(see Note B)
≈ 3.3 V
VOL
VOH
VOH − 0.5 V
≈ 0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
R1
3 V
3 V
0
(see Note B)
0
VOL + 0.5 V
5 V
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf = 2 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13
TYPICAL CHARACTERISTICS
169
140
120
100
−75 −50 −25 0 25 50
Figure 5
Supply Current − mA
180
200
SUPPLY CURRENT
vs
FREE−AIR TEMPERATURE
220
75 100 125
TA − Free−Air Temperature − °C
ICC −
VCC = 4.75 V
VCC = 5 V
VCC = 5.25 V
VCC = 5.5 V
VCC = 4.5 V
tpd −
8
4
2
0
4.5 4.75 5
Figure 6
Propagation Delay − ns
12
14
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
16
5.25 5.5
10
6
VCC − Supply Voltage − V
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
TA = 25 °C
R1 = 300 Ω
R2 = 390 Ω
CL = 50 pF
tPLH (CLK to Q)
10 Outputs Switching
8
4
2
0
−75 −50 −25 0 25 50
Figure 7
Propagation Delay − ns
12
14
PROPAGATION DELAY TIME
vs
FREE−AIR TEMPERATURE
16
75 100 125
10
6
TA − Free−Air Temperature − °C
tpd −
tPLH (CLK to Q)
tPHL (CLK to Q)
tPLH (I, I/O to O, I/O)
tPHL (I, I/O to O, I/O)
VCC = 5 V
R1 = 300 Ω
R2 = 390 Ω
CL = 50 pF
10 Outputs Switching
4
2
0
0 100 200 300 400 500 600
Figure 8
Propagation Delay − ns
6
8
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
10
CL − Load Capacitance − pF
16
14
12
18
20
22
tpd −
tPLH (CLK to Q)
tPHL (CLK to Q)
tPLH (I, I/O to O, I/O)
tPHL (I, I/O to O, I/O)
VCC = 5 V
R1 = 300 Ω
R2 = 390 Ω
CL = 50 pF
2 Outputs Switching
Not Recommended For New Designs
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS012B − JUNE 1990 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
TYPICAL CHARACTERISTICS
TA = 25°C
10
F − Frequency − MHz
30 50
900
950
70
850
100
800
Power Dissipation − mWPD−
POWER DISSIPATION
vs
FREQUENCY
10−BIT COUNTER MODE
1000
TA = 50°C
VCC = 5 V
R1 = 300 Ω
R2 = 390 Ω
CL = 50 pF
TA = 0°C
Figure 9
tpd −
6
4
2
0
1234567
Figure 10
Propagation Delay Time − ns
8
10
Number of Outputs Switching
PROPAGATION DELAY TIME
vs
NUMBER OF OUTOUTS SWITCHING
12
8910
VCC = 5 V
R1 = 300 Ω
R2 = 390 Ω
CL = 50 pF
TA = 25 °C
tPHL (CLK to Q)
tPLH (CLK to Q)
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
Not Recommended For New Designs
PACKAGE OPTION ADDENDUM
www.ti.com 21-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-86053043A NRND LCCC FK 28 1 TBD Call TI Call TI
5962-8605304KA NRND CFP W 24 1 TBD Call TI Call TI
5962-8605304LA NRND CDIP JT 24 1 TBD Call TI Call TI
TIBPAL22V10-20MFKB NRND LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
TIBPAL22V10-20MJTB NRND CDIP JT 24 1 TBD A42 N / A for Pkg Type
TIBPAL22V10-20MWB NRND CFP W 24 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0°–15°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN (6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MCFP007 – OCTOBER 1994
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F24) CERAMIC DUAL FLATPACK
4040180-5/B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
124
0.360 (9,14)
0.240 (6,10)
1312
Base and Seating Plane
30° TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
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