Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 * * * * * * * * * * High-Performance Operation: fmax (External Feedback) . . . 33.3 MHz Propagation Delay . . . 20 ns Max CLK/I I I I I I I I I I I GND Increased Logic Power - Up to 22 Inputs and 10 Outputs Increased Product Terms - Average of 12 per Output Variable Product Term Distribution Allows More Complex Functions to Be Implemented Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control TTL-Level Preload for Improved Testability Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses AC and DC Testing Done at the Factory Utilizing Special Designed-In Test Features I I I NC I I I Dependable Texas Instruments Quality and Reliability Package Options Include Plastic Dual-In-Line and Chip Carrier Packages 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I FK PACKAGE (TOP VIEW) Power-Up Clear on Registered Outputs Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability 1 I I CLK/I NC VCC I/O/Q I/O/Q * JT OR W PACKAGE (TOP VIEW) Second-Generation PLD Architecture 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 I/O/Q I/O/Q I/O/Q NC I/O/Q I/O/Q I/O/Q I I GND NC I I/O/Q I/O/Q * * NC - No internal connection Pin assignments in operating mode description The TIBPAL22V10-20M is a programmable array logic device featuring high speed and functional equivalency when compared to presently available devices. They are implemented with the familiar sum-of-products (AND-OR) logic structure featuring the new concept "Programmable Output Logic Macrocell". These IMPACT-XTM circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms. Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices. This device is covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated. Copyright (c) 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 description (continued) Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on the polarity selected during programming. Output registers can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing. With features such as programmable output logic macrocells and variable product term distribution, the TIBPAL22V10-20M offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs are possible. A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered outputs selected as active-high power up with their outputs low. A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once blown, the verification circuitry is disabled and all other fuses will appear to be open. The TIBPAL22V10-20M is characterized for operation over the full military temperature range of -55C to 125C. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 functional block diagram (positive logic) C1 Set & 1S Reset 44 x 132 8 R 1 Output Logic Macrocell I/O/Q EN 10 I/O/Q 22 CLK/I EN 12 I/O/Q EN 14 I/O/Q EN 16 I/O/Q EN 16 I/O/Q I 11 22 10 EN 14 I/O/Q EN 12 I/O/Q EN 10 I/O/Q EN 8 I/O/Q EN 10 10 10 denotes fused inputs POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 I I I I 5 4 3 2 1 First Fuse Numbers CLK/I 2860 2156 2112 1496 1452 924 880 440 396 0 0 4 8 logic symbol (positive logic) 12 16 20 24 Increments 28 32 36 40 P = 5816 R = 5817 Macrocell P = 5814 R = 5815 Macrocell P = 5812 R = 5813 Macrocell P = 5810 R = 5811 Macrocell P = 5808 R = 5809 Macrocell 19 20 21 22 23 I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Asynchronous Reset (to all registers) TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS Not Recommended For New Designs SRPS012B - JUNE 1990 - REVISED APRIL 2010 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 10 9 8 7 5764 5720 5368 5324 4884 4840 4312 4268 3652 3608 Fuse number = First fuse number + Increment Inside each MACROCELL the "P" fuse is the polarity fuse and the "R" fuse is the register fuse. I I I I I I 6 2904 P = 5826 R = 5827 Macrocell P = 5824 R = 5825 Macrocell P = 5822 R = 5823 Macrocell P = 5820 R = 5821 Macrocell P = 5818 R = 5819 Macrocell 13 14 15 16 17 18 I Synchronous Set (to all registers) I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 5 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 output logic macrocell diagram Output Logic Macrocell MUX 2 AR R I=0 3 1D 0 C1 SS 1 1S 0 From Clock Buffer S0 MUX 1 1 G1 S1 AR = asynchronous reset SS = synchronous set 6 0 1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 G 3 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 R R 1D 1D C1 C1 1S 1S S1 = 0 S0 = 0 S1 = 0 S0 = 1 REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT S1 = 1 S1 = 1 S0 = 0 S0 = 1 I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE FUSE SELECT S1 S0 FEEDBACK AND OUTPUT CONFIGURATION 0 0 Register feedback Registered Active low 0 1 Register feedback Registered Active high 1 0 I/O feedback Combinational Active low 1 1 I/O feedback Combinational Active high 0 = unblown fuse, 1 = blown fuse S1 and S0 are select-function fuses as shown in the output logic macrocell diagram. Figure 1. Resultant Macrocell Feedback and Output Logic After Programming POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions 8 MIN NOM MAX 4.5 5 5.5 UNIT V 5.5 V VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current -2 mA IOL Low-level output current 12 mA tw Pulse duration 2 tsu Setup time before clock th Hold time, input, set, or feedback after clock TA Operating free-air temperature Clock high or low 15 Asynchronous Reset high or low 20 Input 17 Feedback 17 Synchronous Preset (active) 17 Asynchronous Reset (inactive) 20 ns 0 -55 POST OFFICE BOX 655303 ns * DALLAS, TEXAS 75265 ns 125 C Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VIK VCC = 4.5 V, II = - 18 mA VOH VCC = 4.5 V, IOH = - 2 mA VOL VCC = 4.5 V, IOL = 12 mA IOZH VCC = 5.5 V, IOZL II IIH CLK IIL 2.4 TYP MAX UNIT -1.2 V 3.5 V VO = 2.7 V 0.1 mA VCC = 5.5 V, VO = 0.4 V -0.1 mA VCC = 5.5 V, VI = 5.5 V 1 mA VCC = 5.5 V, VI = 2.7 V 25 A VI = 0.4 V IOS VCC = 5.5 V, VO = 0.5 V ICC VCC = 5.5 V, VI = GND, Ci f = 1 MHz, VI = 2 V Co f = 1 MHz, Cclk f = 1 MHz, 0.25 V 0.5 VCC = 5.5 V, All others MIN -0.2 -0.1 -30 Outputs open mA -90 mA 200 mA 5.5 pF VO = 2 V 8 pF VCLK = 2 V 7 pF All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to O avoid test problems caused by test equipment ground degradation. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fmax tpd FROM (INPUT) TO (OUTPUT) External feedback I, I/O I/O TEST CONDITION MIN MAX 33.3 UNIT MHz R1 = 390 , 20 ns tpd I, I/O (reset) Q R2 = 750 , 25 ns tpd CLK Q See Figure 4 15 ns ten I, I/O I/O, Q 20 ns tdis I, I/O I/O, Q 20 ns 1 f .Verification of tsu and tpd(CLK to Q) may be used to verify expected performance. max (with feedback) = t su ) t pd(CLK to Q) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 preload procedure for registered outputs (see Notes 2 and 3) The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below: Step 1. Step 2. Step 3. Step 4. With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Pulse pin 1, clocking in preload data. Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level at the output pin. VIHH Pin 13 tsu VIL td td tw VIH Pin 1 VIL VIH Registered I/O Input VOH Output VIL VOL Figure 2. Preload Waveforms NOTES: 2. Pin numbers shown are for the JT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly. 3. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 power-up reset Following power up, all registers are reset to zero. The output level depends on the polarity selected during programming. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met. VCC 5V 4V tpd (600 ns typ, 1000 ns MAX) Active High Registered Output VOH State Unknown 1.5 V VOL Active Low Registered Output VOH State Unknown 1.5 V VOL tsu VIH CLK 1.5 V 1.5 V VIL tw This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback. Figure 3. Power-Up Reset Waveforms programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 3V High-Level Pulse 1.5 V 1.5 V 0 0 tw th tsu 3V Data Input 1.5 V 1.5 V 0 (see Note B) 3V Low-Level Pulse 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V Input 1.5 V 0 tpd tpd In-Phase Output 1.5 V tpd Out-of-Phase Output (see Note D) 1.5 V Output Control (low-level enabling) VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 1.5 V 0 (see Note B) ten VOH 1.5 V VOL tpd 0 (see Note B) tdis 3.3 V Waveform 1 S1 Closed (see Note C) 1.5 V VOL + 0.5 V VOL tdis ten Waveform 2 S1 Open (see Note C) VOH 1.5 V VOH - 0.5 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. All input pulses have the following characteristics: PRR 10 MHz, tr and tf = 2 ns, duty cycle = 50%. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 4. Load Circuit and Voltage Waveforms 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE PROPAGATION DELAY TIME vs SUPPLY VOLTAGE 16 220 14 200 tPHL (I, I/O to O, I/O) t pd - Propagation Delay - ns I CC - Supply Current - mA 12 VCC = 5.5 V 180 VCC = 5.25 V 169 140 VCC = 5 V VCC = 4.75 V 120 VCC = 4.5 V 100 -75 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C 10 tPLH (I, I/O to O, I/O) 8 tPHL (CLK to Q) 6 tPLH (CLK to Q) TA = 25 C R1 = 300 R2 = 390 CL = 50 pF 10 Outputs Switching 4 2 0 4.5 125 4.75 5 5.25 VCC - Supply Voltage - V Figure 5 Figure 6 PROPAGATION DELAY TIME vs LOAD CAPACITANCE PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 22 16 tPLH (I, I/O to O, I/O) 20 14 t pd - Propagation Delay - ns t pd - Propagation Delay - ns 10 tPLH (I, I/O to O, I/O) 8 tPHL (CLK to Q) 6 tPLH (CLK to Q) 2 0 -75 -50 VCC = 5 V R1 = 300 R2 = 390 CL = 50 pF 10 Outputs Switching -25 0 25 50 75 100 TA - Free-Air Temperature - C tPHL (I, I/O to O, I/O) 18 tPHL (I, I/O to O, I/O) 12 4 5.5 16 14 12 tPHL (CLK to Q) 10 8 tPLH (CLK to Q) 6 VCC = 5 V R1 = 300 R2 = 390 CL = 50 pF 2 Outputs Switching 4 2 0 125 0 100 200 300 400 500 CL - Load Capacitance - pF 600 Figure 8 Figure 7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 Not Recommended For New Designs TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-XTM PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012B - JUNE 1990 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS POWER DISSIPATION vs FREQUENCY 10-BIT COUNTER MODE PROPAGATION DELAY TIME vs NUMBER OF OUTOUTS SWITCHING 1000 12 950 900 TA = 0C 850 TA = 25C TA = 50C 800 10 tPHL (I, I/O to O, I/O) 10 t pd - Propagation Delay Time - ns PD - Power Dissipation - mW VCC = 5 V R1 = 300 R2 = 390 CL = 50 pF 30 50 F - Frequency - MHz 70 100 tPLH (I, I/O to O, I/O) 6 tPLH (CLK to Q) 4 VCC = 5 V R1 = 300 R2 = 390 CL = 50 pF TA = 25 C 2 0 1 2 3 4 5 6 Figure 10 POST OFFICE BOX 655303 7 8 Number of Outputs Switching Figure 9 14 tPHL (CLK to Q) 8 * DALLAS, TEXAS 75265 9 10 PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 5962-86053043A NRND LCCC FK 28 1 TBD Call TI Call TI 5962-8605304KA NRND CFP W 24 1 TBD Call TI Call TI Call TI Call TI 5962-8605304LA NRND CDIP JT 24 1 TBD TIBPAL22V10-20MFKB NRND LCCC FK 28 1 TBD TIBPAL22V10-20MJTB NRND CDIP JT 24 1 TBD A42 N / A for Pkg Type TIBPAL22V10-20MWB NRND CFP W 24 1 TBD A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MCER004A - JANUARY 1995 - REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MCFP007 - OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30 TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD Index point is provided on cap for terminal identification only. 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