SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 HIGH-SPEED DIFFERENTIAL RECEIVER Check for Samples: SN55LVDS33-SP FEATURES 1 * * * * * * * * * * * (1) 400-Mbps Signaling Rate and 200-Mxfr/s Data Transfer Rate (1) Operates With a Single 3.3-V Supply -4 V to 5 V Common-Mode Input Voltage Range Differential Input Thresholds < 50 mV With 50 mV of Hysteresis Over Entire CommonMode Input Voltage Range Complies With TIA/EIA-644 (LVDS) Active Failsafe Assures a High-Level Output With No Input Bus-Pin ESD Protection Exceeds 15-kV HBM Input Remains High-Impedance On Power Down TTL Inputs Are 5-V Tolerant QML-V Qualified, SMD 5962-07248 Military Temperature Range (-55C to 125C) SN55LVDS33W W PACKAGE (TOP VIEW) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). DESCRIPTION/ORDERING INFORMATION These LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option. Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mV over the full input common-mode voltage range. The receivers can withstand 15-kV Human-Body Model (HBM) and 600-V Machine Model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note. The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN55LVDS33 is characterized for operation from -55C to 125C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2012, Texas Instruments Incorporated SN55LVDS33-SP SGLS393C - MARCH 2008 - REVISED MARCH 2012 www.ti.com ORDERING INFORMATION (1) PACKAGE (2) TA -55C to 125C (1) (2) CFP - W ORDERABLE PART NUMBER TOP-SIDE MARKING 5962-0724801VFA 5962-0724801VFA Tube For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Table 1. FUNCTION TABLE (1) SN55LVDS33 DIFFERENTIAL INPUT VID = VA - VB VID -32 mV -100 mV < VID -32 mV VID -100 mV X Open (1) 2 ENABLES OUTPUT G G Y H X H X L H H X ? X L ? H X L X L L L H Z H X H X L H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC Attenuation Network Attenuation Network 1 pF 60 k A Input 200 k 3 pF 250 k 6.5 k Attenuation Network 6.5 k VCC B Input 7V 7V 7V 7V VCC VCC 300 k (G Only) Enable Inputs 100 37 Y Output 7V 7V 300 k (G Only) Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP 3 SN55LVDS33-SP SGLS393C - MARCH 2008 - REVISED MARCH 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Supply voltage range, VCC (2) -0.5 V to +4 V Enables or Y Voltage range -0.5 V to VCC + 4 V A or B -5 V to +6 V Electrostatic discharge A, B, and GND (3) Charged-device mode All pins (4) Class 3, A: 15 kV, B: 500 V 500 V Storage temperature range -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) (4) 260C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3 3.3 3.6 V 2 5 V 0 0.8 V 0.1 3 V VCC Supply voltage VIH High-level input voltage Enables VIL Low-level input voltage Enables |VID| Magnitude of differential input voltage VI or VIC Voltage at any bus terminal (separately or common-mode) -4 5 TA Operating free-air temperature -55 125 4 Submit Documentation Feedback UNIT C Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIT1 Positive-going differential input voltage threshold VIT2 Negative-going differential input voltage threshold (2) VIB = -4 V or 5 V, See Figure 2 -50 VIT3 Differential input failsafe voltage threshold (2) See Table 2 and Figure 5 -32 VID(HYS) Differential input voltage hysteresis, VIT1 - VIT2 VOH High-level output voltage IOH = -4 mA VOL Low-level output voltage IOL = 4 mA ICC Input current (A or B inputs) IIO Differential input current (IIA - IIB) MAX UNIT 50 mV -100 50 G at VCC, No load, Supply current II TYP (1) (2) V 2.4 V 0.4 Steady state G at GND mV 16 25 1.1 6 VI = 0 V, Other input open 25 VI = 2.4 V, Other input open 25 VI = -4 V, Other input open 80 VI = 5 V, Other input open 45 VID = 100 mV, VIC= -4 V or 5 V 5 VA or VB = 0 V or 2.4 V, VCC = 0 V 25 VA or VB = -4 or 5 V, VCC = 0 V 60 V mA A A A II(OFF) Power-off input current (A or B inputs) IIH High-level input current (enables) VIH = 2 V 12 A IIL Low-level input current (enables) VIL = 0.8 V 12 A IOZ High-impedance output current 12 A CI Input capacitance, A or B input to GND (1) (2) -10 VI = 0.4 sin (4E6t) + 0.5 V 5 pF All typical values are at 25C and with a 3.3-V supply. Not production tested but guaranteed to the limit. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP 5 SN55LVDS33-SP SGLS393C - MARCH 2008 - REVISED MARCH 2012 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP (1) TEST CONDITIONS MAX UNIT tPLH(1) Propagation delay time, low-to-high level output tPHL(1) Propagation delay time, high-to-low level output td1 Delay time, failsafe deactivate time (2) td2 Delay time, failsafe activate time (2) tsk(p) Pulse skew (|tPHL(1) - tPLH(1)|) 200 tsk(o) Output skew (3) 150 tsk(pp) Part-to-part skew (4) tr Output signal rise time 0.8 tf Output signal fall time 0.8 tPHZ Propagation delay time, high level-to-high impedance output 5.5 12 ns tPLZ Propagation delay time, low level-to-high impedance output 4.4 12 ns tPZH Propagation delay time, high impedance-to-high level output 3.8 12 ns tPZL Propagation delay time, high impedance-to-low level output 7 12 ns (1) (2) (3) (4) See Figure 3 CL = 10 pF, See Figure 3 and Figure 6 1.8 4 8 ns 1.8 4 8 ns 0.2 See Figure 3 11 ns 2 s ps ps 1.2 See Figure 4 ns ns ns All typical values are at 25C and with a 3.3-V supply. Not production tested but guaranteed to the limit. tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven together. tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. IIA A VO Y VID B (VIA + VIB)/2 VIA VIC IIB VIB VO Figure 1. Voltage and Current Definitions 6 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 1000 100 1000 VIC + - 100 VID 10 pF, 2 Places VO 10 pF VIT1 0V VID -100 mV VO 100 mV VID 0V VIT2 VO NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns. Figure 2. VIT1 and VIT2 Input Voltage Threshold Test Circuit and Definitions Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP 7 SN55LVDS33-SP SGLS393C - MARCH 2008 - REVISED MARCH 2012 www.ti.com VID VIA CL = 10 pF VIB VO VIA 1.4 V VIB 1V 0.4 V VID 0V -0.4 V tPHL tPLH 80% VO 20% VOH 80% 1.4 V VOL 20% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulsewidth = 10 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 3. Timing Test Circuit and Waveforms 8 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 1.2 V B 500 A 10 pF Inputs VO G VTEST G NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. VTEST 2.5 V A 1V 2V 1.4 V 0.8 V G 2V 1.4 V 0.8 V G tPLZ tPZL tPLZ tPZL Y VTEST 2.5 V 1.4 V VOL +0.5 V VOL 0 1.4 V A G 2V 1.4 V 0.8 V G 2V 1.4 V 0.8 V tPHZ tPZH tPHZ tPZH Y VOH VOH -0.5 V 1.4 V 0 Figure 4. Enable/Disable Time Test Circuit and Waveforms Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP 9 SN55LVDS33-SP SGLS393C - MARCH 2008 - REVISED MARCH 2012 www.ti.com Table 2. Receiver Minimum and Maximum VIT3 Input Threshold Test Voltages APPLIED VOLTAGES (1) (1) RESULTANT INPUTS VIA (mV) VIB (mV) VID (mV) VIC (mV) Output -4000 -3900 -100 -3950 L -4000 -3968 -32 -3984 H 4900 5000 -100 4950 L 4968 5000 -32 4984 H These voltages are applied for a minimum of 1.5 s. VIA -100 mV @ 250 KHz VIB VO a) No Failsafe VIA -32 mV @ 250 KHz VIB VO Failsafe Asserted b) Failsafe Asserted Figure 5. VIT3 Failsafe Threshold Test 1.4 V 1V 0.4 V >1.5 s 0V -0.2 V -0.4 V td1 td2 VOH 1.4 V VOL Figure 6. Waveforms for Failsafe Activate and Deactivate 10 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25C VCC = 3.3 V TA = 25C VOH - High-Level Output Voltage - V VOL - Low-Level Output Voltage - V 5 4 3 2 1 0 3 2 1 0 10 0 20 30 40 -40 -30 -20 -10 Figure 7. Figure 8. LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 5 4.5 VCC = 3 V 4 VCC = 3.3 V VCC = 3.6 V 3.5 3 -50 0 50 TA - Free-Air Temperature - C 0 IOH - High-Level Output Current - mA t PHL - High-To-Low Propagation Delay Time - ns t PLH - Low-To-High Propagation Delay Time - ns IOL - Low-Level Output Current - mA 100 5 4.5 VCC = 3 V VCC = 3.3 V 4 VCC = 3.6 V 3.5 3 -50 Figure 9. 0 50 TA - Free-Air Temperature - C 100 Figure 10. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP 11 SN55LVDS33-SP SGLS393C - MARCH 2008 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREQUENCY 140 I CC - Supply Current - mA 120 VCC = 3.3 V 100 80 VCC = 3.6 V 60 VCC = 3 V 40 20 0 0 100 150 200 f - Switching Frequency - MHz Figure 11. 12 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 APPLICATION INFORMATION 0.01 F 1 VCC 16 0.1 F (see Note A) 1B 100 2 3 VCC 4 5 6 1A 4B 4A G 4Y 2Y G 2A 3Y 3A 2B 5V 1N645 (2 places) 15 1Y 100 7 3.6 V 14 100 (see Note B) 13 12 11 See Note C 10 100 8 GND 3B 9 A. Place a 0.1-F Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitor should be located as close as possible to the device terminals. B. The termination resistance value should match the nominal characteristic impedance of the transmission media with 10%. C. Unused enable inputs should be tied to VCC or GND as appropriate. Figure 12. Operation With 5-V Supply RELATED INFORMATION IBIS modeling is available for this device. Contact the local Texas Instruments sales office or the Texas Instruments Web site at www.ti.com for more information. For more application guidelines, see the following documents: * Low-Voltage Differential Signalling Design Notes (SLLA014) * Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038) * Reducing EMI With LVDS (SLLA030) * Slew Rate Control of LVDS Circuits (SLLA034) * Using an LVDS Receiver With RS-422 Data (SLLA031) Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP 13 SN55LVDS33-SP SGLS393C - MARCH 2008 - REVISED MARCH 2012 www.ti.com ACTIVE FAILSAFE FEATURE A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current LVDS failsafe solutions require either external components with subsequent reductions in signal quality or integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the limitations seen in present solutions. A detailed theory of operation is presented in application note, The Active Failsafe Feature of the SN65LVDS32B (SLLA082A). Figure 13 shows one receiver channel with active failsafe. It consists of a main receiver that can respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that form a window comparator. The window comparator has a much slower response than the main receiver and it detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high. Output Buffer Main Receiver + _ A B R Reset Failsafe Timer A > B + 80 mV + _ Failsafe B > A + 80 mV + _ Window Comparator Figure 13. Receiver With Active Failsafe 14 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of choice for system designers. Designers know of the established technology and that it is capable of high-speed data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at the input of the LVDS receiver. Texas Instruments has taken the next step by introducing a wide common-mode LVDS receiver (no divider network required) which can be connected directly to an ECL driver with only the termination bias voltage required for ECL termination (VCC - 2 V). Figure 14 and Figure 15 show the use of an LV/PECL driver driving five meters of CAT-5 cable and being received by Texas Instruments wide common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the characteristic load impedance of 50 . The R2 resistor is a small value and is intended to minimize any possible common-mode current reflections. VCC R1 = 50 R2 = 50 ICC 5 Meters of CAT-5 LV/PECL R3 VEE R3 VB VCC ICC LVDS VB R1 R1 R2 R3 = 240 Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver Figure 15. LV/PECL to Remote SN65LVDS33 at 500 Mbps Receiver Output (CH1) Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP 15 SN55LVDS33-SP SGLS393C - MARCH 2008 - REVISED MARCH 2012 www.ti.com TEST CONDITIONS * * * VCC = 3.3 V TA = 25C (ambient temperature) All four channels switching simultaneously with NRZ data. The scope is pulse-triggered simultaneously with NRZ data. EQUIPMENT * * * Tektronix PS25216 programmable power supply Tektronix HFS 9003 stimulus system Tektronix TDS 784D 4-channel digital phosphor oscilloscope - DPO Tektronix PS25216 Programmable Power Supply Tektronix HFS 9003 Stimulus System Trigger Bench Test Board Tektronix TDS 784D 4-Channel Digital Phosphor Oscilloscope - DPO Figure 16. Equipment Setup 100 Mbit/s 200 Mbit/s Figure 17. Typical Eye Pattern SN65LVDS33 16 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP SN55LVDS33-SP www.ti.com SGLS393C - MARCH 2008 - REVISED MARCH 2012 REVISION HISTORY This errata revision history highlights the technical changes made to the SGLS393 device specific errata to create the SGLS393C revision. Changes from Revision B (February, 2012) to Revision C * Page Deleted Evaluating the LVDS EVM (SLLA033) bullet in Related Information section ....................................................... 13 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS33-SP 17 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2012 PACKAGING INFORMATION Orderable Device 5962-0724801VFA Status (1) ACTIVE Package Type Package Drawing CFP W Pins Package Qty 16 1 Eco Plan TBD (2) Lead/ Ball Finish A42 MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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