NCP1654BD133R2G - ON Semiconductor L.L.C.

July, 2011 − Rev. 4

1Publication Order Number:

NCP1654/D

NCP1654

Power Factor Controller for

Compact and Robust,

Continuous Conduction

Mode Pre-Converters

The NCP1654 is a controller for Continuous Conduction Mode

(CCM) Power Factor Correction step−up pre−converters. It controls

the power switch conduction time (PWM) in a fixed frequency mode

and in dependence on the instantaneous coil current.

Housed in a SO8 package, the circuit minimizes the number of

external components and drastically simplifies the PFC

implementation. It also integrates high safety protection features that

make the NCP1654 a driver for robust and compact PFC stages like

an effective input power runaway clamping circuitry.

Features

•IEC61000−3−2 Compliant

•Average Current Continuous Conduction Mode

•Fast Transient Response

•Very Few External Components

•Very Low Startup Currents (<75 mA)

•Very Low Shutdown Currents (< 400 mA)

•Low Operating Consumption

•±1.5 A Totem Pole Gate Drive

•Accurate Fully Integrated 65/133/200 kHz Oscillator

•Latching PWM for cycle−by−cycle Duty−Cycle Control

•Internally Trimmed Internal Reference

•Undervoltage Lockout with Hysteresis

•Soft−Start for Smoothly Startup Operation

•Shutdown Function

•Pin to Pin Compatible with Industry Standard

•This is a Pb−Free Device

Safety Features

•Inrush Currents Detection

•Overvoltage Protection

•Undervoltage Detection for Open Loop Detection or Shutdown

•Brown−Out Detection

•Soft−Start

•Accurate Overcurrent Limitation

•Overpower Limitation

Typical Applications

•Flat TVs, PC Desktops

•AC Adapters

•White Goods, other Off−line SMPS

PIN CONNECTIONS

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MARKING

DIAGRAM

SO−8

D SUFFIX

CASE 751

Ground 8Driver

Brown−Out

7VCC

6Feedback

5Vcontrol

(Top View)

xx = 65, 133 or 200

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

854Bxx

ALYW

SO−8

(Pb−Free)

Device Package Shipping†

ORDERING INFORMATION

NCP1654BD65R2G 2500 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

SO−8

(Pb−Free)

NCP1654BD133R2G 2500 / Tape &

Reel

SO−8

(Pb−Free)

NCP1654BD200R2G 2500 / Tape &

Reel

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MAXIMUM RATINGS TABLE

Symbol Pin Rating Value Unit

DRV 8 Output Drive Capability − Source

Output Drive Capability − Sink

−1.5

+1.5

VCC 7Power Supply Voltage, VCC pin, continuous voltage −0.3, +20 V

7Transient Power Supply Voltage, duration < 10 ms, IVCC < 10 mA +25 V

Vin 2, 3, 4, 5, 6 Input Voltage −0.3, +10 V

PD(SO)

RqJA(SO)

Power Dissipation and Thermal Characteristics

D suffix, Plastic Package, Case 751

Maximum Power Dissipation @ TA = 70°C

Thermal Resistance Junction−to−Air

450

178

°C/W

TJOperating Junction Temperature Range −40 to +125 °C

TJmax Maximum Junction Temperature 150 °C

TSmax Storage Temperature Range −65 to +150 °C

TLmax Lead Temperature (Soldering, 10 s) 300 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model (HBM) 2000 V per JEDEC standard JESD22, Method A114E

Machine Model (MM) 200 V (except pin#7 which complies 150 V) per JEDEC standard JESD22, Method A115A.

2. This device contains Latch−up Protection and exceeds ±100 mA per JEDEC Standard JESD78.

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TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)

Symbol Rating Min Typ Max Unit

GATE DRIVE SECTION

ROH Source Resistance @ Isource = 100 mA −9.0 20 W

ROL Sink Resistance @ Isink = −100 mA −6.6 18 W

TrGate Drive Voltage Rise Time from 1.5 V to 13.5 V (CL = 2.2 nF) −60 −ns

TfGate Drive Voltage Fall Time from 13.5 V to 1.5 V (CL = 2.2 nF) −40 −ns

REGULATION BLOCK

VREF Voltage Reference 2.425 2.5 2.575 V

IEA Error Amplifier Current Capability −±28 −mA

GEA Error Amplifier Gain 100 200 300 mS

IBpin6 Pin 6 Bias Current @ VFB = VREF −500 −500 nA

Vcontrol

Vcontrol(max)

Vcontrol(min)

DVcontrol

Pin5 Voltage

Maximum Control Voltage @ VFB = 2 V

Minimum Control Voltage @ VFB = 3 V

DVcontrol = Vcontrol(max) − Vcontrol(min)

−

2.7

3.6

0.6

3.0

−

3.3

VOUTL / VREF Ratio (VOUT Low Detect Thresold / VREF) 94 95 96 %

HOUTL / VREF Ratio (VOUT Low Detect Hysteresis / VREF)−0.5 −%

IBOOST Pin 5 Source Current when (VOUT Low Detect) is activated 190 228 260 mA

CURRENT SENSE BLOCK

VSCurrent Sense Pin Offset Voltage, (ICS = 100 mA) −10 −mV

IS(OCP) Overcurrent Protection Threshold 185 200 215 mA

POWER LIMITATION BLOCK

ICS x VBO Overpower Limitation Threshold 200 mVA

ICS(OPL1)

ICS(OPL2)

Overpower Current Threshold (VBO = 0.9 V, VM = 3 V)

Overpower Current Threshold (VBO = 2.67 V, VM = 3 V)

186

222

308

110

PWM BLOCK

Dcycle Duty Cycle Range 0−97 %

OSCILLATOR / RAMP GENERATOR BLOCK

fsw Switching Frequency 65 kHz

133 kHz

200 kHz

120

180

133

200

146

220

kHz

BROWN−OUT DETECTION BLOCK

VBOH Brown−Out Voltage Threshold (rising) 1.22 1.30 1.38 V

VBOL Brown−Out Voltage Threshold (falling) 0.65 0.7 0.75 V

IIB Pin 4 Input Bias Current @ VBO = 1 V −500 −500 nA

CURRENT MODULATION BLOCK

IM1

IM2

IM3

IM4

Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 25 mA)

Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 75 mA, 65 kHz)

Multiplier Output Current (133 kHz, 200 kHz @ 0  125°C)

Multiplier Output Current (133 kHz, 200 kHz @ −40  125°C)

Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 25 mA

Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 75 mA

−

2.1

1.5

−

1.9

5.6

28.1

84.4

−

8.1

8.5

−

3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit charac-

terization has been performed.

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TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)

Symbol UnitMaxTypMinRating

OVERVOLTAGE PROTECTION

VOVP / VREF Ratio (Overvoltage Threshold / VREF) 103 105 107 %

TOVP Propagation Delay (VFB – 107% VREF) to Drive Low −500 −ns

UNDERVOLTAGE PROTECTION / SHUTDOWN

VUVP(on)/VREF UVP Activate Threshold Ratio (TJ = 0°C to +105°C) 4 8 12 %

VUVP(off)/VREF UVP Deactivate Threshold Ratio (TJ = 0°C to +105°C) 6 12 18 %

VUVP(H) UVP Lockout Hysteresis −4−%

TUVP Propagation Delay (VFB < 8% VREF) to Drive Low −500 −ns

THERMAL SHUTDOWN

TSD Thermal Shutdown Threshold 150 − − °C

HSD Thermal Shutdown Hysteresis −30 −°C

VCC UNDERVOLTAGE LOCKOUT SECTION

VCC(on) Start−Up Threshold (Undervoltage Lockout Threshold, VCC rising) 9.6 10.5 11.4 V

VCC(off) Disable Voltage after Turn−On (Undervoltage Lockout Threshold, VCC falling) 8.25 9.0 9.75 V

VCC(H) Undervoltage Lockout Hysteresis 1.0 1.5 −V

DEVICE CONSUMPTION

ISTUP

ICC1

ICC2

ISTDN

Power Supply Current:

Start−Up (@ VCC = 9.4 V)

Operating (@ VCC = 15 V, no load, no switching)

Operating (@ VCC = 15 V, no load, switching)

Shutdown Mode (@ VCC = 15 V and VFB = 0 V)

−

3.7

4.7

300

5.0

6.0

400

3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit charac-

terization has been performed.

NOTE: IM+Ics VBO

4 ǒVcontrol *Vcontrol(min)Ǔ

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DETAILED PIN DESCRIPTIONS

Pin Symbol Name Function

1 GND Ground −

2 Vin Multiplier

Voltage

This pin provides a voltage VM for the PFC duty cycle modulation. The input impedance of the

PFC circuits is proportional to the resistor RM externally connected to this pin. The device op-

erates in average current mode if an external capacitor CM is connected to the pin. Otherwise,

it operates in peak current mode.

3 CS Current Sense

Input

This pin sources a current ICS which is proportional to the inductor current IL. The sense cur-

rent ICS is for overcurrent protection (OCP), overpower limitation (OPL) and PFC duty cycle

modulation. When ICS goes above 200 mA, OCP is activated and the Drive Output is disabled.

4 VBO Brown−Out / In Connect a resistor network among the rectified input voltage, BO pin, and ground. And connect

a capacitor between BO pin and ground. BO pin detects a voltage signal proportional to the

average input voltage.

When VBO goes below VBOL, the circuit that detects too low input voltage conditions (brown−

out), turns off the output driver and keeps it in low state until VBO exceeds VBOH.

This signal which is proportional to the RMS input voltage Vac is also for overpower limitation

(OPL) and PFC duty cycle modulation.

5 Vcontrol Control Voltage /

Soft−Start

The voltage of this pin Vcontrol directly controls the input impedance. This pin is connected to

external type−2 compensation components to limit the Vcontrol bandwidth typically below 20 Hz

to achieve near unity power factor.

The device provides no output when Vcontrol < Vcontrol(min). When it starts operation, the power

increases slowly (soft−start).

6 VFB Feed−Back /

Shutdown

This pin receives a feedback signal VFB that is proportional to the PFC circuits output voltage.

This information is used for both the output regulation, the overvoltage protection (OVP), and

output undervoltage protection (UVP) to protect the system from damage at feedback abnor-

mal situation.

When VFB goes above 105% VREF

, OVP is activated and the Drive Output is disabled.

When VFB goes below 8% VREF

, the device enters a low−consumption shutdown mode.

7 VCC Supply Voltage This pin is the positive supply of the IC. The circuit typically starts to operate when VCC ex-

ceeds 10.5 V and turns off when VCC goes below 9 V. After start−up, the operating range is 9 V

up to 20 V.

8 DRV Drive Output The high current capability of the totem pole gate drive (±1.5 A) makes it suitable to effectively

drive high gate charge power MOSFET.

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105% Vref

8% Vref with 4% Vref

Hysteresis

UVP

OVP

Undervoltage

Lock−Out

Reference

Block

Bias Block

Iref Vdd

Vref

Vcc

DRV

GND

Output

Buffer 8

UVLO

-OTA

±28 mA

Vcontrol

Vref

OPL Vdd

Off

95% Vref

Vdd

Current Mirror

Thermal

Shutdown

Vref

Figure 1. Functional Block Diagram

Ics > 200 mA

Ics

Vdd

C1 S1

Division

65/133/200 kHz

Oscillator

Vref/10% Vref

Vdd

Iref

Im = (Ics*Vbo) / (4*(Vcontrol − Vcontrol(min))

Ics*Vbo > 200 mVA

PWM

Latch

OPL

OCP

Ics Vbo

Fault

OVP

VboH / VboL

VboH = 1.3 V, VboL = 0.7 V

200 mA

Vout Low Detect

Vin

−

Output

Voltage

(VOUT)

EMI

Filter

Input

Iin

LIL

RSENSE

Cbulk

RCS

RboU

RfbL

RfbU

CBO

RboL

Vcontrol(min)

Cfilter

Soft Start

Vramp

UVP BO

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TYPICAL CHARACTERISTICS

Figure 2. Gate Drive Resistance vs.

Temperature

Figure 3. Reference Voltage vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

1251007550250−25−50

2.40

2.45

2.50

2.55

2.60

Figure 4. Source Current Capability of the

Error Amplifier vs. Temperature

Figure 5. Sink Current Capability of the Error

Amplifier vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

−32

−30

−28

−26

−24

−22

−20

Figure 6. Error Amplifier Gain vs. Temperature Figure 7. Feedback Pin Current vs.

Temperature (@Vfb = VREF)

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

100

150

200

250

300

−150

−100

−50

100

150

ROH & ROL, GATE DRIVE

RESISTANCE (W)

VREF (V)

IEA_source (A)

IEA_sink (A)

GEA (mS)

IBpin6 (nA)

ROH

ROL

10075 12550250−25−50

1251007550250−25−50 10075 12550250−25−50

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TYPICAL CHARACTERISTICS

Figure 8. Vcontrol Maximum Voltage vs.

Temperature

Figure 9. Vcontrol Maximum Swing (DVCONTROL)

vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

10075 1255025

0−25

−50

2.7

2.8

2.9

3.0

3.1

3.2

3.3

Figure 10. Ratio (VOUT Low Detect Threshold /

VREF) vs. Temperature

Figure 11. Pin 5 Source Current when (VOUT

Low Detect) is Activated vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1007550 125250−25−50

94.3

94.4

94.5

94.6

94.8

94.9

95.0

95.1

190

200

210

220

230

240

250

260

Figure 12. Over−Current Protection Threshold

vs. Temperature

Figure 13. Over−Power Current Threshold

(@VBO = 0.9 V & Vm = 3 V) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

185

190

195

200

205

210

215

186

206

226

246

266

286

306

VCONTROL(max) (V)

DVCONTROL (V)

VoutL / VREF (%)

IBoost (mA)

IS(OCP) (mA)

ICS(OPL1) (mA)

94.7

10075 12550250−25−50

10075 1255025

0−25

−50 0−25 10075 1255025−50

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TYPICAL CHARACTERISTICS

Figure 14. Over−Power Current Threshold

(@VBO = 2.67 V & Vm = 3 V) vs. Temperature

Figure 15. Maximum Duty Cycle vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−50

100

110

100

Figure 16. Switching Frequency vs.

Temperature (65 kHz Version)

Figure 17. Switching Frequency vs.

Temperature (133 kHz Version)

TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

Figure 18. Switching Frequency vs.

Temperature (200 kHz Version)

ICS(OPL2) (mA)

MAXIMUM DUTY CYCLE (%)

fSW (kHz)

1251007550250−25−50

TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

126

128

130

132

134

136

138

140

fSW (kHz)

TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

180

185

190

195

200

205

210

fSW (kHz)

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TYPICAL CHARACTERISTICS

Figure 19. Brown−Out Voltage Threshold

(Rising) vs. Temperature

Figure 20. Brown−Out Voltage Threshold

(Falling) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

2.58

2.60

2.62

2.64

2.66

Figure 21. Multiplier Output Current (Vcontrol =

VCONTROL(max), Vbo = 0.9 V, ICS = 75 mA) vs.

Temperature

Figure 22. Over Voltage Threshold vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

Figure 23. Ratio (Over Voltage Threshold /

VREF) vs. Temperature

Figure 24. UVP Activate and Deactivate

Threshold Ratio vs. Temperature

VOVP (V)VUVP(on) / VREF and VUVP(off) / VREF (%)

10075 12550250−25−50

103

104

105

106

VOVP / VREF (%)

107

TJ, JUNCTION TEMPERATURE (°C)

2.5

3.5

4.5

5.5

6.5

7.5

Im2 (mA)

1251007550250−25−50

TJ, JUNCTION TEMPERATURE (°C)

0.65

0.70

0.75

VBOL (L)

10075 12550250−25−50

TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

1.20

1.25

1.30

1.35

1.40

VBOH (V)

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TYPICAL CHARACTERISTICS

Figure 25. VCC Start−Up Threshold (VCC

Rising) vs. Temperature

Figure 26. VCC Disable Voltage after Turn−On

(VCC Falling) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−50

200

250

300

350

400

Figure 27. VCC UVLO Hysteresis vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C)

ISTUP (mA)

ISTDN (mA)

OPERATING CURRENT (mA)

1251007550250−25−50

ICC2, No Load, Switching

ICC1, No Load, No Switching

Figure 28. Supply Current in Startup Mode vs.

Temperature

Figure 29. Supply Current in Shutdown Mode

vs. Temperature

Figure 30. Operating Supply Current vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−50

1.0

1.2

1.4

1.6

1.8

2.0

VCC(H) (V)

TJ, JUNCTION TEMPERATURE (°C)

10075 12

50250−25−50

8.3

8.5

8.7

8.9

9.1

9.3

9.5

9.7

VCC(off) (V)

TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−50

9.6

9.8

10.0

10.4

10.6

11.0

11.2

11.4

VCC(on) (V)

10.2

10.8

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Detailed Operating Description

Introduction

The NCP1654 is a PFC driver designed to operate in

fixed frequency, continuous conduction mode. The fixed

frequency operation eases the compliance with EMI

standard and the limitation of the possible radiated noise

that may pollute surrounding systems. In addition,

continuous conduction operation reduces the application

di/dt and their resulting interference. More generally, the

NCP1654 is an ideal candidate in systems where

cost−effectiveness, reliability and high power factor are the

key parameters. It incorporates all the necessary features to

build a compact and rugged PFC stage:

•Compactness and Flexibility: housed in a SO8

package, the NCP1654 requires a minimum of

external components. In particular, the circuit scheme

simplifies the PFC stage design and eliminates the

need for any input voltage sensing. In addition, the

circuit offers some functions like the Brown−Out or

the true power limiting that enable the optimizations

of the PFC design,

•Low Consumption and Shutdown Capability: the

NCP1654 is optimized to exhibit consumption as

small as possible in all operation modes. The

consumed current is particularly reduced during the

start−up phase and in shutdown mode so that the PFC

stage power losses are extremely minimized when the

circuit is disabled. This feature helps meet the more

stringent stand−by low power specifications. Just

ground the Feed−back pin to force the NCP1654 in

shutdown mode,

•Safety Protections: the NCP1654 permanently monitors

the output voltage, the coil current and the die

temperature to protect the system from possible

over−stresses. Integrated protections (Overvoltage

protection, coil current limitation, thermal shutdown...)

make the PFC stage extremely robust and reliable:

−Maximum Current Limit: the circuit permanently

senses the coil current and immediately turns off the

power switch if it is higher than the set current limit.

The NCP1654 also prevents any turn on of the

power switch as long as the coil current is not below

its maximum permissible level. This feature protects

the MOSFET from possible excessive stress that

could result from the switching of a current higher

than the one the power switch is dimensioned for. In

particular, this scheme effectively protects the PFC

stage during the start−up phase when large in−rush

currents charge the output capacitor.

−Undervoltage Protection for Open Loop Protection

or Shut−down: the circuit detects when the

feed−back voltage goes below than about 8% of the

regulation level. In this case, the circuit turns off and

its consumption drops to a very low value. This

feature protects the PFC stage from starting

operation in case of low AC line conditions or in

case of a failure in the feed−back network (i.e. bad

connection).

−Fast Transient Response: given the low bandwidth

of the regulation block, the output voltage of PFC

stages may exhibit excessive over or under−shoots

because of abrupt load or input voltage variations

(e.g. at start up). If the output voltage is too far from

the regulation level:

Overvoltage Protection: NCP1654 turns off the

power switch as soon as Vout exceeds the OVP

threshold (105% of the regulation level). Hence

a cost & size effective bulk capacitor of lower

voltage rating is suitable for this application,

Dynamic Response Enhancer: NCP1654

drastically speeds up the regulation loop by its

internal 200ĂmA enhanced current source when the

output voltage is below 95% of its regulation level.

−Brown−Out Detection: the circuit detects low AC

line conditions and disables the PFC stage in this

case. This protection mainly protects the power

switch from the excessive stress that could damage it

in such conditions,

−Over−Power Limitation: the NCP1654 computes the

maximum permissible current in dependence of the

average input voltage measured by the brown−out

block. It is the second OCP with a threshold that is

line dependent. When the circuit detects an

excessive power transfer, it resets the driver output

immediately,

−Thermal Shutdown: an internal thermal circuitry

disables the circuit gate drive and then keeps the

power switch off when the junction temperature

exceeds 150°C typically. The circuit resumes

operation once the temperature drops below about

120°C (30°C hysteresis),

−Soft Start: Vcontrol is pulled low brown−out detection

activates, or Undervoltage protection activates, and

no drive is provided.

At start up, the “200 mA enhanced current source” is

disabled. So there is only 28 mA to charge the

compensation components, and makes Vcontrol raise

gradually. This is to obtain a slow increasing duty

cycle and hence reduce the voltage and current

stress on the MOSFET. Hence it provides a soft−start

feature.

•Output Stage Totem Pole: the NCP1654 incorporates

a ±1.5A gate driver to efficiently drive TO220 or

TO247 power MOSFETs.

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PRINCIPLE OF NCP1654 SCHEME

CCM PFC Boost

A CCM PFC boost converter is shown in Figure 31. The

input voltage is a rectified 50 ro 60 Hz sinusoidal signal.

The MOSFET is switching at a high frequency (typically

65/133/200 kHz in NCP1654) so that the inductor current

IL basically consists of high and low−frequency

components.

Filter capacitor Cfilter is an essential and very small value

capacitor in order to eliminate the high−frequency

component of the inductor IL. This filter capacitor cannot

be too bulky because it can pollute the power factor by

distorting the rectified sinusoidal input voltage.

Figure 31. CCM PFC Boost Converter

Cbulk

Vin

RSENSE

Cfilter

Iin ILVout

Output

Voltage

PFC Methodology

The NCP1654 uses a proprietary PFC methodology

particularly designed for CCM operation. The PFC

methodology is described in this section.

Figure 32. Inductor Current in CCM

Time

Iin

t1t2

As shown in Figure 32, the inductor current IL in a

switching period T includes a charging phase for duration

t1 and a discharging phase for duration t2. The voltage

conversion ratio is obtained in (Equation 1).

Vout

Vin +t1)t2

t2+T

T*t1

(eq. 1)

Vin +T*t1

TVout

where

Vout is the output voltage of PFC stage,

Vin is the rectified input voltage,

T is the switching period,

t1 is the MOSFET on time, and

t2 is the MOSFET off time.

The input filter capacitor Cfilter and the front−ended EMI

filter absorbs the high−frequency component of inductor

current IL. It makes the input current Iin a low−frequency

signal only of the inductor current.

(eq. 2)

Iin +IL*50

where

Iin is the input AC current.

IL is the inductor current.

IL−50 supposes a 50 Hz operation. The suffix 50 means

it is with a 50 Hz bandwidth of the original IL.

From (Equation 1) and (Equation 2), the input

impedance Zin is formulated.

(eq. 3)

Zin +Vin

Iin +T*t1

Vout

IL*50

where Zin is input impedance.

Power factor is corrected when the input impedance Zin

in (Equation 3) is constant or varies slowly in the 50 or 60

Hz bandwidth.

Figure 33. PFC Duty Modulation and Timing Diagram

Ich

VMVref PFC Modulation

Vramp

Cramp

Clock

Vramp

Vref

VM without

Filtering

Clock

Latch Set

Latch Reset

Output

Inductor

Current

The PFC modulation and timing diagram is shown in

Figure 33. The MOSFET on time t1 is generated by the

intersection of reference voltage VREF and ramp voltage

Vramp. A relationship in (Equation 4) is obtained.

(eq. 4)

Vramp +Vm)Icht1

Cramp +VREF

where

NCP1654

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Vramp is the internal ramp voltage, the positive input of the

PFC modulation comparator,

Vm is the multiplier voltage appearing on Vm pin,

Ich is the internal charging current,

Cramp is the internal ramp capacitor, and

VREF is the internal reference voltage, the negative input of

the PFC modulation comparator.

Ich, Cramp, and VREF also act as the ramp signal of

switching frequency. Hence the charging current Ich is

specially designed as in (Equation 5). The multiplier

voltage Vm is therefore expressed in terms of t1 in

(Equation 6).

(eq. 5)

Ich +CrampVREF

(eq. 6)

Vm+VREF *t1

Cram

CrampVREF

T+VREF

T*t1

From (Equation 3) and (Equation 6), the input impedance

Zin is re−formulated in (Equation 7).

(eq. 7)

Zin +Vm

VREF

Vout

IL*50

Because VREF and Vout are roughly constant versus time,

the multiplier voltage Vm is designed to be proportional to

the IL−50 in order to have a constant Zin for PFC purpose.

It is illustrated in Figure 34.

Figure 34. Multiplier Voltage Timing Diagram

Time

Iin

Vin

It can be seen in the timing diagram in Figure 33 that Vm

originally consists of a switching frequency ripple coming

from the inductor current IL. The duty ratio can be

inaccurately generated due to this ripple. This modulation

is the so−called “peak current mode”. Hence, an external

capacitor CM connected to the multiplier voltage Vm pin is

essential to bypass the high−frequency component of Vm.

The modulation becomes the so−called “average current

mode” with a better accuracy for PFC.

Figure 35. External Connection on the Multiplier

Voltage Pin

PFC Duty

Modulation

Vm+

RMIcsVbo

4(Vcontrol *VCONTROL(min))

RMCM

VmIm

The multiplier voltage Vm is generated according to

(Equation 8).

(eq. 8)

Vm+RMIcsVbo

4(Vcontrol *VCONTROL(min))

Where,

RM is the external multiplier resistor connected to Vm pin,

which is constant.

Vbo is the input voltage signal appearing on the BO pin,

which is proportional to the rms input voltage,

Ics is the sense current proportional to the inductor current

IL as described in (Equation 11).

Vcontrol is the control voltage signal, the output voltage of

Operational Trans−conductance Amplifier (OTA), as

described in (Equation 12).

RM directly limits the maximum input power capability

and hence its value affects the NCP1654 to operate in either

“follower boost mode” or “constant output voltage mode”.

Figure 36. External Connection on the Brown Out Pin

Vbo

RboL

Vin

RboU

CBO +

VboH / VboL

VboH = 1.3 V, VboL = 0.7 V

Refer to Figure 36,

(eq. 9)

Vbo +KBO(Vin)+KBO @22

pVac

(eq. 10)

KBO +RboL

RboU )RboL

where

Vbo is the voltage on BO pin.

KBO is the decay ratio of Vin to Vbo.

<Vin> is the average voltage signal of Vin, the voltage

appearing on Cfilter.

Vac is the RMS input voltage.

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RboL is low side resistor of the dividing resistors between

Vin and BO pin.

RboU is upper side resistor of the dividing resistors between

Vin and BO pin.

Figure 37. Current Sensing

Gnd

RSENSE

RCS

ICS CS

VCS

NCP1654

−

Refer to Figure 37, sense current Ics is proportional to the

inductor current IL as described in (Equation 11). IL

consists of the high−frequency component (that depends on

di/dt or inductor L) and low−frequency component (that is

IL−50).

(eq. 11)

Ics +RSENSE

RCS

where

RSENSE is the sense resistor to sense IL.

RCS is the offset resistor between CS pin and RSENSE.

Figure 38. Vcontrol Low−Pass Filtering

VREF OTA

Vcontrol

±20 mA

Vout

VCONTROL(min)

To Vm Pin

Vfb

RfbL

RfbU

Vin

Refer to Figure 38, the Operational Trans−conductance

Amplifier (OTA) senses Vout via the feedback resistor

dividers, RfbU and RfbL. The OTA constructs a control

voltage, Vcontrol, depending on the output power and hence

Vout. The operating range of Vcontrol is from

VCONTROL(min) to VCONTROL(max). The signal used for

PFC duty modulation is after decreasing a offset voltage,

VCONTROL(min), i.e. Vcontrol−VCONTROL(min).

This control current Icontrol is a roughly constant current

that comes from the PFC output voltage Vout that is a slowly

varying signal. The bandwidth of Icontrol can be

additionally limited by inserting the external type−2

compensation components (that are RZ, CZ, and CP as

shown in Figure 38). It is recommended to limit fcontrol, that

is the bandwidth of Vcontrol (or Icontrol), below 20 Hz

typically to achieve power factor correction purpose.

The transformer of Vout to Vcontrol is as described in

(Equation 12) if CZ is >> CP

. GEA is the error amplifier gain.

Vcontrol

Vout +RfbL @GEARZ

RfbL )RfbU @1)sRZCZ

sRZCZ(1 )sRZCP)(eq. 12)

From (Equation 7) − (Equation 11), the input impedance

Zin is re−formulated in (Equation 13).

Zin +2

ǸRMRSENSEVoutVacKBOIL

2pRCS @(Vcontrol *VCONTROL(min))@VREFIL*50

(eq. 13)

When IL is equal to IL−50, (Equation 13) is re−formulated

in (Equation 14)

Zin +2

ǸRMRSENSEVoutVacKBO

2pRCS @(Vcontrol *VCONTROL(min))@VREF

(eq. 14)

The multiplier capacitor CM is the one to filter the

high−frequency component of the multiplier voltage Vm.

The high−frequency component is basically coming from

the inductor current IL. On the other hand, the filter

capacitor Cfilter similarly removes the high−frequency

component of inductor current IL. If the capacitors CM and

Cfilter match with each other in terms of filtering capability,

IL becomes IL−50. Input impedance Zin is roughly constant

over the bandwidth of 50 or 60 Hz and power factor is

corrected.

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Input and output power (Pin and Pout) are derived in (Equation 15) when the circuit efficiency η is obtained or assumed.

The variable Vac stands for the rms input voltage.

Pin +Vac 2

Zin +

2pRCS @(Vcontrol *VCONTROL(min))@VREF @Vac

ǸRMRSENSEVoutKBO

(eq. 15)

(Vcontrol *VCONTROL(min))Vac

Vout

Pout +hPin +h

2pRCS @(Vcontrol *VCONTROL(min))@VREF @Vac

ǸRMRSENSEVoutKBO

(eq. 16)

(Vcontrol *VCONTROL(min))Vac

Vout

Follower Boost

The “Follower Boost” is an operation mode where the

pre−converter output voltage stabilizes at a level that varies

linearly versus the ac line amplitude. This technique aims

at reducing the gap between the output and input voltages

to optimize the boost efficiency and minimize the cost of

the PFC stage (refer to MC33260 data sheet for more

details at http://www.onsemi.com ).

The NCP1654 operates in follower boost mode when

Vcontrol is constant, i.e. Vcontrol raises to its maximum value

VCONTROL(max). Re−formulate (Equation 16) to become

(Equation 17) and (Equation 18) by replace Vcontrol by

VCONTROL(max). If Vcontrol is constant based on

(Equation 15), for a constant load or power demand the

output voltage Vout of the converter is proportional to the

rms input voltage Vac. It means the output voltage Vout

becomes lower when the rms input voltage Vac becomes

lower. On the other hand, the output voltage Vout becomes

lower when the load or power demand becomes higher.

Pout +h

2pRCS @(VCONTROL(max) *VCONTROL(min))@VREF @Vac

ǸRMRSENSEVoutKBO

(eq. 17)

+h2pRCS @DVCONTROL @VREF @Vac

ǸRMRSENSEVoutKBO

Vout +h2pRCS @DVCONTROL @VREF

ǸRMRSENSEKBO

@Vac

Pout

(eq. 18)

where

VCONTROL(max) is the maximum control voltage.

DVCONTROL is the gap between VCONTROL(max) and

VCONTROL(min).

It is illustrated in Figure 39.

Figure 39. Follower Boost Characteristics

Vout (Traditional Boost)

Vout (Follower Boost)

Vin

Pout

Time

Follower Boost Benefits

The follower boost circuit offers and opportunity to

reduce the output voltage Vout whenever the rms input

voltage Vac is lower or the power demand Pout is higher.

Because of the step−up characteristics of boost converter,

the output voltage Vout will always be higher than the input

voltage Vin even though Vout is reduced in follower boost

operation. As a result, the on time t1 is reduced. Reduction

of on time makes the loss of the inductor and power

MOSFET smaller. Hence, it allows cheaper cost in the

inductor and power MOSFET or allows the circuit

components to operate at a lower stress condition in most

of the time.

Reference Section

The internal reference voltage (VREF) is trimmed to be

±2% accurate over the temperature range (the typical value

is 2.5 V). VREF is the reference used for the regulation.

VREF also serves to build the thresholds of the fast transient

response, Overvoltage (OVP), brown out (BO), and

Undervoltage protections (UVP).

Output Feedback

The output voltage Vout of the PFC circuits is sensed at

Vfb pin via the resistor divider (RfbL and RfbU) as shown in

Figure 38. Vout is regulated as described in (Equation 19).

Vout +VREF

RfbU )RfbL

RfbL

(eq. 19)

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The feedback signal Vfb represents the output voltage

Vout and will be used in the output voltage regulation,

Overvoltage protection (OVP), fast transient response, and

Undervoltage protection (UVP)

Output Voltage Regulation

NCP1654 uses a high gain Operational Trans−

conductance Amplifier (OTA) as error amplifier. Refer to

Figure 38, the output of OTA Vcontrol operating range is

from VCONTROL(min) to VCONTROL(max).

Fast Transient Response

Given the low bandwidth of the regulation block, the

output voltage of PFC stages may exhibit excessive over or

under−shoots because of abrupt load or input voltage

variations (such as start−up duration). As shown in

Figure 40, if the output voltage is out of regulation,

NCP1654 has 2 functions to maintain the output voltage

regulation.

Figure 40. OVP and Fast Transient Response

95%

VREF

OTA

Vcontrol

Vout Low Detect

200 mA

Vdd

±20 mA

105%

VREF

Vout

OVP

Vfb

RfbU

RfbL

CFB

•Overvoltage Protection: When Vfb is higher than

105% of VREF (i.e. Vout > 105% of nominal output

voltage), the Driver output of the device goes low for

protection. The circuit automatically resumes

operation when Vfb becomes lower than 105% of

VREF. If the nominal Vout is set at 390 V, then the

maximum output voltage is 105% of 390 V = 410 V.

Hence a cost & size effective bulk capacitor of lower

voltage rating is suitable for this application,

•Dynamic response enhancer: NCP1654 drastically

speeds up the regulation loop by its internal 200 mA

enhanced current source when the output voltage is

below 95% of its regulation level. Under normal

condition, the maximum sink and source of output

current capability of OTA is around 28 mA. Thanks to

the “Vout low detect” block, when the Vfb is below

95% VREF, an extra 200 mA current source will raise

Vcontrol rapidly. Hence prevent the PFC output from

dropping too low and improve the transient response

performance. The relationship between current

flowing in/out Vcontrol pin and Vfb is as shown in

Figure 41.

It is recommended to add a typical 100 pF capacitor CFB

decoupling capacitor next to feedback pin to prevent from

noise impact.

−250

−200

−150

−100

−50

2 2.2 2.4 2.6 2.8 3

Vfb

Figure 41. Vfb vs. Current Flowing in/out from Vcontrol Pin

No DRV when

Vfb is above

105% VREF

VCONTROL PIN CURRENT (mA)

200 mA raises

Vcontrol rapidly

when Vfb is below

95% VREF

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Soft Start

The block diagram and timing diagram of soft start

function are as shown in Figure 42 and Figure 43. The

device provides no output (or no duty ratio) when the

Vcontrol is lower than VCONTROL(min). Vcontrol is pulled low

when:

•Brown−out, or

•Undervoltage Protection

When the IC recovers from one of the following

conditions; Undervoltage Lockout, Brown−out or

Undervoltage Protection, the 200 mA current source block

keeps off. Hence only the Operating Trans−conductance

Amplifier (OTA) raises the Vcontrol. And Vcontrol rises

slowly. This is to obtain a slow increasing duty cycle and

hence reduce the voltage and current stress on the

MOSFET. A soft−start operation is obtained.

Figure 42. Soft Start Block Diagram

95%

VREF

OTA

Vfb

Vcontrol

Vout Low Detect

200 mA

Vdd

±20 mA

Bias

Vdd Off UVPUVLOBO

UVLOBO

95% VREF

Figure 43. Soft Start Timing Diagram

Period I Period II

UVLO, BO, or UVP

Vdd

Vdd Rising

Vfb

Set

Reset

Vout Low Detect

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Undervoltage Protection (UVP) for Open Loop

Protection or Shutdown

Figure 44. Undervoltage Protection

ISTDN

ICC2

Shutdown Operating

8% VREF 12% VREF

Vfb

As shown in Figure 44, when Vfb is less than 8% of VREF,

the device is shut down and consumes less than 400 mA.

The device automatically starts operation when the output

voltage goes above 12% of VREF. In normal situation of

boost converter configuration, the output voltage Vout is

always greater than the input voltage Vin and the feedback

signal Vfb is always greater than 8% and 12% of VREF to

enable NCP1654 to operate.

This Undervoltage Protection function has 2 purposes.

•Open Loop Protection − Protect the power stage from

damage at feedback loop abnormal, such as Vfb is

shorted to ground or the feedback resistor RfbU is

open.

•Shutdown mode − Disables the PFC stage and forces a

low consumption mode. This feature helps to meet

stringent stand−by specifications. Power Factor being

not necessary in stand−by, the PFC stage is generally

inhibited to save the pre−converter losses. To further

improve the stand−by performance, the PFC controller

should consume minimum current in this mode.

Current Sense

The device senses the inductor current IL by the current

sense scheme in Figure 37. The device maintains the

voltage at CS pin to be zero voltage (i.e., Vcs ≈ 0 V) so that

(Equation 11),

Ics +RSENSE

RCS

IL,

can be formulated.

This scheme has the advantage of the minimum number

of components for current sensing. The sense current Ics

represents the inductor current IL and will be used in the

PFC duty modulation to generate the multiplier voltage

Vm, Over−Power Limitation (OPL), and Over−Current

Protection. (Equation 11) would insist in the fact that it

provides the flexibility in the RSENSE choice and that it

allows to detect in−rush currents.

Over−Current Protection (OCP)

Over−Current Protection is reached when Ics is larger

than IS(OCP) (200 mA typical). The offset voltage of the CS

pin is typical 10 mV and it is neglected in the calculation.

Hence, the maximum OCP inductor current threshold

IL(OCP) is obtained in (Equation 20).

(eq. 20)

IL(OCP) +

RCSIS(OCP)

RSENSE +RCS

RSENSE @200 mA

When over−current protection threshold is reached, the

Drive Output of the device goes low. The device

automatically resumes operation when the inductor current

goes below the threshold.

Input Voltage Sense

The device senses the rms input voltage Vac by the

sensing scheme in Figure 45. Vbo senses the average

rectified input voltage Vin via the resistor divider. An

external capacitor CBO is to maintain the Vbo the average

value of Vin. Vbo is used for Brown−Out Protection, PFC

duty modulation and over−power limitation (OPL).

Brown−Out Protection

The device uses the Vbo signal to protect the PFC stage

from operating as the input voltage is lower than expected.

Re−formulate (Equation 9) to get (Equation 21). Refer to

Figure 45, Vin is different before and after the device

operating.

•Before the device operates, Vin is equal to the peak

value of rms input voltage, Vac. Hence Vbo is as

described in (Equation 21).

(eq. 21)

Vbo +RboL

RboL )RboU

(Vin)+RboL

RboL )RboU

ǸVac

•After device operates, Vin is the rectified sinusoidal

input voltage. Thanks to CBO, Vbo is the average of

rectified input voltage. Hence Vbo decays to 2/p of the

peak value of rms input voltage Vac as described in

(Equation 22).

(eq. 22)

Vbo +RboL

RboL )RboU

pVac

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Figure 45. Brown−Out Protection

-BO

RboL

RboU

CBO

Vbo

Vin

Vac +

−

VboH / VboL

VboH = 1.3 V, VboL = 0.7 V

After Device OperatesBefore Device Operates

Hence a larger hysteresis of the brown out comparator is

needed, which is 0.7 V typical in this device. When Vbo

goes below than VBOL (0.7 V typical), the device turns off

the Drive output and keeps it off till Vbo exceeds VBOH

(1.3 V typical). When the device awakes after an off−state

(Undervoltage lockout or shutdown), the default threshold

is VBOH.

Overpower Limitation (OPL)

This is a second OCP with a threshold that is line

dependent. Sense current Ics represents the inductor current

IL and hence represents the input current approximately.

Input voltage signal Vbo represents the rms input voltage.

The product (Ics ⋅ Vbo) represents an approximated input

power (IL ⋅ Vac). It is illustrated in Figure 46.

Figure 46. Over−Power Limitation

Current Mirror

>200 mVA?

OPL

RCS ICS CS

Vbo

RSENSE

Vin

ICS +IL

RSENSE

RCS

When the product (Ics ⋅ Vbo) is greater than a permissible

level 200 mVA, the device turns off the drive output so that

the input power is limited. The OPL is automatically

deactivated when the product (Ics ⋅ Vbo) is lower than the

200 mVA level. This 200 mVA level corresponds to the

approximated input power (IL ⋅ Vac) to be smaller than the

particular expression in (Equation 23).

(eq. 23)

IcsVbo t200 mVA

ǒIL

RSENSE

RCS Ǔ@ǒ22

ǸKBO

p@VacǓt200 mVA

IL@Vac tRCS @p

RSENSE @KBO @50 2

ǸmVA

Bias the Controller

It is recommended to add a typical 1 nF to 100 nF

decoupling capacitor next to the Vcc pin for proper

operation. When the NCP1654 operates in follower boost

mode, the PFC output voltage is not always regulated at a

particular level under all application range of input voltage

and load power. It is not recommended to make a

low−voltage bias supply voltage by adding an auxiliary

winding on the PFC boost inductor. Alternatively, it is

recommended to get the Vcc biasing supply from the

2nd−stage power conversion stage.

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Vcc Undervoltage LockOut (UVLO)

The device incorporates an Undervoltage Lockout block

to prevent the circuit from operating when Vcc is too low

in order to ensure a proper operation. An UVLO

comparator monitors Vcc pin voltage to allow the NCP1654

to operate when Vcc exceeds 10.5 V typically. The

comparator incorporates some hysteresis (1.5 V) to prevent

erratic operation as the Vcc crosses the threshold. When Vcc

goes below the UVLO comparator lower threshold (9 V

typically), the circuit turns off. It is illustrated in Figure 47.

After startup, the operating range is between 9 V and 20 V.

Figure 47. Vcc Undervoltage LockOut (UVLO)

VCC

ICC

OFF

State

<75 mA

VCC(ON)

VCC(OFF)

6 mA

Thermal Shutdown

An internal thermal circuitry disables the circuit gate

drive and then keeps the power switch off when the junction

temperature exceeds 150°C. The output stage is then

enabled once the temperature drops below typically 120°C

(i.e., 30°C hysteresis). The thermal shutdown is provided

to prevent possible device failures that could result from an

accidental overheating.

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Figure 48. Application Schematic − 300 W 65 kHz

Power Factor Correction Circuit

TB2

390 V

1.8 M

180 mF, 450 V

D1 MSR860G

SPP20N60S5

10 k

R5 10

1N4148

TB3

+15 V +

22 mFC9

0.1 mFC10

100 pF

23.2 k

C12

2.2 mF

220 nF

NCP1654

47 k

1 nF

R11

82.5 k

0.47 mF

R10

R13

3.3 M

3.6 k

650 mH

L1 R6 0.1

0.1 mF

DB1

0.47 mF

2 x 6.8 mHL2

L3 150 mH

0.47 mF

5 A Fuse

AC Inlet

TB1

IC1

1234

8765

GND

DRV

VCC

Vcontrol

R12

12 k

−

GBU8J

8 A

600 V

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PACKAGE DIMENSIONS

SO−8

D SUFFIX

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45_

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over

time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under

its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

NCP1654/D

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