AK4399EQ - Asahi Kasei Microsystems Co., Ltd. (AKM)

[AK4399]

MS1005-E-03 2009/04

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GENERAL DESCRIPTION

AK4399 is a 32-bit DAC, which corresponds to DVD-Audio systems. An internal circuit includes newly

developed 32bit Digital Filter for better sound quality achieving low distortion characteristics and wide

dynamic range. The AK4399 has full differential SCF outputs, removing the need for AC coupling

capacitors and increasing performance for systems with excessive clock jitter. The AK4399 accepts

192kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including Blu-Ray,

DVD-Audio and SACD.

FEATURES

• 128x Over sampling

• Sampling Rate: 30kHz ∼ 216kHz

• 32Bit 8x Digital Filter (Minimum delay option GD=7/fs)

- Ripple: ±0.005dB, Attenuation: 100dB

• High Tolerance to Clock Jitter

• Low Distortion Differential Output

• DSD data input

• Digital De-emphasis for 32, 44.1, 48kHz sampling

• Soft Mute

• Digital Attenuator (255 levels and 0.5dB step)

• Mono Mode

• External Digital Filter Mode

• THD+N: -105dB

• DR, S/N: 123dB (Mono mode: 126dB)

• I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD

• Master Clock:

30kHz ~ 32kHz: 1152fs

30kHz ~ 54kHz: 512fs or 768fs

30kHz ~ 108kHz: 256fs or 384fs

108kHz ~ 216kHz: 128fs or 192fs

• Power Supply: 4.75 ∼ 5.25V

• Digital Input Level: TTL

• Package: 44pin LQFP

AK4399

High Performance 123dB Premium 32-Bit DAC

[AK4399]

MS1005-E-03 2009/04

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■ Block Diagram

MCL

K

SDATA/DSDL

LRCK/DSDR/WC

K

CSN/SMUTE

BICK/DCLK

CCLK/DEM0

CDTI/DEM1

DZFR

VSS1

VDDR

PDN AVDD

SCF

Clock

Divider

VSS3DVDD

DINR

DINL

BCK

CAD0 CAD1/DIF0 PSN DZFL/DIF1 DIF2

VSS2

VDDL

VCML

AOUTRN

VCMR

VREFHL

VREFLL

VREFLR

VREFLL

VSS4

AOUTLP

AOUTLN

AOUTRP

PCM

Data

Interface

DSD

Data

Interface

External

DF

Interface

8X

Interpolator

Control

Register

DATT

Soft Mute

ΔΣ

Modulator

Bias

Vref

Block Diagram

[AK4399]

MS1005-E-03 2009/04

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■ Ordering Guide

AK4399EQ −10 ∼ +70°C 44pin LQFP (0.8mm pitch)

AKD4399 Evaluation Board for AK4399

■ Pin Layout

AOUTLP

AOUTLN

34

VCML

33

35

NC 36

NC 37

NC 38

NC 39

VSS3 40

AVDD 41

MCLK 42

VSS4 43

NC 44

VSS2 32

VDDL 31

VREFHL 30

VREFLL 29

NC 28

VREFLR 27

VREFHR

26

VDDR 25

VSS1 24

AOUTRN 23

DVDD 1

PDN 2

BICK/DCL

K

3

SDATA/DSDL 4

LRCK/DSDR/WC

K

5

SMUTE/CSN 6

TST1/CAD0 7

DEM0/CCL

K

8

DEM1/CDTI 9

DIF0/CAD1 10

DIF1/DZFL 11

22

21

20

19

18

17

16

15

14

13

12

A

OUTRP

VCMR

NC

DINL

DINR

NC

BCK

TST2/DZFR

PSN

NC

DIF2

AK4399

Top View

[AK4399]

MS1005-E-03 2009/04

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PIN/FUNCTION

No. Pin Name I/O Function

1 DVDD - Digital Power Supply Pin, 4.75 ∼ 5.25V

2 PDN I

Power-Down Mode Pin

When at “L”, the AK4399 is in power-down mode and is held in reset.

The AK4399 should always be reset upon power-up.

BICK I Audio Serial Data Clock Pin in PCM Mode

3 DCLK I DSD Clock Pin in DSD Mode

SDATA I Audio Serial Data Input Pin in PCM Mode

4 DSDL I DSD Lch Data Input Pin in DSD Mode

LRCK I L/R Clock Pin in PCM Mode

DSDR I DSD Rch Data Input Pin in DSD Mode

5

WCK I Word Clock input pin

SMUTE I

Soft Mute Pin in Parallel Control Mode

When this pin is changed to “H”, soft mute cycle is initiated.

When returning “L”, the output mute releases.

6

CSN I Chip Select Pin in Serial Control Mode

TST1 I Test Pin in Parallel Control Mode (Internal pull-down pin)

7 CAD0 I Chip Address 0 Pin in Serial Control Mode (Internal pull-down pin)

DEM0 I De-emphasis Enable 0 Pin in Parallel Control Mode

8 CCLK I Control Data Clock Pin in Serial Control Mode

DEM1 I De-emphasis Enable 1 Pin in Parallel Control Mode

9 CDTI I Control Data Input Pin in Serial Control Mode

DIF0 I Digital Input Format 0 Pin in PCM Mode

10 CAD1 I Chip Address 1 Pin in Serial Control Mode

DIF1 I Digital Input Format 1 Pin in PCM Mode

11 DZFL O Lch Zero Input Detect Pin in Serial Control Mode

12 DIF2 I Digital Input Format 2 Pin in PCM Mode

13 NC - No internal bonding.

Connect to GND.

Note: All input pins except internal pull-up/down pins must not be left floating.

[AK4399]

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14 PSN I Parallel or Serial Select Pin (Internal pull-up pin)

“L”: Serial Control Mode, “H”: Parallel Control Mode

TST2 I

Test pin in Parallel Control Mode.

Connect to GND.

15

DZFR O Rch Zero Input Detect Pin in Serial Control Mode

16 BCK I Audio Serial Data Clock Pin (Internal pull-down pin)

17 NC - No internal bonding.

Connect to GND.

18 DINR I Rch Audio Serial Data Input Pin (Internal pull-down pin)

19 DINL I Lch Audio Serial Data Input Pin (Internal pull-down pin)

20 NC - No internal bonding.

Connect to GND.

21 VCMR - Right channel Common Voltage Pin,

Normally connected to VSS with a 10uF electrolytic cap.

22 AOUTRP O Rch Positive Analog Output Pin

23 AOUTRN O Rch Negative Analog Output Pin

24 VSS1 - Ground Pin

25 VDDR - Rch Analog Power Supply Pin, 4.75 ∼ 5.25V

26 VREFHR I Rch High Level Voltage Reference Input Pin

27 VREFLR I Rch Low Level Voltage Reference Input Pin

28 NC - No internal bonding.

Connect to GND.

29 VREFLL I Lch Low Level Voltage Reference Input Pin

30 VREFHL I Lch High Level Voltage Reference Input Pin

31 VDDL - Lch Analog Power Supply Pin, 4.75 ∼ 5.25V

32 VSS2 - Ground Pin

33 AOUTLN O Lch Negative Analog Output Pin

34 AOUTLP O Lch Positive Analog Output Pin

35 VCML - Left channel Common Voltage Pin,

Normally connected to VSS with a 10uF electrolytic cap.

36 NC - No internal bonding.

Connect to GND.

37 NC - No internal bonding.

Connect to GND.

38 NC - No internal bonding.

Connect to GND.

39 NC - No internal bonding.

Connect to GND.

40 VSS3 - Ground Pin

41 AVDD - Analog Power Supply Pin, 4.75 ∼ 5.25V

42 MCLK I Master Clock Input Pin

43 VSS4 - Ground Pin

44 NC - No internal bonding.

Connect to GND.

Note: All input pins except internal pull-up/down pins must not be left floating.

[AK4399]

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■ Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

(1) Parallel Mode (PCM Mode only)

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.

Analog AOUTRP, AOUTRN These pins must be open.

SMUTE This pin must be connected to VSS4.

TST1 This pin must be open.

Digital

TST2 This pin must be connected to VSS4.

(2) Serial Mode

1. PCM Mode

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.

Analog AOUTRP, AOUTRN These pins must be open.

DIF2 These pins must be connected to VSS4.

Digital DZFL, DZFR These pins must be open.

2. DSD Mode

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.

AOUTRP, AOUTRN These pins must be open.

Analog

DZFL, DZFR These pins must be open.

[AK4399]

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ABSOLUTE MAXIMUM RATINGS

(VSS1-4 =0V; Note 1)

Parameter Symbol min max Units

Power Supplies:

Analog

Digital

AVDD

VDDL/R

DVDD

−0.3

6.0

V

Input Current, Any Pin Except Supplies IIN - ±10 mA

Digital Input Voltage VIND −0.3 DVDD+0.3 V

Ambient Temperature (Power applied) Ta −10 70 °C

Storage Temperature Tstg −65 150 °C

Note 1. All voltages with respect to ground.

Note 2. VSS1-4 must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(VSS1-4 =0V; Note 1)

Parameter Symbol min typ max Units

Power Supplies

(Note 3)

Analog

Digital

AVDD

VDDL/R

DVDD

4.75

5.0

5.25

V

Voltage

Reference

(Note 4)

“H” voltage reference

“L” voltage reference

VREFH − VREFL

VREFHL/R

VREFLL/R

ΔVREF

AVDD−0.5

VSS

3.0

-

AVDD

-

AVDD

V

Note 1. All voltages with respect to ground.

Note 3. The power up sequence between AVDD, VDDL/R and DVDD is not critical.

Note 4. The analog output voltage scales with the voltage of (VREFH − VREFL).

AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5.

* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

[AK4399]

MS1005-E-03 2009/04

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ANALOG CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS;

Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;

Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 20; unless otherwise specified.)

Parameter min typ max Units

Resolution - - 24 Bits

Dynamic Characteristics (Note 5)

fs=44.1kHz

BW=20kHz

0dBFS

−60dBFS

-

-105

-60

98

-

dB

fs=96kHz

BW=40kHz

0dBFS

−60dBFS

-

102

-57

-

dB

THD+N

fs=192kHz

BW=40kHz

BW=80kHz

0dBFS

−60dBFS

102

-57

-54

-

dB

Dynamic Range (−60dBFS with A-weighted) (Note 6) 117 123 dB

S/N (A-weighted) (Note 7) 117 123 dB

Interchannel Isolation (1kHz) 110 120 dB

DC Accuracy

Interchannel Gain Mismatch - 0.15 0.3 dB

Gain Drift (Note 8) - 20 - ppm/°C

Output Voltage (Note 9) ±2.65 ±2.8 ±2.95 Vpp

Load Capacitance - - 25 pF

Load Resistance (Note 10) 1 - - kΩ

Power Supplies

Power Supply Current

Normal operation (PDN pin = “H”)

AVDD + VDDL/R

DVDD (fs ≤ 96kHz)

DVDD (fs = 192kHz)

-

60

43

46

90

-

70

mA

Power down (PDN pin = “L”) (Note 11)

AVDD+VDDL/R+DVDD

-

10

100

μA

Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.

Note 6. Figure 20 External LPF Circuit Example 2. 101dB for 16-bit data and 118dB for 20-bit data.

Note 7. Figure 20 External LPF Circuit Example 2. S/N does not depend on input data size.

Note 8. The voltage on (VREFH − VREFL) is held +5V externally.

Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R − VREFLL/R).

AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5.

Note 10. Regarding Load Resistance, AC load is 1kΩ (min) with a DC cut capacitor (Figure 20). DC load is 1.5k ohm

(min) without a DC cut capacitor (Figure 19). The load resistance value is with respect to ground. Analog

characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the capacitive load

must be minimized.

Note 11. In the power down mode. The P/S pin = DVDD, and all other digital input pins including clock pins

(MCLK, BICK and LRCK) are held VSS4.

[AK4399]

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SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

22.05

20.0

-

kHz

Stopband (Note 12) SB 24.1 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 100 dB

Group Delay (Note 13) GD - 36 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz - ±0.2 - dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

48.0

43.5

-

kHz

Stopband (Note 12) SB 52.5 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 95 dB

Group Delay (Note 13) GD - 36 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz - ±0.3 - dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

96.0

87.0

-

kHz

Stopband (Note 12) SB 105 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 90 dB

Group Delay (Note 13) GD - 36 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz - +0/−1 - dB

Note 12. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@±0.01dB), SB=0.546×fs.

Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of

both channels to input register to the output of analog signal.

[AK4399]

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MINIMUM DELAY FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“1”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

22.05

20.0

-

kHz

Stopband (Note 12) SB 24.1 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 100 dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 20.0kHz - ±0.2 - dB

MINIMUM DELAY FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“1”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

48.0

43.5

-

kHz

Stopband (Note 12) SB 52.5 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 95 dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 40.0kHz - ±0.3 - dB

MINIMUM DELAY FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“1”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

96.0

87.0

-

kHz

Stopband (Note 12) SB 105 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 90 dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 80.0kHz - +0/−1 - dB

[AK4399]

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DC CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)

Parameter Symbol min typ max Units

High-Level Input Voltage

Low-Level Input Voltage

VIH

VIL

2.4

-

0.8

V

High-Level Output Voltage (Iout=−100μA)

Low-Level Output Voltage (Iout=100μA)

VOH

VOL

DVDD−0.5

-

0.5

V

Input Leakage Current (Note 14) Iin - - ±10 μA

Note 14. The TST1/CAD0 and P/S pins have internal pull-up devices, nominally 100kΩ. Therefore The TST1/CAD0 and

P/S pins are not included.

[AK4399]

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SWITCHING CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)

Parameter Symbol min typ max Units

Master Clock Timing

Frequency

Duty Cycle

fCLK

dCLK

7.7

40

41.472

60

MHz

%

LRCK Frequency (Note 15)

1152fs, 512fs or 768fs

256fs or 384fs

128fs or 192fs

Duty Cycle

fsn

fsd

fsq

Duty

30

54

108

45

54

108

216

55

kHz

%

PCM Audio Interface Timing

BICK Period

1152fs, 512fs or 768fs

256fs or 384fs

128fs or 192fs

BICK Pulse Width Low

BICK Pulse Width High

BICK “↑” to LRCK Edge (Note 16)

LRCK Edge to BICK “↑” (Note 16)

SDATA Hold Time

SDATA Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

1/128fsn

1/64fsd

1/64fsq

30

20

ns

External Digital Filter Mode

BICK Period

BCK Pulse Width Low

BCK Pulse Width High

BCK “↑” to WCK Edge

WCK Edge to BCK “↑”

WCK Pulse Width Low

WCK Pulse Width High

DATA Hold Time

DATA Setup Time

tB

tBL

tBH

tBW

tWB

tWCK

tWCH

tDH

tDS

27

10

5

54

5

ns

DSD Audio Interface Timing

DCLK Period

DCLK Pulse Width Low

DCLK Pulse Width High

DCLK Edge to DSDL/R (Note 17)

tDCK

tDCKL

tDCKH

tDDD

1/64fs

160

−20

20

ns

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN High Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

80

50

150

50

ns

Reset Timing

PDN Pulse Width (Note 18)

tPD

150

ns

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Note 15. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4399 should be reset by the

PDN pin or RSTN bit.

Note 16. BICK rising edge must not occur at the same time as LRCK edge.

Note 17. DSD data transmitting device must meet this time.

Note 18. The AK4399 can be reset by bringing the PDN pin “L” to “H” upon power-up.

■ Timing Diagram

1/fCLK

tCLKL

VIH

tCLKH

MCLK VIL

dCLK=tCLKH x fCLK, tCLKL x fCLK

1/fs

VIH

LRCK VIL

tBCK

tBCKL

VIH

tBCKH

BICK VIL

1/fs

VIH

WCK VIL

tB

tBL

VIH

tBH

BCK VIL

Clock Timing

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tLRB

LRCK

VIH

BICK VIL

tSDS

VIH

SDATA VIL

tSDH

VIH

VIL

tBLR

Audio Interface Timing (PCM Mode)

VIH

DCLK VIL

tDDD

VIH

DSDL

DSDR VIL

tDCKHtDCKL

tDCK

Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)

VIH

DCLK VIL

tDDD

VIH

DSDL

DSDR VIL

tDCKHtDCKL

tDCK

tDDD

Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)

[AK4399]

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tCSS

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

WRITE Command Input Timing

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

D3 D2 D1 D0

tCSW

tCSH

WRITE Data Input Timing

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tPD

PDN VIL

Power Down & Reset Timing

tWB

WCK

VIH

BCK VIL

tDS

VIH

DATA VIL

tDH

VIH

VIL

tBW

External Digital Filter I/F mode

[AK4399]

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OPERATION OVERVIEW

■ D/A Conversion Mode

In serial mode, the AK4399 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls

PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,

PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4399

should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4399 performs for

only PCM data.

DP bit Interface

0 PCM

1 DSD

Table 1. PCM/DSD Mode Control

When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external digital filter

(EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXD bit controls the modes. When

switching internal and external digital filters, the AK4399 must be reset by RSTN bit. A Digital filter switching takes

2~3k/fs.

Ex DF bit Interface

0 PCM

1 EX DF I/F

Table 2. Digital Filter Control (DP bit = “0”)

■ System Clock

[1] PCM Mode

The external clocks, which are required to operate the AK4399, are MCLK, BICK and LRCK. MCLK should be

synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the

delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the initial master clock

is set to the appropriate frequency (Table 3). When external clocks are changed, the AK4399 should be reset by the PDN

pin or RSTN bit.

The AK4399 is automatically placed in reset state when MCLK and LRCK are stopped during a normal operation (PDN

pin =“H”), and the analog output becomes Hi-Z. When MCLK and LRCK are input again, the AK4399 exit reset state and

starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4399 is in

power-down mode until MCLK and LRCK are supplied.

The MCLK frequency corresponding to each sampling speed should be provided (Table 4).

MCLK Mode Sampling Rate

1152fs Normal 30kHz~32kHz

512fs 768fs Normal 30kHz~54kHz

256fs 384fs Double 30kHz~108kHz

128fs 192fs Quad 108kHz~216kHz

Table 3. Sampling Speed

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LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A

88.2kHz N/A N/A 22.5792 33.8688 N/A N/A N/A

96.0kHz N/A N/A 24.5760 36.8640 N/A N/A N/A

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A

Table 4. System Clock Example (Parallel Control Mode) (N/A: Not available)

MCLK= 256fs/384fs supports sampling rate of 30kHz~108kHz (Table 5). But, when the sampling rate is 30kHz~54kHz,

DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.

MCLK DR,S/N

256fs/384fs 120dB

512fs/768fs 123dB

Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)

[2] DSD Mode

The external clocks, which are required to operate the AK4399, are MCLK and DCLK. MCLK should be synchronized

with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.

The AK4399 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin =“H”),

and the analog output becomes Hi-Z. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations,

the AK4399 is in power-down mode until MCLK is supplied.

DCKS bit MCLK Frequency DCLK Frequency

0 512fs 64fs (default)

1 768fs 64fs

Table 6. System Clock (DSD Mode)

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■ Audio Interface Format

[1] PCM Mode

Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and selected by the

DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table 7. In all formats the serial data

is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and 16-bit

MSB justified formats by zeroing the unused LSBs. Settings should be made by DIF2-0 pins in parallel mode and DIF2-0

bits in serial mode.

Mode DIF2 DIF1 DIF0 Input Format BICK Figure

0 0 0 0 16bit LSB justified

≥ 32fs Figure 1

1 0 0 1 20bit LSB justified

≥ 48fs Figure 2

2 0 1 0 24bit MSB justified

≥ 48fs Figure 3 (default)

3 0 1 1 24bit I2S Compatible ≥ 48fs Figure 4

4 1 0 0 24bit LSB justified

≥ 48fs Figure 2

5 1 0 1 32bit LSB justified

≥ 64fs Figure 5

6 1 1 0 32bit MSB justified

≥64fs Figure 6

7 1 1 1 32bit I2S Compatible ≥ 64fs Figure 7

Table 7. Audio Interface Format

SDAT

A

BICK

LRCK

SDAT

A

15 14 6 5 4

BICK

0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1

3210 1514

(

32fs

)

(

64fs

)

014

115 16 17 31 0 1 14 15 16 17 31 0 1

15 14 0 15 14 0

Mode 0 Don’t care Don’t care

15:MSB, 0:LSB

Mode 0 15 14 6 5 4 3 2 1 0

Lch Data Rch Data

Figure 1. Mode 0 Timing

SDAT

A

LRCK

BICK

(

64fs

)

091 10 11 12 31 0 1 9 10 11 12 31 0 1

19 0 19 0

Mode 1 Don’t care Do n’t care

19:MSB, 0:LSB

SDAT

A

Mode 4 23:MSB, 0:LSB

20 19 0 20 19 0

Don’t care Don’t care

22 21 22 21

Lch Data Rch Data

8

23 23

8

Figure 2. Mode 1/4 Timing

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LRCK

BICK

(

64fs

)

SDAT

A

0221 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 1 0 Don’t care23

Lch Data Rch Data

23 30 2222423 30

22 1 0 Don’t care

23 2223

Figure 3. Mode 2 Timing

LRCK

BICK

(

64fs

)

SDAT

A

031 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 10Don’t care

23

Lch Data Rch Data

23 25 322423 25

22 1 0Don’t care23 23

Figure 4. Mode 3 Timing

LRCK

BICK(128fs)

SDATA

0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1

031 1

BICK(64fs)

SDATA

0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0

31

1

30 931 30 20 19 18 9 3120 19 18

31: MSB, 0:LSB

80

18 0

1

Lch Data Rch Data

031 1

Figure 5. Mode 5 Timing

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LRCK

BICK(128fs)

SDATA

0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0

31

1

30 031 30 12 11 10 0 3112 11 10

BICK(64fs)

SDATA

0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0

31

1

30 931 30 20 19 18 9 3120 19 18

31: MSB, 0:LSB

80

18 0

1

Lch Data Rch Data

Figure 6. Mode 6 Timing

LRCK

BICK(128fs)

SDATA

0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 0 1

31 031 13 12 11 0 13 12 11

BICK(64fs)

SDATA

0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0

0

1

31 9031 212019 9 021 20 19

31: MSB, 0:LSB

81

28 1

2

Lch Data Rch Data

Figure 7. Mode 7 Timing

[2] DSD Mode

In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can

invert the polarity of DCLK.

DCLK (64fs)

DCKB=1

DCLK (64fs)

DCKB=0

DSDL,DSDR

Normal

DSDL,DSDR

Phase M odulation

D1

D0 D1 D2

D0 D2 D3

D1 D2 D3

Figure 8. DSD Mode Timing

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[3] External Digital Filter Mode (EX DF I/F Mode)

DW indicates the number of BCK in one WCK cycle. The audio data is input by MCLK, BCK and WCK from the DINL

and DINR pins. Three formats are available (Table 9) by DIF2-0 bits setting. The data is latched on the rising edge of

BCK. The BCK and MCLK clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each

sampling speed are shown in Table 8.

The AK4399 is automatically placed in reset state when MCLK and WCK are stopped during a normal operation (PDN

pin =“H”), and the analog output becomes Hi-Z. When MCLK and WCK are input again, the AK4399 exit reset state and

starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4399 is in

power-down mode until MCLK and WCK are supplied.

MCLK&BCK [MHz]

Sampling

Speed[kHz] 128fs 192fs 256fs 384fs 512fs 768fs

WCK ECS

N/A N/A N/A N/A

22.5792 33.8688 16fs

44.1(30~54) 32 48 DW

0

N/A N/A 11.2896

16.9344 N/A 33.8688 8fs

44.1(30~54) 32 48 96 DW

1

N/A N/A

24.576 36.864 N/A N/A 8fs

96(54~108) 32 48 DW

0

12.288 18.432 N/A 36.864 N/A N/A 4fs

96(54~108) 32 48 96 DW

1

24.576 36.864 N/A N/A N/A N/A 4fs

192(108~216) 32 48 DW

0

N/A 36.864 N/A N/A N/A N/A 2fs

192(108~216) 96 DW

1

Table 8 System Clock Example (EX DF I/F mode) (N/A: Not available)

Mode DIF2 DIF1 DIF0 Input Format

0 0 0 0 16bit LSB justified

1 0 0 1 N/A

2 0 1 0 N/A

3 0 1 1 N/A

4 1 0 0 24bit LSB justified

5 1 0 1 32bit LSB justified

6 1 1 0 N/A

7 1 1 1 N/A

Table 9 Audio Interface Format (EX DF I/F mode) (N/A: Not available)

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BCK

WCK

DINL or

DINR 23 22

BCK

0 1 8 9 10 11 16 17 26 27 28 29 30 31 0 1

21 20 17 16

0 5 1 6 7 8 47 48 49 65 92 93 94 95 0 1

31 30

31 0

15 14 6 5 4 3 2 1 0

Don’t care Don’t care

DINL or

DINR 2 31

24

Don’t care Don’t care

BCK

0 5

1 6 7 8 23 24 25 17 44 45 46 47 0 1

31 0

Don’t care

DINL or

DINR 2 31Don’t care Don’t care Don’t car

e

1/16fs or 1/8fs or 1/4fs or 1/2fs

Figure 9 EX DF I/F Mode Timing

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■ D/A Conversion Mode Switching Timing

RSTN bit

D/A Data

D/A Mode

≥4/fs

≥0

PCM Data DSD Data

PCM Mode DSD Mode

Figure 10. D/A Mode Switching Timing (PCM to DSD)

RSTN bit

D/A Data

D/A Mode

≥4/fs

DSD Data PCM Data

DSD Mode PCM Mode

Figure 11. D/A Mode Switching Timing (DSD to PCM)

Note. The signal range is identified as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go beyond this duty

range at the SACD format book (Scarlet Book).

■ De-emphasis Filter

A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or

disabled with DEM1-0 pins or DEM1-0 bits. In case of 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is

always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are

switched.

DEM1 DEM0 Mode

0 0 44.1kHz

0 1 OFF (default)

1 0 48kHz

1 1 32kHz

Table 10. De-emphasis Control

■ Output Volume

The AK4399 includes channel independent digital output volumes (ATT) with 255 levels at linear step including MUTE.

These volume control is in front of the DAC and it can attenuate the input data from 0dB to –127dB and mute. When

changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions.

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■ Zero Detection (PCM mode, DSD mode)

The AK4399 has channel-independent zeros detect function. When the input data at each channel is continuously zeros

for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately return to “L”

if the input data of each channel is not zero after going to “H”. If the RSTN bit is “0”, the DZF pins of both channels go to

“H”. The DZF pins of both channels go to “L” at 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, the DZF

pins of both channels go to “H” only when the input data for both channels are continuously zeros for 8192 LRCK cycles.

The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels are always “L”.

The DZFB bit can invert the polarity of the DZF pin.

■ Mono Output

The AK4399 can select input/output for both output channels by setting the MONO bit and SELLR bit. This function is

available for any audio format.

MONO bit SELLR bit Lch Out Rch Out

0 0 Lch In Rch In

0 1 Rch In Lch In

1 0 Lch In Lch In

1 1 Rch In Rch In

Table 11 MONO Mode Output Select

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■ Soft Mute Operation

The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE bit set to “1”,

the output signal is attenuated by −∞ during ATT_DATA × ATT transition time from the current ATT level. When the

SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation

gradually changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before

attenuating −∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.

The soft mute is effective for changing the signal source without stopping the signal transmission.

SM U T E pin or

SMU TE bit

A

ttenuation

D ZF pin

ATT_Level

-∞

A

OUT

8192/fs

GD GD

(1)

(2)

(3)

(4)

(1)

(2)

Notes:

(1) ATT_DATA × ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in

Normal Speed Mode.

(2) The analog output corresponding to the digital input has group delay (GD).

(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued

and returned to ATT level by the same cycle.

(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for each channel

goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.

Figure 12. Soft Mute Function

■ System Reset

The AK4399 should be reset once by bringing the PDN pin = “L” upon power-up. It initializes register settings of the

device. The AK4399 exits this system reset (power-down mode) by MCLK and LRCK after the PDN pin = “H”, and the

analog block exits power-down mode. The digital block exits power-down mode after the internal counter counts MCLK

for 4/fs.

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■ Power ON/OFF timing

The AK4399 is placed in the power-down mode by bringing the PDN pin “L” and the registers are initialized. the analog

outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin signal, the analog output should be

muted externally if the click noise influences system application.

The DAC can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding

analog outputs go to VCML/R. As some click noise occurs at the edge of RSTN signal, the analog output should be muted

externally if click noise aversely affect system performance.

PDN pin

Power

Reset

Normal Operation

Clock In

MCLK,LRCK,BICK

DAC In

(Digital)

DAC Out

(Analog)

Ex ternal

Mute Mute ON

(6)

DZFL/DZFR

Don’t care

“0”data

GD

(2)

(4)

(5)

(7)

GD

(4)

Mute ON

“0”data

Don’t care

Internal

State

(3) (3)

(1)

Notes:

(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.

(2) The analog output corresponding to digital input has group delay (GD).

(3) Analog outputs are floating (Hi-Z) in power-down mode.

(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.

(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).

(6) Mute the analog output externally if click noise (3) adversely affect system performance

The timing example is shown in this figure.

(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”).

Figure 13. Power-down/up Sequence Example

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■ Reset Function

(1) RESET by RSTN bit = “0”

When the RSTN bit = “0”, the AK4399’s digital block is powered down, but the internal register values are not initialized.

In this time, the analog outputs go to VCML/R voltage and DZFL/DZFR pins are “H”. Figure 14 shows an example of

reset by RSTN bit.

Internal

State

RSTN bit

Digital Block

P

d

N ormal Operat ion

GD GD

“0 ” data

D/A Out

(Analog)

D/A I n

(Digital) (1) (3)

DZF

(3) (1)

(2)

Norm al Operation

2/fs(4)

Internal

RSTN bit

2~3/fs (5)3~4/fs (5)

(6)

Notes:

(1) The analog output corresponding to digital input has group delay (GD).

(2) Analog outputs settle to VCOM voltage.

(3) Small pop noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”

data is input.

(4) The DZF pins change to “H” when the RSTN bit becomes “0”, and return to “L” at 2/fs after RSTN bit becomes

“1”.

(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the

internal RSTN bit “1”.

(6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance

Figure 14. Reset Sequence Example 1

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(2) RESET by MCLK or LRCK/WCK Stop

The AK4399 is automatically placed in reset state when MCLK or LRCK is stopped during PDM mode (RSTN pin

=“H”), and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4399 exits reset state

and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. In DSD mode the AK4399 is in

reset state when MCLK is stopped, and it is in reset state when MCLK and WCK are stopped in external digital filter

mode.

N ormal Operat ion

Internal

State

Digital Circ uit Pow er-dow n Normal Operation

GD GD

D/A Out

(Analog)

D/A In

(Digital)

Clock In

MCLK, BICK, LRCK

(2)

(3)

External

MUTE (6)

(5)

(2)

M CLK, BICK, LRCK S to p

RS T B pin

Power-down

(4) (4)

(4)

Hi-Z

(6)

(5)

(1)

AVDD pin

DV DD pin

(6)

Notes:

(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.

(2) The analog output corresponding to digital input has group delay (GD).

(3) The digital data can be stopped. Click noise after MCLK, BICK and LRCK are input again can be reduced by

inputting “0” data during this period.

(4) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK inputs. This

noise occurs even when “0” data is input.

(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset state (MCLK or LRCK is stopped).

(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown

in this figure.

Figure 15. Reset Sequence Example 2

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■ Register Control Interface

Pins (parallel control mode) or registers (serial control mode) can control the functions of the AK4399. In parallel control

mode, the register setting is ignored, and in serial control mode the pin settings are ignored. When the state of the PSN pin

is changed, the AK4399 should be reset by the PDN pin. The serial control interface is enabled by the PSN pin = “L”. In

this mode, pin settings must be all “L”. Internal registers may be written to through3-wire µP interface pins: CSN, CCLK

and CDTI. The data on this interface consists of Chip address (2-bits, C1/0), Read/Write (1-bit; fixed to “1”), Register

address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The AK4399 latches the data on the rising edge of CCLK,

so data should be clocked in on the falling edge. The writing of data is valid when CSN “↑”. The clock speed of CCLK is

5MHz (max).

Function Parallel Control Mode Serial Control Mode

Audio Format Y Y

De-emphasis Y Y

SMUTE Y Y

DSD Mode - Y

EX DF I/F - Y

Minimum delay Filter - Y

Digital Attenuator - Y

Table 12. Function List1 (Y: Available, -: Not available)

Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing circuit is

reset by the RSTN bit, but the registers are not initialized.

CDTI

CCLK

C1

012345678 9 10 11 12 13 14 15

D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3

CSN

C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)

R/W: READ/WRITE (Fixed to “1”, Write only)

A4-A0: Register Address

D7-D0: Control Data

Figure 16. Control I/F Timing

* The AK4399 does not support the read command.

* When the AK4399 is in power down mode (PDN pin = “L”) or the MCLK is not provided, a writing into the control

registers is prohibited.

* The control data can not be written when the CCLK rising edge is 15 times or less or 17 times or more during CSN is

“L”.

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MS1005-E-03 2009/04

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Function List

Function Default Address Bit PCM DSD Ex DF I/F

Attenuation Level 0dB 03H

04H

ATT7-0 Y Y Y

External Digital Filter I/F Mode Disable 00H EXDF Y - Y

Ex DF I/F mode clock setting 16fs(fs=44.1kHz) 00H ESC - - Y

Audio Data Interface Modes 24bit MSB justified 00H DIF2-0 Y - -

Data Zero Detect Enable Disable 01H DZFE Y Y -

Data Zero Detect Mode Separated 01H DZFM Y Y

Minimum delay Filter Enable Sharp roll-off filter 01H SD Y - -

De-emphasis Response OFF 01H DEM1-0 Y - -

Soft Mute Enable Normal Operation 01H SMUTE Y Y Y

DSD/PCM Mode Select PCM mode 02H DP Y Y -

Master Clock Frequency Select at

DSD mode

512fs 02H DCKS

- Y -

MONO mode Stereo mode select Stereo 02H MONO Y Y Y

Inverting Enable of DZF “H” active 02H DZFB Y Y -

The data selection of L channel and

R channel

R channel 02H SELLR Y Y Y

Table 13. Function List2 (Y: Available, -: Not available)

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■ Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 0 EXDF ECS 0 DIF2 DIF1 DIF0 RSTN

01H Control 2 DZFE DZFM SD 0 0 DEM1 DEM0 SMUTE

02H Control 3 DP 0 DCKS DCKB MONO DZFB SELLR 0

03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

Notes:

Data must not be written into addresses from 05H to 1FH.

When the PDN pin goes to “L”, the registers are initialized to their default values.

When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default

values.

When the state of the PSN pin is changed, the AK4399 should be reset by the PDN pin.

■ Register Definitions

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 0 EXDF ECS 0 DIF2 DIF1 DIF0 RSTN

Default 1 0 0 0 0 1 0 1

RSTN: Internal Timing Reset

0: Reset. All registers are not initialized.

1: Normal Operation (default)

When internal clocks are changed, the AK4399 should be reset by the PDN pin or RSTN bit.

DIF2-0: Audio Data Interface Modes (Table 7)

Initial value is “010” (Mode 2: 24-bit MSB justified).

ECS: Ex DF I/F mode clock setting (Table 8)

0: Disable: Internal Digital Filter mode (default)

1: Enable: External Digital Filter mode

EXDF: External Digital Filter I/F Mode (Serial mode only)

0: Disable: Internal Digital Filter mode (default)

1: Enable: External Digital Filter mode

DIF2-0: Audio Data Interface Modes (Table 7)

Initial value is “010” (Mode2: 24bit MSB justified)

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Control 2 DZFE DZFM SD 0 0 DEM1 DEM0 SMUTE

Default 0 0 0 0 0 0 1 0

SMUTE: Soft Mute Enable

0: Normal Operation (default)

1: DAC outputs soft-muted.

DEM1-0: De-emphasis Response (Table 10)

Initial value is “01” (OFF).

SD: Minimum delay Filter Enable

0: Sharp roll-off filter (default)

1: Minimum delay filter

DZFM: Data Zero Detect Mode

0: Channel Separated Mode (default)

1: Channel ANDed Mode

If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both

channels are continuously zeros for 8192 LRCK cycles.

DZFE: Data Zero Detect Enable

0: Disable (default)

1: Enable

Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are

always “L”.

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Control 3 DP 0 DCKS DCKB MONO DZFB SELLR 0

Default 0 0 0 0 0 0 0 0

SELLR: The data selection of L channel and R channel, when MONO mode

0: All channel output R channel data, when MONO mode. (default)

1: All channel output L channel data, when MONO mode.

It is enabled when MONO bit is “1”, and outputs Rch date to both channels when “0”,outputs Lch data to

both channels when “1”.

DZFB: Inverting Enable of DZF

0: DZF pin goes “H” at Zero Detection (default)

1: DZF pin goes “L” at Zero Detection

MONO: MONO mode Stereo mode select

0: Stereo mode (default)

1: MONO mode

When MONO bit is “1”, MONO mode is enabled.

DCKB: Polarity of DCLK (DSD Only)

0: DSD data is output from DCLK falling edge. (default)

1: DSD data is output from DCLK rising edge.

DCKS: Master Clock Frequency Select at DSD mode (DSD only)

0: 512fs (default)

1: 768fs

DP: DSD/PCM Mode Select

0: PCM Mode (default)

1: DSD Mode

When D/P bit is changed, the AK4399 should be reset by RSTN bit.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

Default 1 1 1 1 1 1 1 1

ATT7-0: Attenuation Level

256 levels, 0.5dB step

Data Attenuation

FFH 0dB

FEH -0.5dB

FDH -1.0dB

: :

02H -126.5dB

01H -127.0dB

00H MUTE (-∞)

The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from

FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH

when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is

independent of soft mute function.

[AK4399]

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SYSTEM DESIGN

Figure 17 shows the system connection diagram. Figure 19, Figure 20 and Figure 21 show the analog output circuit

examples. The evaluation board (AKD4399) demonstrates the optimum layout, power supply arrangements and

measurement results.

DVDD

NC

1

PDN

44

2

BICK 3

SDATA 4

LRCK

5

CSN 6

CAD0 7

CCLK 8

CDTI

9

CAD1 10

DZFL 11

VSS4

43

MCL

K

42

AVDD

41

VSS3

40

NC

39

NC

38

NC

3

7

NC

36

VCML

3

5

AOUTLP

34

DIF2

12

NC

13

PSN

14

DZFR

1

5

BCK

16

NC

1

7

DINR

18

DINL

19

NC

20

VCMR

21

AOUTRP

22

33

32

31

30

29

28

27

26

25

24

23

AOUTLN

VSS2

VDDL

VREFHL

VREFLL

NC

VREFLR

VREFHR

VDDR

VSS1

AOUTRN

AK4399E Q

Top View

Analog5.0V

+ 10u 0.1u

Digital 5.0V

10u 0.1u

+

Ceramic Capacitor

+ Electrolytic Capacitor

+

0.1u

+

10u

+ 10u 0.1u

+

10u 0.1u

Lch

LPF

Rch

LPF Rch

Mute

Lch

Mute

Micro-

Controller

Rch Out

Lch Out

Reset & PD

64fs

Audio Data

fs

Master cloc

k

10u

+

10u

+

A

nalogDigital

Notes:

- Chip Address = “00”. BICK = 64fs, LRCK = fs

- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc.

- VSS1-4 must be connected to the same analog ground plane.

- When AOUT drives a capacitive load, some resistance should be connected in series between AOUT and the

capacitive load.

- All input pins except pull-down/pull-up pins should not be allowed to float.

Figure 17. Typical Connection Diagram (AVDD=VDDL/R=5V, DVDD=5V, Serial control mode)

[AK4399]

MS1005-E-03 2009/04

- 36 -

A nalog Ground Digital Ground

System

Controller

DVDD

N

C

1

PDN

44

2

BICK/DCLK3

SDATA/DSDL4

LRCK

/

DSDR/WCK5

SMUTE/CSN6

DFS0/CAD07

DEM0/CCLK8

DEM1/CDTI

9

DIF0/CAD110

DIF1/DZFL11

DIF2 12

33

AOUTLN

AK4399EQ

13

14

15

16

17

18

19

20

21

22

NC

PSN

ACKS/DZFR

BC K

NC

DINR

DINL

NC

VCM

R

AOUTRP

32 VSS2

31 VDDL

30 VREFHL

29 VREFLL

28 NC

27 VREFL

R

26 VREFHR

25 VDD

R

24 VSS1

23

A

OUTRN

VSS4 43

MCLK 42

AVDD 41

VSS

3

40

N

C

39

N

C

38

N

C

37

N

C

36

VCML 35

AOUTLP 34

Figure 18. Ground Layout

1. Grounding and Power Supply Decoupling

To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD

respectively. AVDD and VDDL/R are supplied from analog supply in system and DVDD is supplied from digital supply in

system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from the point with low impedance of

regulator etc. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be

connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as

possible to the supply pin.

2. Voltage Reference

The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is

normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R

should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency

noise. No load current may be drawn from VCML/R pin. All signals, especially clocks, should be kept away from the

VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4399.

3. Analog Outputs

The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R − VREFLL/R = 5V) centered around

AVDD/2. The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−.

If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of the external

summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive

full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for

000000H(@24bit).

The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio

passband. Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.

Figure 20 shows an example of differential outputs and LPF circuit example by three op-amps.

[AK4399]

MS1005-E-03 2009/04

- 37 -

1.5k 1.5k

390

1.5k 390

1.5k 1n

+Vop

1n

-Vop

AOUT-

AOUT+

2.2n Analog

Out

AK4399

Figure 19. External LPF Circuit Example 1 for PCM (fc = 99.2kHz, Q=0.704)

Frequency Response Gain

20kHz −0.011dB

40kHz −0.127dB

80kHz −1.571dB

Table 14. Frequency Response of External LPF Circuit Example 1 for PCM

330

100u 180

A

OUTL-

10k

3.9

n

1.2k

680

3.3n

6

4

3

2

7

10u

0.1u

0.1u 10u

10u

NJM5534D

330

100u 180

A

OUTL+

10k

3.9n

1.2k

680

3.3n

6

4

3

2

7

10u

0.1u

0.1

u

10u

NJM5534D 0.1u

+

NJM5534D

0.1u 10u

100

4

3

2

1.0n

620

560

7

+

-

+

-

+

-

+

1.0n

Lch

-15

+15

6

560

Figure 20. External LPF Circuit Example 2 for PCM

1

st Stage 2nd Stage Total

Cut-off Frequency 182kHz 284kHz -

Q 0.637 - -

Gain +3.9dB -0.88dB +3.02dB

20kHz -0.025 -0.021 -0.046dB

40kHz -0.106 -0.085 -0.191dB

Frequency

Response 80kHz -0.517 -0.331 -0.848dB

Table 15. Frequency Response of External LPF Circuit Example 2 for PCM

[AK4399]

MS1005-E-03 2009/04

- 38 -

It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass

filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4399 can achieve this filter

response by combination of the internal filter (Table 16) and an external filter (Figure 21).

Frequency Gain

20kHz −0.4dB

50kHz −2.8dB

100kHz −15.5dB

Table 16. Internal Filter Response at DSD Mode

1.8k 4.3k

1.0k

1.8k 1.0k

4.3k 270p

+Vop

270p

-Vop

AOUT-

AOUT+

3300p Analog

Out

2.0k

2200p

-

+

2.8Vpp

6.34Vpp

2.8Vpp

Figure 21. External 3rd Order LPF Circuit Example for DSD

Frequency Gain

20kHz −0.05dB

50kHz −0.51dB

100kHz −16.8dB

DC gain = 1.07dB

Table 17. 3rd Order LPF (Figure 21) Response

[AK4399]

MS1005-E-03 2009/04

- 39 -

4. Performance Plot

Figure 22 shows a FFT measurement result.

[Conditions]

Ta=25ºC; AVDD1/2=5.0V; VREFHL/R=5.0V, VREFLL/R=0V, DVDD=5.0V; VSS1=VSS2=VSS3=VSS4=0V;

fs=44.1kHz; Signal Frequency=1kHz, 0dBFS; LPF Configuration: Figure 20; Measured by Audio Precision, System Two.

-180

+0

-170

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

d

B

r

A

20 20k50 100 200 500 1k 2k 5k 10k

Hz

Figure 22. FFT (Blue: Left Channel, Red: Right Channel)

[AK4399]

MS1005-E-03 2009/04

- 40 -

PACKAGE

0.10

0.145

±

0.055

0.37

10.0

1.60max

1 11

23

33

44pin LQFP (Unit: mm)

10.0

12.0

34

44

0.80

22

12

12.0

0.10

±

0.05

0°∼7°

0.6

±

0.15

1.40

±

0.05

0.20 M

+0.08

–0.07

S

1.00

■ Material & Lead finish

Package molding compound: Epoxy, Halogen (bromine and chlorine) free

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

[AK4399]

MS1005-E-03 2009/04

- 41 -

MARKING

AK4399EQ

XXXXXXX

A

KM

1

1) Pin #1 indication

2) AKM Logo

3) Date Code: XXXXXXX(7 digits)

4) Marking Code: AK4399

5) Audio 4 pro Logo

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents

08/10/20 00 First Edition

09/02/13 01 Comment

Addition

1 “(Mono mode: 126dB)” was added.

39 4. Measuring Example was added.

Figure 22 was added.

09/02/25 02 Error Correct 37 Figure 19 was changed.

Table 14 was changed.

09/04/27 03 Description

Change

Short Delay Filter → Minimum Delay Filter

[AK4399]

MS1005-E-03 2009/04

- 42 -

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use

of any information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or

strategic materials.

z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or

other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use

approved with the express written consent by Representative Director of AKM. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or

for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or

perform may reasonably be expected to result in loss of life or in significant injury or damage to person or

property.

z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the

product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or

distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims

arising from the use of said product in the absence of such notification.