a Low Cost PC Temperature Monitor and Fan Control ASIC ADM1028 Preliminary Technical Data FEATURES GENERAL DESCRIPTION The ADM1028 is a low-cost temperature monitor and fan controller for microprocessor-based systems. The temperature of a remote sensor diode may be measured, allowing monitoring of processor temperature in single processor systems. An on-chip temp sensor monitors ambient system temperature. On-Chip Temperature Sensor External Temperature Measurement with Remote Diode Interrupt and Overtemperature Outputs Fault Tolerant Fan Control With Auto Hardware Trip Point Remote Reset and Power Down Functions LDCM Support System Management Bus (SMBus) Communications Standby Mode to Minimize Power Consumption Limit Comparison of all Monitored Values Measured values can be read out via the System Management Bus, and values for limit comparisons can be programmed in over the same serial bus. Y R A N L I M A I C L I E HN R P EC TA T DA The ADM1028 also contains a DAC for fan speed control. An automatic hardware temperature trip point is provided and the fan will be driven to full speed if it is exceeded. APPLICATIONS Network Servers and Personal Computers Microprocessor-Based Office Equipment Test Equipment and Measuring Instruments Finally, the chip has remote reset and power down functionality, allowing it to be remotely shutdown via the SMBus. The ADM1028's 3.0V to 5.5V supply voltage range, low supply current, and SMBus make it ideal for a wide range of applications. These include hardware monitoring applications in PCs, electronic test equipment, and office electronics. FUNCTIONAL BLOCK DIAGRAM V C C3 AUX 5 V C C3AU X POWER ON RESET 10k V R_OFF 13 16 SDA SERIAL BUS INTERFACE 15 SCL 8 FAN_SPD/TEST_IN REMOTE FUNCTION REGISTER R_RST 7 ADDRESS POINTER REGISTER AUXRST 3 RESET ADM 1028 RST 6 ANALOG OUTPUT REGISTER AND 8-BIT DAC ALERT STATUS REGISTER FAN_SPD SHUTOFF & R_OFF RESET VALUE AND LIMIT REGISTERS LIMIT COMPARATORS D+ 10 D- ADC ANALO G SIGNAL CONDITIONING 9 2.5V BANDGAP REFERENCE V C C3AU X 10k V INTERRUPT STATUS REGISTERS INT MASK REGISTER 14 INT THERMA/TEST_OUT 11 MASK GATING THERMB 12 CONFIGURATION REGISTER 2 4 GPI GND 1 FAN_OFF REV. PrD 05/2000 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1998 ADM1028-SPECIFICATIONS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted) PARAMETER Min Typ Max Units POWER SUPPLY Supply Voltage, VCC Supply Current, ICC 3.0 3.30 1.4 32 5.5 2.0 <100 V mA A 3 2 o C C o C 5 3 o TEMP.-TO-DIGITAL CONVERTER Internal Sensor Accuracy Resolution 1 External Diode Sensor Accuracy Resolution Remote Sensor Source Current Total Monitoring Cycle Time, tc 60 3.5 1 90 5.5 130 7.5 C C o C A A 1.0 1.4 s 2.5 3 3 V % % LSB LSB LSB mA mA o Test Conditions Interface Inactive, ADC Active Standby Mode +60OC# TA # +100oC +60OC# TA # +100oC High Level (D+ = D- +0.65V) Low Level (D+ = D- +0.65V) Y R A N L I M A I C L I E HN R P EC TA T DA ANALOG OUTPUT Output Voltage Range Total Unadjusted Error, TUE Full-Scale Error Zero Error Differential Non-Linearity, DNL Integral Non-Linearity Output Source Current Output Sink Current 0 1 2 1 1 2 1 IL = 2mA No Load Monotonic by Design VOLTAGE MONITOR THRESHOLDS Reset Threshold, VCC3AUX Hysteresis R_RST OUTPUT Reset Output Voltage, VOL Reset Output Pulse Width, tR_RST# VCC to Reset Delay, tD THERMA OUTPUT THERMA pull-up resistance 2.85 2.925 50 125 3.00 V mV 0.3 V 4000 s s 13 k 20 7 10 -2- Measured with Vcc falling. ISINK = 1.2mA; VCC = VTH(MAX) REV. PrD Preliminary Technical Data ADM1028 Specifications (Continued) PARAMETER Min Typ DIGITAL OUTPUT THERMA THERMA/TEST_OUT, R_OFF Output High Voltage, VOH 2.4 Output Low Voltage, VOL OPEN-DRAIN DIGITAL OUTPUTS (INT, THERMB, FAN_OFF, R_RST) Output Low Voltage, VOL High Level Output Leakage Current, IOH 0.1 OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Leakage Current, IOH 0.1 Max Units Test Conditions/Comments V V IOUT = 3.0mA 0.4 0.4 1 V A IOUT = -3.0mA VOUT = VCC 0.4 1 V A IOUT = -3.0mA VOUT = VCC 0.8 5 V (min) V (max) A mV Y R A N L I M A I C L I E HN R P EC TA T DA SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current Hysteresis DIGITAL INPUT LOGIC LEVELS (FAN_SPD/TEST_IN, GPI) Input High Voltage, VIH Input Low Voltage, VIL DIGITAL INPUT LEAKAGE CURRENT (ALL DIGITAL INPUTS) Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN SERIAL BUS TIMING Clock Frequency, fSCLK Bus Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA Stop Condition Setup Time, tSU;STO SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT 2.1 500 2.2 0.8 -1 -0.005 0.005 5 1 100 4.7 4.0 4.0 4.0 4.7 4.0 1000 300 250 300 V V A A pF kHz s s s s s s ns ns ns ns NOTES 1 Typicals are at TA=25C and represent most likely parametric norm. Standby current typ is measured with V CC = 3.3V. 3 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge. REV. PrD -3- VIN = VCC VIN = 0 See See See See See See See See See See See Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1 1 1 1 1 1 1 1 1 1 1 Preliminary Technical Data ADM1028 ABSOLUTE MAXIMUM RATINGS* THERMAL CHARACTERISTICS Positive Supply Voltage (VCC) 6.5 V Voltage on Digital Inputs except Therm -0.3V to 6.5V Voltage on Therm pin -0.3V to Vcc +0.3V Voltage on Any other Input -0.3V to VCC +0.3V or Output Pin Input Current at any pin 5mA Package Input Current 20mA Maximum Junction Temperature (T Jmax) 150 C Storage Temperature Range -65C to +150C Lead Temperature Soldering 10 sec +300C IR Reflow Peak temperature +220C ESD Rating (Human Body Model) 4000 V 16-Pin QSOP Package: JA = 105C/Watt, JC = 39C/Watt ORDERING GUIDE Model Temperature Range Package Description Package Option ADM1028ARQ 0C to +100C 16-Pin QSOP Package RQ-16 Y R A N L I M A I C L I E HN R P EC TA T DA *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional. Operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. tL O W ADM1028 PINOUT tF tR FAN_OFF 1 16 SDA GPI 2 15 SCL AUXRST 3 14 INT GND 4 ADM1028 V CC3AUX 5 TOP VIEW (Not to Scale) RST 6 11 THERMA/NTEST_OUT R_RST 7 10 D+ FAN_SPD/NTEST_IN 8 9 13 R_OFF 12 THERMB D- t H D;S T A S CL t H D;S T A S DA tH D;D AT t H IG H t S U;S T O t S U;D A T t S U;S T A tB UF P S S P Figure 1. Diagram for Serial Bus Timing -4- REV. PrD Preliminary Technical Data ADM1028 PIN FUNCTION DESCRIPTION PIN NO. MNEMONIC DESCRIPTION 1 FAN_OFF Digital Output (Open Drain) Fan Off Request. When asserted low this indicates a request to shut the fan off independent of the FAN_SPD output. When negated (output FET off) it indicates that the fan may be turned on. 2 GPI Digital Input (12V tolerant). This pin is a general purpose logic input with 12V tolerance. It can be programmed as an active high or active low input that sets bit 4 of the Interrupt Status Register. A voltage >2.2V on this pin, represents a logic "1" while a floating condition is interpreted as logic "0". 3 AUXRST Digital Input. This pin can be driven low as an input to reset the ADM1028. 4 GND GROUND. Power and signal ground. 5 VCC3AUX 6 RST 7 R_RST 8 FAN_SPD/TEST_IN Analog Output/Test Input. An active-high input that enables NAND boardlevel connectivity testing. Refer to section on NAND testing. Used as an analog output for fan speed control when NAND test is not selected. 9 D- Remote Thermal Diode Negative Input. This is the negative input (current sink) from the remote thermal diode. This also serves as the negative input into the A/D. 10 D+ 11 THERMA/TEST_OUT Digital Output (Open Drain with integrated VCC3AUX pull-up). An active low thermal overload output that indicates a violation of a temperature set point (over -temperature). The fan is on full-speed whenever this pin is asserted low. Acts as the output of the NAND Tree when the ADM1028 is in NAND Tree Test Mode. 12 THERMB Digital Output (Open Drain). This pin is a second THERM signal. It can be used to drive external circuitry with a different external pull-up supply rail. 13 R_OFF Digital Output or Open Drain with integrated VCC3AUX pull-up. Remote off (power down) output. This pin is driven high on receipt of a specific SMBus message. The pin (and its associated register bit) remain high until the RST input is asserted low. 14 INT Digital Output (Open Drain), System Interrupt Output. This signal indicates a violation of a set trip point. The output is enabled when Bit 1 of the Configuration Register is set to 1. The default state is disabled. 15 SCL Digital Input SMBus Clock 16 SDA Digital I/O(Open Drain) REV. PrD Y R A N L I M A I C L I E HN R P EC TA T DA POWER +3.3Vaux. Power source and voltage monitor input for power on reset. Digital Input. This pin can be pulled low externally to indicate to the ADM1028 that the main system power has been removed. The ADM1028 will shut off the FAN_SPD output and reset its R_OFF output. Digital Output (Open drain). This pin is a remote reset output which pulses low on receipt of a specific SMBus message. Remote Thermal Diode Positive Input. This is the positive input (current source) from the remote thermal diode. This serves as the positive input into the A/D. -5- SMBus bi-directional Data Preliminary Technical Data ADM1028 AWAITING DATA AWAITING DATA Y R A N L I M A I C L I E HN R P EC TA T DA Figure 2. Temperature Error vs. PC Board Track Resistance Figure 5. Pentium III Temperature Measurement vs. ADM1028 Reading Figure 3. Temperature Error vs. Power Supply Noise Frequency Figure 6. Temperature Error vs. Capacitance Between D+ and D- AWAITING DATA AWAITING DATA Figure 4. Temperature Error vs. Common-Mode Noise Frequency Figure 7. Standby Current vs. Clock Frequency -6- REV. PrD Preliminary Technical Data ADM1028 AWAITING DATA AWAITING DATA Y R A N L I M A I C L I E HN R P EC TA T DA AWAITING Figure 8. Temperature Error vs. Differential-Mode Noise Frequency Figure 10. Power-up Reset vs. Temperature DATA Figure 9. Standby Supply Current vs. Supply Voltage REV. PrD -7- Preliminary Technical Data ADM1028 SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device. FUNCTIONAL DESCRIPTION GENERAL DESCRIPTION The ADM1028 is a low-cost temperature monitor and fan controller for microprocessor-based systems. The temperature of a remote sensor diode may be measured, allowing monitoring of processor temperature in a singleprocessor system. An on-chip temperature sensor allows monitoring of system ambient temperature. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. If the R/W bit is a 0 then the master will write to the slave device. If the R/W bit is a 1 the master will read from the slave device. Measured values can be read out via the serial System Management Bus, and values for limit comparisons can be programmed in over the same serial bus. The ADM1028 also contains a DAC for fan speed control. An automatic hardware temperature trip point is provided for fault tolerant fan control and the fan will be driven to full speed if this is exceeded. Two interrupt outputs are provided, which will be asserted if the software or hardware limits are exceeded. Y R A N L I M A I C L I E HN R P EC TA T DA Finally, the chip has remote reset and shutdown capabilities. INTERNAL REGISTERS OF THE ADM1028 A brief description of the ADM1028's principal internal registers is given below. More detailed information on the function of each register is given in Tables 4 to 10. Configuration Register: Provides control and configuration. Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1028, the first byte of data is always a register address, which is written to the Address Pointer Register. Interrupt (INT) Status Register: This register provides status of each Interrupt event. Interrupt (INT) Mask Register: Allows masking of individual interrupt sources. Value and Limit Registers: The results of temperature measurements are stored in these registers, along with their limit values. Analog Output Register: The code controlling the analog output DAC is stored in this register. Alert Status Register: Indicates the status of the THERM signal and GPI pin. Remote Function Register: This register allows control of the R_RST and R_OFF outputs. SERIAL BUS INTERFACE Control of the ADM1028 is carried out via the serial bus. The ADM1028 is connected to this bus as a slave device, under the control of a master device, e.g. the 810 chipset. The ADM1028 has a 7-bit serial bus address. When the device is powered up, it will do so with a default serial bus address. The SMBus address for the ADM1028 is 0101110 binary. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA whilst the serial clock line 2. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the slave device.Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the case of the ADM1028, write operations contain either one or two bytes, and read operations contain one byte, and perform the following functions: To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, then the write operation contains a second data byte that is written to the register selected by the address pointer register. This is illustrated in figure 11a. The device address is sent over the bus followed by R/W set to 0. This is followed by two data bytes.The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register. When reading data from a register there is only one possibility: -8- REV. PrD Preliminary Technical Data ADM1028 1. The serial bus address is written to the device along with the address pointer register value. The ADM1028 should then acknowledge the write by pulling SDA low during the 9th clock pulse. The master does not generate a STOP condition but issues a new START condition. The serial bus address is again sent but with the R/W bit high indicating a READ operation. The ADM1028 will then return the data from the selected register, and a No Acknowledge is generated to signify the end of the read operation. The master will then initiate a STOP condition to end the transaction and release the SMBus. output of this sensor and outputs the temperature data in 8-bit two's complement format. The format of the temperature data is shown in Table 2. EXTERNAL TEMPERATURE MEASUREMENT The ADM1028 can measure the temperature of an external diode sensor or diode-connected transistor, connected to pins 9 and 10. Pins 9 and 10 are a dedicated temperature input channel. The default functions of pins Pins 11 and 12 are as THERM outputs to indicate overtemperature conditions. The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about -2mV/oC.Unfortunately, the absolute value of Vbe, varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass-production. In figures 11a & 11b, the serial bus address is shown as the default value 01011(A1)(A0), where A1 and A0 are the lowest two bits of the device SMBus address. Y R A N L I M A I C L I E HN R P EC TA T DA TEMPERATURE MEASUREMENT SYSTEM The technique used in the ADM1028 is to measure the change in Vbe when the device is operated at two different currents. INTERNAL TEMPERATURE MEASUREMENT The ADM1028 contains an on-chip bandgap temperature sensor. The on-chip ADC performs conversions on the 1 9 SCL 0 SDA This is given by: 1 0 S T AR T BY MASTER 1 1 A1 A0 1 D7 R /W D6 D5 D4 D3 9 D2 D1 D0 ACK. BY ADM 1028 ACK. BY ADM 1028 F R AM E 1 S E RI AL B US A DD RE S S B Y T E F R AM E 2 AD DR E S S P O I NT E R RE G I S T E R BY T E 1 9 S C L (CO NT I NU E D ) S D A (C O N T IN U E D) D7 D6 D4 D5 D3 D2 D1 D0 STOP B Y MASTER ACK. BY ADM 1028 F R AM E 3 DAT A BY T E Figure 11a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register 1 9 1 9 SC L 0 SD A 1 0 1 1 A1 A0 D6 D7 R/W ST AR T BY M A ST E R D5 D4 D3 D2 D1 D0 ACK. BY ADM 1028 ACK. BY ADM 1028 FR AM E 1 SE RIAL B US A DD RE SS B YT E FR AM E 2 AD DR ES S P O I NT ER RE G I ST ER BY TE 1 9 9 1 SC L SD A 0 1 0 1 1 A1 ST AR T BY M A ST E R A0 D7 R/W D6 D5 D4 FRAM E 3 SE RI AL B US A DD RE SS B YT E D2 D1 FRAM E 4 DATA BY TE F RO M ADM 1028 -9- D0 NO AC K . BY M AS TE R Figure 11b. Reading Data from the ADM1028 REV. PrD D3 ACK. BY ADM 1028 ST O P B Y M A ST E R Preliminary Technical Data ADM1028 Vbe = KT/q x ln(N) +100 C 0110 0100 where: +125 C 0111 1101 K is Boltzmann's constant +127 C 0111 1111 q is charge on the carrier To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input. If the sensor is used in a very noisy environment, a capacitor of value up to 1000pF may be placed between the D+ and D- inputs to filter the noise. T is absolute temperature in Kelvins N is ratio of the two currents Figure 12 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor. To measure Vbe, the sensor is switched between operating currents of I and N x I. The resulting waveform is passed through a 65kHz lowpass filter to remove noise, thence to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a DC voltage proportional to Vbe. This voltage is measured by the ADC to give a temperature output in 8-bit two's complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. An external temperature measurement takes nominally 9.6ms. If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input. Y R A N L I M A I C L I E HN R P EC TA T DA TABLE 2. TEMPERATURE DATA FORMAT Temperature Digital Output -128 C 1000 0000 -125 C 1000 0011 -100 C 1001 1100 -75 C 1011 0101 -50 C 1100 1110 -25 C 1110 0111 -1 C 1111 1111 0 C 0000 0000 +1 C 0000 0001 +10 C 0000 1010 +25 C 0001 1001 +50 C 0011 0010 +75 C 0100 1011 LAYOUT CONSIDERATIONS Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken: 1. Place the ADM1028 as close as possible to the remote sensing diode. Provided that the worst noise sources such as clock generators, data/address buses and CRTs are avoided, this distance can be 4 to 8 inches. 2. Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. 3. Use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. V DD I N x I I B IA S V O UT+ D+ TO AD C RE M O TE SE N SIN G TR A NS IST O R DBI AS DI O D E VO UTLO W P AS S F IL TE R f c = 65 kHz Figure 12. ADM1028 Signal Conditioning -10- REV. PrD Preliminary Technical Data GND ADM1028 4. The op-amp may be powered from the +V rail alone. If it is powered from +V then the input common-mode range should include ground to accommodate the minimum output voltage of the DAC, and the output voltage should swing below 0.6V to ensure that the transistor can be turned fully off. 10 m il 10 m il . D+ 10 m il 10 m il D- 10 m il . 5. In all these circuits, the output transistor must have an ICMAX greater than the maximum fan current, and be capable of dissipating power due to the voltage dropped across it when the fan is not operating at fullspeed. 10 m il GND 10 m il . Figure 13. Arrangement of Signal Tracks 6. If the fan motor produces a large back e.m.f when switched off, it may be necessary to add clamp diodes to protect the output transistors in the event that the output goes from full-scale to zero very quickly. 4. Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/ solder joints are used, make sure that they are in both the D+ and D- path and at the same temperature. Y R A N L I M A I C L I E HN R P EC TA T DA Thermocouple effects should not be a major problem as 1oC corresponds to about 200V, and thermocouple voltages are about 3V/oC of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200V. FAULT TOLERANT FAN CONTROL 5. Place 0.1F bypass and 2200pF input filter capacitors close to the ADM1028. The ADM1028 incorporates a fault tolerant fan control capability that is tied to operation of the THERMA, THERMB outputs. It can override the setting of the analog output and force it to maximum to give full fan speed in the event of a critical overtemperature problem, even if, for some reason, this has not been handled by the system software. 6. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This will work up to about 6 to 12 feet. 7. For really long distances (up to 100 feet) use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND close to the ADM1028. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor C1 may be reduced or removed. In any case the total shunt capacitance should not exceed 1000pF. Cable resistance can also introduce errors. 1 series resistance introduces about 0.5oC error. ANALOG OUTPUT The ADM1028 has a single analog output (FAN_SPD) from an unsigned 8 bit DAC which produces 0 - 2.5V. The analog output register defaults to 00 during power-on reset, which produces minimum fan speed. The analog output may be amplified and buffered with external circuitry such as an op-amp and transistor to provide fan speed control. Suitable fan drive circuits are given in Figures 14a to 14e. When using any of these circuits, the following points should be noted: 1. All of these circuits will provide an output range from zero to almost +VFAN. 2. To amplify the 2.5V range of the analog output up to +VFAN, the gain of these circuits needs to be set as shown. Figure 14c shows how the FAN_OFF signal may be used (with any of the control circuits) to gate the fan on and off independent of the value on the FAN_SPD/TEST_IN pin. There are two temperature set point registers that will activate the fault tolerant fan control. One of these limits is programmable by the user and one is a hardware (readonly) register that will operate if the user does not program any limit. The fault tolerant fan control is activated if a limit is exceeded for three or more consecutive readings. These limits are separate from the normal high and low temperature limits for the INT output, which do not affect the fault tolerant fan control or THERM outputs. A hardware limit of 100oC is programmed in to the register at address 18h, for the remote diode Default THERM limit. This is the default limit and the analog output will be forced to full-scale if the remote sensor reads more than 100oC. This makes the fault tolerant fan control failsafe in that it will operate at this temperature even if the user has programmed no other limit, or in the event of a software malfunction. Similarly, the Default Internal Temp THERM limit held in register 17h, forces the analog output full-scale if the ambient temperature measured is more than 70oC. The user may override the default limits by programming a new limit into register 14h for the remote sensor and a new limit into register 13h for the internal sensor. The default value in register 14h is the same as for the readonly register (100oC), but it may be programmed with higher or lower values. Once registers 13h and 14h have been programmed, or if the defaults are acceptable, bit 3 of the configuration 3. Care must be taken when choosing the op-amp to ensure that its input common-mode range and output voltage swing are suitable. REV. PrD -11- Preliminary Technical Data ADM1028 +12V +5V R3 100k V FAN _SPD R4 100k V Q3 N D T452 P Q1 N DT452P A D8541 + R2 1 5k V 5V FA N R1 1 0k V R2 3.9k V FA N _S PD Q 1 /Q 2 M B T3 904 DUAL R5 5k V Y R A N L I M A I C L I E HN R P EC TA T DA R1 1k V Figure 14d. Discrete 12V Fan Drive Circuit with P-Channel MOSFET, SIngle Supply Figure 14a. 5V Fan Circuit with Op-Amp +1 2V R4 1kV FA N _ S PD A D 85 1 9 Q1 BD136 2SA968 R3 1kV + R2 3 9k V R5 100kV R4 100kV FAN_SPD R1 1 0k V R6 5k V Q1/Q2 MBT3904 DUAL +12V Q4 BD132 TIP32A R3 100V Q3 BC556 2N3906 R2 3.9k V R1 1k V Figure 14b. 12V Fan Circuit with Op-Amp and PNP Transistor Figure 14e. Discrete 12V Fan Drive Circuit with Bipolar Output Single Supply +12V R3 100kV FAN_S PD - Q1 NDT452P AD8519 + R2 3 9k V R1 10kV + 3 .3 V R4 1kV FAN_O FF Q2 M M FT3055V Figure 14c. 12V Fan Circuit with Op-Amp and P-Channel MOSFET -12- REV. PrD Preliminary Technical Data ADM1028 no longer generate an interrupt. However, the bits in the status register will be set as normal. register must be set to `1'. This bit is a write-once bit that can only be written to `1' and it has two effects: 1. it makes the values in registers 13h and 14h the active limits, and disables read-only registers 17h and 18h. INTERRUPT CLEARING 2. it locks the data into registers 13h and 14h, so that it cannot be changed until the lock bit is reset, either when AUXRST or RST is asserted, or a Power On Reset occurs. The Interrupt Status Register reflects out-of-limit conditions. The Status bits may be individually cleared by writing a "1" to the appropriate status bits. Writing a "1" to bits 1 & 2 cause software interrupts to be generated. Bit 4 (GPI) of the Interrupt Status Register reflects the current status of the GPI pin, and so cannot be cleared by writing to this bit. Once the hardware override of the analog output is triggered, it will only return to normal operation after three consecutive measurements that are 5 degrees lower than the set limit. The INT output is cleared with the INT_Enable bit, which is Bit 1 of the Configuration Register, without affecting the contents of the Interrupt (INT) Status Registers. Whenever FAN_SPD output is forced to full-scale, the FAN_OFF output is negated. Y R A N L I M A I C L I E HN R P EC TA T DA THE ADM1028 INTERRUPT SYSTEM The ADM1028 has three interrupt outputs, INT, THERMA and THERMB. These have different functions. INT responds to violations of software programmed temperature limits and its interrupt sources are maskable, as described in more detail later. Interrupts and status bits are only set if a limit is exceeded for at least 3 consecutive conversions. Operation of the INT output is illustrated in Figure 15. Assuming that the temperature starts off within the programmed limits and that temperature interrupt sources are not masked, INT will go low if the temperature measured by the external sensor goes outside the programmed high or low temperature limit for the sensor. INT also goes low whenever THERM is low. 100o C 90o C THERM OUTPUTS The THERMA, THERMB signals are functionally identical. These system overtemperature outputs will assert together when an overtemperature is detected. THERMA (pin 11) is an open drain digital output which has an integrated pullup resistor to VCC3AUX. THERMB is an open drain digital output, intended to drive external circuitry operating at a different supply voltage level. THERM OPERATING MODE THERM only responds to the "hardware" temperature limits at addresses 14h and 18h, not to the software programmed limits. The function of these registers was described earlier with regard to fault tolerant fan speed control. HA R D W A R E T R IP P O I NT 80o C HIGH LIMIT 70o C 5o Temp. 60o C TE M P 50o C LOW LIMIT 40o C THE R M * INT *INT cleared by software * P R O G RA M M E D VALU E logic re-armed here Once the interrupt has been cleared, it will not be reasserted even if the temperature remains outside the limit previously exceeded. However, INT will be re-armed if the temperature falls back within the set limits for 3 consecutive conversions. Once the INT function has been re-armed, it will then be re-asserted once a limit is exceeded for 3 consecutive conversions. Figure 16. Operation of THERM Outputs THERM will go low if the hardware temperature limit is exceeded for three consecutive measurements. It will remain low until the temperature falls 5 degrees below the limit for three consecutive measurements. While THERM is low, the analog output will go to FFh to boost a controlled fan to full speed and FAN_OFF will be negated. When the Fault Tolerant Fan Control state is exited, the analog FAN_SPD output returns to its previously programmed value, which may have been changed during the time that the FAN_SPD output was forced to FFh. INTERRUPT MASKING Any of the bits in the Interrupt Status Register can be masked out by setting the corresponding mask bit in the Interrupt Mask Register. That interrupt source will then REV. PrD P RE V IO US F AN S PE E D V AL UE AN A L O G OU TP U T THIGH interrupt Figure 15. Operation of INT Output FFh -13- Preliminary Technical Data ADM1028 INTERRUPT STRUCTURE POWER-ON RESET The Interrupt Structure of the ADM1028 is shown in more detail in Figure 17. As each measurement value is obtained and stored in the appropriate value register, the value and the limits from the corresponding limit registers are fed to the high and low limit comparators. The result of each comparison (1 = out of limit, 0 = in limit) is routed to the corresponding bit input of the Interrupt Status Register via a data demultiplexer, and used to set that bit high or low as appropriate. When the ADM1028 is powered up, it will initiate a power-on reset sequence when the supply voltage VCC3AUX rises above the power-on reset threshold, with registers being reset to their power-on values. Normal operation will begin when the supply voltage rises above the reset threshold. Registers whose power on values are not shown have power on conditions that are indeterminate (this includes the Value and Limit Registers). In most applications, usually the first action after power on would be to write limits into the Limit Registers. The Interrupt Mask Register has bits corresponding to each of the Interrupt Status Register Bits. Setting an Interrupt Mask Bit high forces the corresponding Status Bit output low, whilst setting an Interrupt Mask Bit low allows the corresponding Status Bit to be asserted. After masking, the status bits are all OR'd together to produce the INT output, which will pull low if any unmasked status bit goes high, i.e. when any measured value goes out of limit. Power on reset clears or initializes the following registers (the initialized values are shown in Table 4): - Configuration Register Y R A N L I M A I C L I E HN R P EC TA T DA - Interrupt Status Register - Interrupt Mask Register - Analog Output Register The INT output is enabled when Bit 1 of the Configuration Register (INT_Enable) is high. - Programmable Trip Point Registers The ADM1028 can also be reset by taking AUXRST low as an input. The above-mentioned registers will be reset to their default values and the ADC will remain inactive as long as AUXRST is below the reset threshold. Taking the RST pin low will cause the following registers to be reset. GENERAL PURPOSE LOGIC INPUT (GPI) Pin 2 is used as a general purpose logic input with 12V tolerance. The GPI input may be programmed to be active high or active low by clearing or setting bit 6 of the Configuration Register. The default value is active high. Bit 4 of the Interrupt Status register follows the state (or inverted state) of GPI and will generate an interrupt when it is set to 1, like any other input to the Interrupt Status Register. However, the GPI bit is not latched in the Status Register and always reflects the current state (or inverted state) of the GPI input. If it is 1 it will not be cleared by reading the Status Register. LOW LIMIT FLAG2 INT. THERM GPI EXT. TEMP EXT. THERM DIODE FAULT - DAC Output, Fan speed 0 1 2 3 4 5 IN T E RR U P T STATUS REGISTER 1 = OUT OF LIMIT FLAG1 Bit 3 of the Configuration Register (Programmable THERM Limit Lock Bit) MASK GATING X 8 6 7 STATUS BIT INT MASK BIT MASKING DATA FROM BUS 8 MASK BITS (SAME BIT ORDER AS STATUS REGISTER) INTERRUPT MASK REGISTER FROM VALUE AND LIMIT VALUE REGISTERS HI G H A N D LO W LI MI T CO M PA R A TO R S HIGH LIMIT DAT A DEM UL TI PL EX ER INT. TEMP - INT ENABLE CONFIGURATION REGISTER Figure 17. ADM1028 Interrupt Register Structure -14- REV. PrD Preliminary Technical Data ADM1028 INITIALIZATION (SOFT RESET) TABLE 3. TEST VECTORS Soft reset performs a similar, but not identical, function to power on reset. The Limit Registers remain unchanged. RST AUXRST GPI SDA SCL 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 Soft reset is accomplished by setting Bit 4 of the Configuration Register high. This Bit automatically clears after being set. Unlike clearing INT, where the temperature must fall back within the set limits for three conversions before the INT function is rearmed, the soft reset allows INT to be pulled low immediatey after the soft reset. NAND TREE TEST A NAND tree is provided in the ADM1028 for Automated Test Equipment (ATE) board level connectivity testing. The device is placed into NAND tree test mode by powering up with pin FAN_SPD/TEST_IN (pin 8) held high. This pin is sampled and its state at power-up is latched. If it is connected high, then the NAND tree test mode is invoked. NAND tree test mode will only be exited once the ADM1028 is powered down. Y R A N L I M A I C L I E HN R P EC TA T DA In NAND tree test mode, all digital inputs may be tested as illustrated in Table 3. THERMA/TEST_OUT will become the NAND tree output pin. The structure of the NAND Tree is shown in Figure 21. To perform a NAND Tree test, all pins are initially driven low. The test vectors set all inputs low, then oneby-one toggles them high (keeping them high). Exercising the test circuit with this "walking one" pattern, starting with the input closest to the output of the tree, cycling towards the farthest, causes the output of the tree to toggle with each input change. Allow for a typical propagation delay of 500ns. P O W E R -O N RESET C lk FA N_S P D / T E S T _ IN D Q LA TC H ENABLE RST AUXRST GPI THERM A/ TE S T_O UT SDA SCL Figure 21. NAND Tree CONFIGURING THE INTERRUPT On power-up, the Interrupt functionality of the device is disabled. The Configuration register (0x40) must be written to, in order to enable the Interrupt output. The INT_Enable bit (bit 1) of the Register should be set to 1. REV. PrD -15- THERMA Preliminary Technical Data ADM1028 TABLE4. ADM1028 REGISTERS Register Name Address A7 - A0 in hex Comments Value Registers 0x14 - 0x38 See Table 5 Company ID 0x3E This location will contain the company identification number. This register is read only. Revision 0x3F This location will contain the revision number of the part in the lower four bits of the register [3:0]. The upper four bits reflect the ADM1028 Version Number [7:4]. The first version is 1101. The next version of ADM1028 would be 1110, etc. For instance, if the stepping were A0 and this part is a ADM1028, then this register would read 1101 0000. This register is read only. Configuration Register Interrupt Status Register Interrupt Mask Register Manufacturer Test Remote function Alert Status Y R A N L I M A I C L I E HN R P EC TA T DA 0x40 See Table 6. Power on value = 0010 0001 0x41 See Table 7. Power on value = 0000 0000 0x43 See Table 8. Power on value = 0000 0000 0x44 - 0x4A Test Registers for manufacturer's use only. Do not write to these registers. 0x4B See Table 9. Power on value = 0000 0000 0x4C See Table 10. Power on value = 0000 0000 TABLE 5. REGISTERS 0X13- 0X3A VALUE REGISTERS Address Read/Write Description 0x13 Read/Write Programmable Internal Therm Automatic Trip Point - default 127 degrees C. This register can only be written to if the write once bit in the configuration register (0x40, bit 3) has not been set. 0x14 Read/Write Programmable Remote Thermal Diode Automatic Trip Point - default 100 degrees C. This register can only be written to if the write once bit in the configuration register (0x40, bit 3) has not been set. 0x15 Read/Write Test register for manufacturer's use only. Do not write to this register 0x17 Read Only Default Internal Therm Automatic Trip Point - default 70 degrees C Cannot be changed. Disabled when bit 3 of Config register is set 0x18 Read Only Default Remote Thermal Diode Automatic Trip Point - default 100 degrees C Cannot be changed. Disabled when bit 3 of Config register is set 0x19 Read/Write Analog Output, FAN_SPD (defaults to 0x00h) 0x26 Read Only External Remote Temperature Value 0x27 Read Only Internal Temperature Value 0x37 Read/Write External Remote Temperature High Limit 0x38 Read/Write External Remote Temperature Low Limit 0x39 Read/Write Internal Temperature High Limit - default 127 degrees C. 0x3A Read/Write Internal Temperature Low Limit -16- REV. PrD Preliminary Technical Data TABLE 6. REGISTER 0X40 BIT ADM1028 CONFIGURATION REGISTER POWER ON DEFAULT <7:0> = 21H Name R/W Description 0 START Read/Write Setting this bit to a "1" enables startup of ADM1028; clearing this bit to "0" places ADM1028 in standby mode. At startup temperature monitoring and limit checking functions begin. Note, all limit values should be programmed into ADM1028 prior to using the standard thermal interrupt mechanism based upon high and low limits. (Powerup default=1) 1 INT Enable Read/Write Setting this bit to a "1" enables the INT output. 1=Enabled 0=Disabled (Powerup Default = 0) 2 Reserved Read Only Reserved (default = 0) 3 Programmable Therm Limit Lock Bit Read/Write Once Setting this bit to a "1" will lock in the value set into the Programmable Remote Therm Limit Register (Value Register 0x14). Furthermore, bit is set, the values in the Default Remote Therm Limit Register (Value Register 0x18) will no longer have an effect on the THERM, FAN_SPD, or FAN-OFF outputs. This bit cannot be written again until after RST has been asserted. (Power-up default = 0) 4 Soft Reset 5 FAN OFF 6 7 REV. PrD Y R A N L I M A I C L I E HN R P EC TA T DA Read/Write Setting this bit to a "1"will restore powerup default values to the Configuration Register, Interrupt Status Register and Interrupt Mask Register. This also rearms INT structure but not the THERM structure. This bit automatically clears itself since the power on default is zero. Read/Write Setting this bit to a "1" will cause the FAN OFF pin to be floated. Clearing this bit to "0" will cause the FAN OFF pin to be driven low which requests that the fan be turned off. This bit will be unconditionally set if the THERM pin is ever asserted; once THERM is negated this bit must be returned to its prior state (prior to THERM assertion). Reading this bit reflects the state of the FAN-OFF output buffer. Due to the open-drain nature of this pin the value read does not represent the actual state of the external circuit connected to it. (Power up default =1) GPI Invert Read/Write Setting this bit to a "1" will invert the GPI input for the purpose of level detection and interrupt generation. Clearing this bit to "0" leaves the GPI input unmodified. (Powerup default=0) Reserved Read Only Reserved. (Powerup default = 0). -17- Preliminary Technical Data ADM1028 TABLE 7. REGISTER 0X41. INTERRUPT STATUS REGISTER. POWER ON DEFAULT <7:0> = 00H BIT NAME READ/WRITE DESCRIPTION 0 Int. Temp Error Read/Write `1' to clear A one indicates that one of the limits for the internal temperature sensor has been exceeded. 1 Flag 1 Read/Write This bit can be used as a general purpose flag with the capability of generating an interrupt. Writing a `1' to this bit causes it to be set to `1'. Writing a `0' clears this bit. 2 Flag 2 Read/Write This bit can be used as a general purpose flag with the capability of generating an interrupt. Writing a `1' to this bit causes it to be set to `1'. Writing a `0' clears this bit. 3 Int. THERM Read/Write `1' to clear A one indicates that the internal thermal overload (THERM) limit has been exceeded. 4 GPI Input Read Only A "1" indicates that the GPI pin is asserted. The polarity of the GPI pin is determined by GPI Invert (bit 6) in the Configuration Register. For example, if GPI Invert is cleared then this bit will be "1" when the GPI pin is high ("1"); this bit will be "0" when the GPI pin is low ("0"). If GPI Invert is set then this bit will be "1" when the GPI pin is low ("0"); this bit will be "0" when the GPI pin is high ("1"). Note that the state of GPI is not latched; this bit simply reflects the state or inverted state of the GPI pin. Note: if this bit is "1" reading this register will NOT clear it to "0." 5 Ext. Temp Error Read/Write `1' to clear A one indicates that one of the limits for the external temperature sensor has been exceeded. 6 Ext. THERM Read/Write `1' to clear A one indicates that the external thermal overload (THERM) limit has been exceeded. 7 Ext Diode Fault Read/Write `1' to clear A one indicates either a short- or open-circuit fault on the remote sensor diode. TABLE 8. REGISTER 0X43 BIT Y R A N L I M A I C L I E HN R P EC TA T DA INTERRUPT MASK REGISTER. POWER ON DEFAULT <7:0> = 00H Name Read/Write Description 0 Int Temp Error Read/Write A one disables the corresponding interrupt status bit for the INT output. 1 Flag 1 Mask Read/Write A one disables the corresponding interrupt status bit for the INT output. 2 Flag 2 Mask Read/Write A one disables the corresponding interrupt status bit for the INT output. 3 Int THERM Read/Write A one disables the corresponding interrupt status bit for the INT output. 4 GPI Mask Read/Write A one disables the corresponding interrupt status bit for the INT output. 5 Ext Temp Error Read/Write A one disables the corresponding interrupt status bit for the INT output. 6 Ext THERM Read/Write A one disables the corresponding interrupt status bit for the INT output. 7 Ext Diode Fault Read/Write A one disables the corresponding interrupt status bit for the INT output. -18- REV. PrD Preliminary Technical Data TABLE 9. REGISTER 0X4B BIT ADM1028 REMOTE FUNCTION REGISTER. POWER ON DEFAULT <7:0> = 00 H Name Read/Write Description 0 R_RST Read/Write Writing a "1" to this bit causes the R_RST output to be pulsed low for a minimum of 125s. This bit will self-clear to 0 when the R_RST pulse is complete. Writing a "0" to this bit has no effect. Reading this bit reflects the state of this register bit and not the state of the pin. The power-on default value is "0". 1 R_OFF Read/Write Writing a "1" to this bit causes the R_OFF output to be driven high. This bit will be cleared, and the output driven low, when RST is asserted. Writing a "0" to this bit has no effect. The power-on default value is "0". 2 Reserved Read/Write Reserved (default = 0) 3 Reserved Read/Write Reserved (default = 0) 4 Reserved Read/Write Reserved (default = 0) 5 Reserved Read/Write Reserved (default = 0) 6 Reserved Read/Write Reserved (default = 0) 7 Reserved Read/Write Reserved (default = 0) TABLE 10. REGISTER 0X4C BIT Y R A N L I M A I C L I E HN R P EC TA T DA ALERT STATUS REGISTER. POWER ON DEFAULT <7:0> = 00 H Name Read/Write Description 0 THERM Alert Read Only A one indicates that thee xternal thermal overload limit is currently exceeded. 1 GPI Alert Read Only This bit represents the logic level of the GPI pin if bit 6 of the Configuration Register is "0", or the inverse logic level of the GPI pin if bit 6 of the Configuration Register is "1". 2 Reserved Read Only Undefined 3 Reserved Read Only Undefined 4 Reserved Read Only Undefined 5 Reserved Read Only Undefined 6 Reserved Read Only Undefined 7 Reserved Read Only Undefined REV. PrD -19- Preliminary Technical Data ADM1028 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin QSOP Package (RQ-16) 0.197 (5.00) 0.189 (4.80) 9 16 0.244 (6.20) 0.157 (3.99) 0.228 (5.79) 0.150 (3.81) 1 8 P IN 1 0.069 (1.75) 0.059 (1.50) M AX 0.053 (1.35) Y R A N L I M A I C L I E HN R P EC TA T DA 0.010 (0.25) 0.004 (0.10) 0.025 (0.64) BS C 0.012 (0.30) 0.008 (0.20) S EAT ING P LAN E 0.010 (0.20) 0.007 (0.18) 88 08 0.050 (1.27) 0.016 (0.41) REF: JEDEC 0.150" SSOP - DRAWING NUMBER MO-137 -20- REV. PrD